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/Linux-v6.1/Documentation/devicetree/bindings/bus/
Dmvebu-mbus.txt65 pcie-mem-aperture = <0xe0000000 0x8000000>;
66 pcie-io-aperture = <0xe8000000 0x100000>;
73 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
87 0xSIAA0000 0x00oooooo
91 S = 0x0 for a MBus valid window
92 S = 0xf for a non-valid window (see below)
94 If S = 0x0, then:
99 If S = 0xf, then:
105 (S = 0x0), an address decoding window is allocated. On the other side,
106 entries for translation that do not correspond to valid windows (S = 0xf)
[all …]
/Linux-v6.1/arch/mips/include/asm/
Dinst.h25 #define I_JTARGET_SFT 0
26 #define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)
29 #define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)
32 #define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)
34 #define I_IMM_SFT 0
35 #define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
36 #define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)
39 #define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
42 #define MIPSInst_CACHESEL(x) ((MIPSInst(x) & 0x00030000) >> I_CACHESEL_SFT)
45 #define MIPSInst_RD(x) ((MIPSInst(x) & 0x0000f800) >> I_RD_SFT)
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/display/
Dallwinner,sun4i-a10-display-frontend.yaml63 port@0:
94 reg = <0x01e00000 0x20000>;
104 #size-cells = <0>;
108 #size-cells = <0>;
111 fe0_out_be0: endpoint@0 {
112 reg = <0>;
/Linux-v6.1/arch/arm/mach-davinci/
Dusb-da8xx.c23 #define DA8XX_USB0_BASE 0x01e00000
24 #define DA8XX_USB1_BASE 0x01e25000
102 [0] = {
Ddavinci.h31 #define DAVINCI_PLL1_BASE 0x01c40800
32 #define DAVINCI_PLL2_BASE 0x01c40c00
33 #define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01c41000
35 #define DAVINCI_SYSTEM_MODULE_BASE 0x01c40000
36 #define SYSMOD_VDAC_CONFIG 0x2c
37 #define SYSMOD_VIDCLKCTL 0x38
38 #define SYSMOD_VPSS_CLKCTL 0x44
39 #define SYSMOD_VDD3P3VPWDN 0x48
40 #define SYSMOD_VSCLKDIS 0x6c
41 #define SYSMOD_PUPDCTL1 0x7c
[all …]
Ddevices.c23 #define DAVINCI_I2C_BASE 0x01C21000
24 #define DAVINCI_ATA_BASE 0x01C66000
25 #define DAVINCI_MMCSD0_BASE 0x01E10000
26 #define DM355_MMCSD0_BASE 0x01E11000
27 #define DM355_MMCSD1_BASE 0x01E00000
28 #define DM365_MMCSD0_BASE 0x01D11000
29 #define DM365_MMCSD1_BASE 0x01D00000
36 0x800); in davinci_map_sysmod()
48 .end = DAVINCI_I2C_BASE + 0x40,
76 .end = DAVINCI_ATA_BASE + 0x7ff,
[all …]
/Linux-v6.1/arch/nios2/boot/dts/
D3c120_devboard.dts18 #size-cells = <0>;
20 cpu: cpu@0 {
23 reg = <0x00000000>;
38 altr,reset-addr = <0xc2800000>;
39 altr,fast-tlb-miss-addr = <0xc7fff400>;
40 altr,exception-addr = <0xd0000020>;
46 memory@0 {
48 reg = <0x10000000 0x08000000>,
49 <0x07fff400 0x00000400>;
52 sopc@0 {
[all …]
/Linux-v6.1/drivers/gpu/drm/nouveau/nvkm/subdev/top/
Dgk104.c35 for (i = 0; i < 64; i++) { in gk104_top_oneinit()
39 type = ~0; in gk104_top_oneinit()
40 inst = 0; in gk104_top_oneinit()
43 data = nvkm_rd32(device, 0x022700 + (i * 0x04)); in gk104_top_oneinit()
45 switch (data & 0x00000003) { in gk104_top_oneinit()
46 case 0x00000000: /* NOT_VALID */ in gk104_top_oneinit()
48 case 0x00000001: /* DATA */ in gk104_top_oneinit()
49 inst = (data & 0x3c000000) >> 26; in gk104_top_oneinit()
50 info->addr = (data & 0x00fff000); in gk104_top_oneinit()
51 if (data & 0x00000004) in gk104_top_oneinit()
[all …]
/Linux-v6.1/arch/arm64/boot/dts/ti/
Dk3-am62a7-sk.dts30 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
39 reg = <0x00 0x9e780000 0x00 0x80000>;
40 alignment = <0x1000>;
45 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
46 alignment = <0x1000>;
52 reg = <0x00 0x9c900000 0x00 0x01e00000>;
57 vmain_pd: regulator-0 {
103 pinctrl-0 = <&usr_led_pins_default>;
105 led-0 {
118 AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
[all …]
/Linux-v6.1/arch/arm/mach-ep93xx/
Dts72xx.c70 #define TS72XX_NAND_CONTROL_ADDR_LINE 22 /* 0xN0400000 */
71 #define TS72XX_NAND_BUSY_ADDR_LINE 23 /* 0xN0800000 */
82 bits = __raw_readb(addr) & ~0x07; in ts72xx_nand_hwcontrol()
83 bits |= (ctrl & NAND_NCE) << 2; /* bit 0 -> bit 2 */ in ts72xx_nand_hwcontrol()
85 bits |= (ctrl & NAND_ALE) >> 2; /* bit 2 -> bit 0 */ in ts72xx_nand_hwcontrol()
100 return !!(__raw_readb(addr) & 0x20); in ts72xx_nand_device_ready()
109 .offset = 0,
128 .chip_offset = 0,
139 .start = 0, /* filled in later */
140 .end = 0, /* filled in later */
[all …]
/Linux-v6.1/arch/arm64/boot/dts/allwinner/
Dsun50i-h5.dtsi11 #size-cells = <0>;
13 cpu0: cpu@0 {
16 reg = <0>;
84 reg = <0x01c00000 0x1000>;
91 reg = <0x00018000 0x1c000>;
94 ranges = <0 0x00018000 0x1c000>;
96 ve_sram: sram-section@0 {
99 reg = <0x000000 0x1c000>;
106 reg = <0x01c0e000 0x1000>;
117 reg = <0x01c15000 0x1000>;
[all …]
Dsun50i-a64.dtsi47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0>;
123 #clock-cells = <0>;
130 #clock-cells = <0>;
152 #size-cells = <0>;
163 simple-audio-card,dai-link@0 {
174 sound-dai = <&codec 0>;
196 polling-delay-passive = <0>;
197 polling-delay = <0>;
[all …]
/Linux-v6.1/drivers/net/wireless/broadcom/brcm80211/include/
Dchipcommon.h14 u32 chipid; /* 0x0 */
20 u32 otpstatus; /* 0x10, corerev >= 10 */
26 u32 intstatus; /* 0x20 */
30 u32 chipcontrol; /* 0x28, rev >= 11 */
31 u32 chipstatus; /* 0x2c, rev >= 11 */
34 u32 jtagcmd; /* 0x30, rev >= 10 */
40 u32 flashcontrol; /* 0x40 */
46 u32 broadcastaddress; /* 0x50 */
50 u32 gpiopullup; /* 0x58, corerev >= 20 */
51 u32 gpiopulldown; /* 0x5c, corerev >= 20 */
[all …]
/Linux-v6.1/include/soc/fsl/qe/
Dqe.h32 QE_CLK_NONE = 0,
131 return 0; in cpm_muram_dma()
226 return 0; in qe_alive_during_sleep()
270 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
283 __be32 traps[16]; /* Trap addresses, 0 == ignore */
327 #define BD_STATUS_MASK 0xffff0000
328 #define BD_LENGTH_MASK 0x0000ffff
336 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
337 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
338 #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
[all …]
/Linux-v6.1/arch/mips/include/asm/mips-boards/
Dbonito64.h42 #define BONITO_BOOT_BASE 0x1fc00000
43 #define BONITO_BOOT_SIZE 0x00100000
45 #define BONITO_FLASH_BASE 0x1c000000
46 #define BONITO_FLASH_SIZE 0x03000000
48 #define BONITO_SOCKET_BASE 0x1f800000
49 #define BONITO_SOCKET_SIZE 0x00400000
51 #define BONITO_REG_BASE 0x1fe00000
52 #define BONITO_REG_SIZE 0x00040000
54 #define BONITO_DEV_BASE 0x1ff00000
55 #define BONITO_DEV_SIZE 0x00100000
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/pci/
Dnvidia,tegra194-pcie.yaml81 - const: p2u-0
119 0: C0
128 0 : C0
231 bus@0 {
234 ranges = <0x0 0x0 0x0 0x8 0x0>;
239 reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
240 <0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
241 <0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
242 <0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
249 linux,pci-domain = <0>;
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/amdkfd/
Dkfd_int_process_v11.c39 * The 44-bit packet is mapped as {context_id1[7:0],context_id0[31:0]} plus
43 * Encoding type (0 = Auto, 1 = Wave, 2 = Error)
48 * - context_id0[24:0]
50 * Auto - only context_id0[8:0] is used, which reports various interrupts
51 * generated by SQG. The rest is 0.
52 * Wave - user data sent from m0 via S_SENDMSG (context_id0[23:0])
53 * Error - Error Type (context_id0[24:21]), Error Details (context_id0[20:0])
56 * S_SENDMSG and Errors. These are 0 for Auto.
60 SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x0,
66 SQ_INTERRUPT_ERROR_TYPE_EDC_FUE = 0x0,
[all …]
/Linux-v6.1/drivers/net/wireless/realtek/rtw89/
Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
/Linux-v6.1/arch/arm64/boot/dts/qcom/
Dsm6125.dtsi22 #clock-cells = <0>;
29 #clock-cells = <0>;
37 #size-cells = <0>;
39 CPU0: cpu@0 {
42 reg = <0x0 0x0>;
54 reg = <0x0 0x1>;
63 reg = <0x0 0x2>;
72 reg = <0x0 0x3>;
81 reg = <0x0 0x100>;
93 reg = <0x0 0x101>;
[all …]
/Linux-v6.1/drivers/macintosh/
Dwindfarm_pm91.c57 #define DBG(args...) do { } while(0)
83 #define FAILURE_FAN 0x01
84 #define FAILURE_SENSOR 0x02
85 #define FAILURE_OVERTEMP 0x04
153 if (hdr == 0) { in wf_smu_create_cpu_fans()
160 /* Get the FVT params for operating point 0 (the only supported one in wf_smu_create_cpu_fans()
168 tmax = 0x5e0000; /* 94 degree default */ in wf_smu_create_cpu_fans()
224 if (--st->ticks != 0) { in wf_smu_cpu_fans_tick()
251 if (temp > 0x4a0000) in wf_smu_cpu_fans_tick()
265 if (fan_cpu_main && wf_smu_failure_state == 0) { in wf_smu_cpu_fans_tick()
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dsun5i.dtsi56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0>;
97 #clock-cells = <0>;
104 #clock-cells = <0>;
119 size = <0x6000000>;
120 alloc-ranges = <0x40000000 0x10000000>;
135 reg = <0x01c00000 0x30>;
140 sram_a: sram@0 {
142 reg = <0x00000000 0xc000>;
[all …]
Dsun8i-a23-a33.dtsi91 #size-cells = <0>;
93 cpu0: cpu@0 {
96 reg = <0>;
112 #clock-cells = <0>;
120 #clock-cells = <0>;
136 reg = <0x01c00000 0x30>;
143 reg = <0x01d00000 0x80000>;
146 ranges = <0 0x01d00000 0x80000>;
148 ve_sram: sram-section@0 {
151 reg = <0x000000 0x80000>;
[all …]
Dsun4i-a10.dtsi111 #size-cells = <0>;
112 cpu0: cpu@0 {
115 reg = <0x0>;
166 #clock-cells = <0>;
173 #clock-cells = <0>;
199 size = <0x6000000>;
200 alloc-ranges = <0x40000000 0x10000000>;
214 reg = <0x01c00000 0x30>;
219 sram_a: sram@0 {
221 reg = <0x00000000 0xc000>;
[all …]
Dsun6i-a31.dtsi101 #size-cells = <0>;
103 cpu0: cpu@0 {
106 reg = <0>;
213 #clock-cells = <0>;
221 #clock-cells = <0>;
238 #clock-cells = <0>;
245 #clock-cells = <0>;
252 #clock-cells = <0>;
254 reg = <0x01c200d0 0x4>;
274 reg = <0x01c02000 0x1000>;
[all …]
/Linux-v6.1/drivers/staging/rtl8712/
Drtl871x_mp.c26 pmp_priv->curr_rateidx = 0; in _init_mp_priv_()
27 pmp_priv->curr_txpoweridx = 0x14; in _init_mp_priv_()
30 pmp_priv->check_mp_pkt = 0; in _init_mp_priv_()
31 pmp_priv->tx_pktcount = 0; in _init_mp_priv_()
32 pmp_priv->rx_pktcount = 0; in _init_mp_priv_()
33 pmp_priv->rx_crcerrpktcount = 0; in _init_mp_priv_()
54 for (i = 0; i < NR_MP_XMITFRAME; i++) { in init_mp_priv()
64 return 0; in init_mp_priv()
70 return 0; in free_mp_priv()
93 u32 cmd32 = 0, val32 = 0; in fw_iocmd_read()
[all …]

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