Lines Matching +full:0 +full:x01e00000

70 #define TS72XX_NAND_CONTROL_ADDR_LINE	22	/* 0xN0400000 */
71 #define TS72XX_NAND_BUSY_ADDR_LINE	23	/* 0xN0800000 */
82 		bits = __raw_readb(addr) & ~0x07;  in ts72xx_nand_hwcontrol()
83 		bits |= (ctrl & NAND_NCE) << 2;	/* bit 0 -> bit 2 */  in ts72xx_nand_hwcontrol()
85 		bits |= (ctrl & NAND_ALE) >> 2;	/* bit 2 -> bit 0 */  in ts72xx_nand_hwcontrol()
100 	return !!(__raw_readb(addr) & 0x20);  in ts72xx_nand_device_ready()
109 		.offset		= 0,
128 		.chip_offset	= 0,
139 		.start		= 0,			/* filled in later */
140 		.end		= 0,			/* filled in later */
162 		ts72xx_nand_resource[0].start = start;  in ts72xx_register_flash()
163 		ts72xx_nand_resource[0].end = start + SZ_16M - 1;  in ts72xx_register_flash()
175 #define TS72XX_RTC_INDEX_PHYS_BASE	(EP93XX_CS1_PHYS_BASE + 0x00800000)
176 #define TS72XX_RTC_DATA_PHYS_BASE	(EP93XX_CS1_PHYS_BASE + 0x01700000)
179 	DEFINE_RES_MEM(TS72XX_RTC_INDEX_PHYS_BASE, 0x01),
180 	DEFINE_RES_MEM(TS72XX_RTC_DATA_PHYS_BASE, 0x01),
193 #define TS72XX_WDT_CONTROL_PHYS_BASE	(EP93XX_CS2_PHYS_BASE + 0x03800000)
194 #define TS72XX_WDT_FEED_PHYS_BASE	(EP93XX_CS2_PHYS_BASE + 0x03c00000)
197 	DEFINE_RES_MEM(TS72XX_WDT_CONTROL_PHYS_BASE, 0x01),
198 	DEFINE_RES_MEM(TS72XX_WDT_FEED_PHYS_BASE, 0x01),
218 #define BK3_EN_SDCARD_PHYS_BASE         0x12400000
219 #define BK3_EN_SDCARD_PWR 0x0
220 #define BK3_DIS_SDCARD_PWR 0x0C
230 	pr_debug("%s: SD card pwr %s VDD:0x%x\n", __func__,  in bk3_mmc_spi_setpower()
257 		.bus_num		= 0,
258 		.chip_select		= 0,
286 #define TS73XX_FPGA_LOADER_BASE		0x03c00000
312 		.bus_num		= 0,
313 		.chip_select		= 0,
351 	.atag_offset	= 0x100,
364 	DEFINE_RES_MEM(EP93XX_I2S_PHYS_BASE, 0x100),
381 		.offset	= 0x00000000,
382 		.size		= 0x01e00000,
385 		.offset	= 0x01e00000,
386 		.size		= 0x05f20000
389 		.offset	= 0x07d20000,
390 		.size		= 0x002e0000,
415 	.atag_offset	= 0x100,