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Searched +full:- +full:refclk (Results 1 – 25 of 350) sorted by relevance

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/Linux-v6.1/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dpllgt215.c36 *P = info->vco1.max_freq / freq; in gt215_pll_calc()
37 if (*P > info->max_p) in gt215_pll_calc()
38 *P = info->max_p; in gt215_pll_calc()
39 if (*P < info->min_p) in gt215_pll_calc()
40 *P = info->min_p; in gt215_pll_calc()
42 lM = (info->refclk + info->vco1.max_inputfreq) / info->vco1.max_inputfreq; in gt215_pll_calc()
43 lM = max(lM, (int)info->vco1.min_m); in gt215_pll_calc()
44 hM = (info->refclk + info->vco1.min_inputfreq) / info->vco1.min_inputfreq; in gt215_pll_calc()
45 hM = min(hM, (int)info->vco1.max_m); in gt215_pll_calc()
50 N = tmp / info->refclk; in gt215_pll_calc()
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/Linux-v6.1/drivers/phy/ti/
Dphy-dm816x-usb.c1 // SPDX-License-Identifier: GPL-2.0-only
47 struct clk *refclk; member
55 otg->host = host; in dm816x_usb_phy_set_host()
57 otg->state = OTG_STATE_UNDEFINED; in dm816x_usb_phy_set_host()
65 otg->gadget = gadget; in dm816x_usb_phy_set_peripheral()
67 otg->state = OTG_STATE_UNDEFINED; in dm816x_usb_phy_set_peripheral()
77 if (clk_get_rate(phy->refclk) != 24000000) in dm816x_usb_phy_init()
78 dev_warn(phy->dev, "nonstandard phy refclk\n"); in dm816x_usb_phy_init()
81 regmap_update_bits(phy->syscon, phy->usb_ctrl, in dm816x_usb_phy_init()
86 regmap_read(phy->syscon, phy->usb_ctrl, &val); in dm816x_usb_phy_init()
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Dphy-ti-pipe3.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-ti-pipe3 - PIPE3 PHY driver.
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
171 struct clk *refclk; member
215 /* DRA75x TRM Table 26-17 Preferred USB3_PHY_RX SCP Register Settings */
241 /* DRA75x TRM Table 26-9 Preferred SATA_PHY_RX SCP Register Settings */
266 /* DRA75x TRM Table 26-62 Preferred PCIe_PHY_RX SCP Register Settings */
302 struct pipe3_dpll_map *dpll_map = phy->dpll_map; in ti_pipe3_get_dpll_params()
304 rate = clk_get_rate(phy->sys_clk); in ti_pipe3_get_dpll_params()
306 for (; dpll_map->rate; dpll_map++) { in ti_pipe3_get_dpll_params()
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/Linux-v6.1/Documentation/devicetree/bindings/usb/
Dsmsc,usb3503.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SMSC USB3503 High-Speed Hub Controller
10 - Dongjin Kim <tobetter@gmail.com>
15 - smsc,usb3503
16 - smsc,usb3503a
21 connect-gpios:
26 intn-gpios:
31 reset-gpios:
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Docteon-usb.txt7 - compatible: must be "cavium,octeon-5750-usbn"
9 - reg: specifies the physical base address of the USBN block and
12 - #address-cells: specifies the number of cells needed to encode an
15 - #size-cells: specifies the number of cells used to represent the size
18 - ranges: specifies the translation between child address space and parent
21 - clock-frequency: speed of the USB reference clock. Allowed values are
24 - cavium,refclk-type: type of the USB reference clock. Allowed values are
27 - refclk-frequency: deprecated, use "clock-frequency".
29 - refclk-type: deprecated, use "cavium,refclk-type".
33 The main node must have one child node which describes the built-in
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Ddwc3-cavium.txt4 - compatible: Should contain "cavium,octeon-7130-usb-uctl"
13 compatible = "cavium,octeon-7130-usb-uctl";
16 #address-cells = <0x00000002>;
17 #size-cells = <0x00000002>;
18 refclk-frequency = <0x05f5e100>;
19 refclk-type-ss = "dlmc_ref_clk0";
20 refclk-type-hs = "dlmc_ref_clk0";
23 compatible = "cavium,octeon-7130-xhci", "snps,dwc3";
25 interrupt-parent = <0x00000010>;
/Linux-v6.1/drivers/gpu/drm/i915/display/
Dintel_cdclk.c2 * Copyright © 2006-2017 Intel Corporation
82 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); in intel_cdclk_get_cdclk()
89 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); in intel_cdclk_set_cdclk()
95 return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config); in intel_cdclk_modeset_calc_cdclk()
101 return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk); in intel_cdclk_calc_voltage_level()
107 cdclk_config->cdclk = 133333; in fixed_133mhz_get_cdclk()
113 cdclk_config->cdclk = 200000; in fixed_200mhz_get_cdclk()
119 cdclk_config->cdclk = 266667; in fixed_266mhz_get_cdclk()
125 cdclk_config->cdclk = 333333; in fixed_333mhz_get_cdclk()
131 cdclk_config->cdclk = 400000; in fixed_400mhz_get_cdclk()
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Dintel_dpll.c1 // SPDX-License-Identifier: MIT
190 * the range value for them is (actual_value - 2).
231 /* LVDS 100mhz refclk limits. */
302 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
303 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
307 * divided-down version of it.
310 int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params() argument
312 clock->m = clock->m2 + 2; in pnv_calc_dpll_params()
313 clock->p = clock->p1 * clock->p2; in pnv_calc_dpll_params()
314 if (WARN_ON(clock->n == 0 || clock->p == 0)) in pnv_calc_dpll_params()
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Dintel_dpll.h1 /* SPDX-License-Identifier: MIT */
23 int vlv_calc_dpll_params(int refclk, struct dpll *clock);
24 int pnv_calc_dpll_params(int refclk, struct dpll *clock);
25 int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
42 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
/Linux-v6.1/Documentation/devicetree/bindings/pinctrl/
Dralink,mt7620-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/ralink,mt7620-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
20 const: ralink,mt7620-pinctrl
23 '-pins$':
26 '^(.*-)?pinmux$':
29 $ref: pinmux-node.yaml#
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/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dfsl,imx8-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Richard Zhu <hongxing.zhu@nxp.com>
13 "#phy-cells":
18 - fsl,imx8mm-pcie-phy
26 clock-names:
28 - const: ref
33 reset-names:
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Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
18 - ti,am64-wiz-10g
19 - ti,j7200-wiz-10g
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/Linux-v6.1/drivers/gpu/drm/gma500/
Dgma_display.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2006-2011 Intel Corporation
44 int target, int refclk,
49 void (*clock)(int refclk, struct gma_clock_t *clock);
50 const struct gma_limit_t *(*limit)(struct drm_crtc *crtc, int refclk);
83 extern const struct gma_limit_t *gma_limit(struct drm_crtc *crtc, int refclk);
84 extern void gma_clock(int refclk, struct gma_clock_t *clock);
89 struct drm_crtc *crtc, int target, int refclk,
Doaktrail_crtc.c1 // SPDX-License-Identifier: GPL-2.0-only
40 int refclk, struct gma_clock_t *best_clock);
44 int refclk, struct gma_clock_t *best_clock);
83 int refclk) in mrst_limit() argument
86 struct drm_device *dev = crtc->dev; in mrst_limit()
91 switch (dev_priv->core_freq) { in mrst_limit()
106 dev_err(dev->dev, "mrst_limit Wrong display type.\n"); in mrst_limit()
112 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
113 static void mrst_lvds_clock(int refclk, struct gma_clock_t *clock) in mrst_lvds_clock() argument
115 clock->dot = (refclk * clock->m) / (14 * clock->p1); in mrst_lvds_clock()
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Dcdv_intel_display.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2006-2011 Intel Corporation
24 int refclk, struct gma_clock_t *best_clock);
56 /* The single-channel range is 25-112Mhz, and dual-channel
57 * is 80-224Mhz. Prefer single channel as much as possible.
117 ret__ = -ETIMEDOUT; \
216 int pipe = gma_crtc->pipe; in cdv_dpll_set_clock_cdv()
271 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
287 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
289 if (clock->vco < 2250000) { in cdv_dpll_set_clock_cdv()
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/Linux-v6.1/drivers/phy/xilinx/
Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
26 #include <dt-bindings/phy/phy.h>
32 /* TX De-emphasis parameters */
103 /* Refclk selection parameters */
171 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
185 * struct xpsgtr_phy - representation of a lane
192 * @refclk: reference clock index
201 unsigned int refclk; member
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/Linux-v6.1/drivers/net/ethernet/arc/
Demac_rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * emac-rockchip.c - Rockchip EMAC specific glue layer
32 struct clk *refclk; member
39 u32 speed_offset = emac->soc_data->grf_speed_offset; in emac_rockchip_set_mac_speed()
55 err = regmap_write(emac->grf, emac->soc_data->grf_offset, data); in emac_rockchip_set_mac_speed()
77 .compatible = "rockchip,rk3036-emac",
81 .compatible = "rockchip,rk3066-emac",
85 .compatible = "rockchip,rk3188-emac",
95 struct device *dev = &pdev->dev; in emac_rockchip_probe()
103 if (!pdev->dev.of_node) in emac_rockchip_probe()
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/Linux-v6.1/arch/mips/bcm63xx/
Dclk.c33 if (clk->set && (clk->usage++) == 0) in clk_enable_unlocked()
34 clk->set(clk, 1); in clk_enable_unlocked()
39 if (clk->set && (--clk->usage) == 0) in clk_disable_unlocked()
40 clk->set(clk, 0); in clk_disable_unlocked()
92 if (clk->id == 0) in enetx_set()
401 return clk->rate; in clk_get_rate()
421 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
422 CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
438 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
439 CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
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/Linux-v6.1/Documentation/devicetree/bindings/mips/cavium/
Ductl.txt4 - compatible: "cavium,octeon-6335-uctl"
8 - reg: The base address of the UCTL register bank.
10 - #address-cells: Must be <2>.
12 - #size-cells: Must be <2>.
14 - ranges: Empty to signify direct mapping of the children.
16 - refclk-frequency: A single cell containing the reference clock
19 - refclk-type: A string describing the reference clock connection
24 compatible = "cavium,octeon-6335-uctl";
27 #address-cells = <2>;
28 #size-cells = <2>;
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/Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn32/
Ddcn32_dccg.c34 (dccg_dcn->regs->reg)
38 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
41 dccg_dcn->base.ctx
43 dccg->ctx->logger
148 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
157 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
166 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
175 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
190 /* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */
197 int req_dtbclk_khz = params->pixclk_khz / 4; in dccg32_set_dtbclk_dto()
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/Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn314/
Ddcn314_dccg.c1 // SPDX-License-Identifier: MIT
37 (dccg_dcn->regs->reg)
41 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
44 dccg_dcn->base.ctx
46 dccg->ctx->logger
151 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
160 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
169 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
178 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
193 /* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */
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/Linux-v6.1/drivers/net/ethernet/ti/
Dcpts.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/clk-provider.h>
32 #define cpts_read32(c, r) readl_relaxed(&c->reg->r)
33 #define cpts_write32(c, v, r) writel_relaxed(v, &c->reg->r)
37 return (event->high >> PORT_NUMBER_SHIFT) & PORT_NUMBER_MASK; in cpts_event_port()
42 return time_after(jiffies, event->tmo); in event_expired()
47 return (event->high >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; in event_type()
60 return -1; in cpts_fifo_pop()
69 list_for_each_safe(this, next, &cpts->events) { in cpts_purge_events()
72 list_del_init(&event->list); in cpts_purge_events()
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/Linux-v6.1/arch/arm/boot/dts/
Dberlin2cd.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
11 #include <dt-bindings/clock/berlin2.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 model = "Marvell Armada 1500-mini (BG2CD) SoC";
17 #address-cells = <1>;
18 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
30 compatible = "arm,cortex-a9";
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/Linux-v6.1/drivers/clk/berlin/
Dbg2.c1 // SPDX-License-Identifier: GPL-2.0
6 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
10 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/berlin2.h>
19 #include "berlin2-avpll.h"
20 #include "berlin2-div.h"
21 #include "berlin2-pll.h"
77 * - audio_fast_pll is unknown
78 * - audiohd_pll is unknown
79 * - video0_pll is unknown
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/Linux-v6.1/Documentation/devicetree/bindings/clock/
Dmarvell,berlin.txt5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 clock node should be a sub-node of the chip controller node. Marvell Berlin2
13 - compatible: must be "marvell,berlin2-clk" or "marvell,berlin2q-clk"
14 - #clock-cells: must be 1
15 - clocks: must be the input parent clock phandle
16 - clock-names: name of the input parent clock
17 Allowed clock-names for the reference clocks are
18 "refclk" for the SoCs oscillator input on all SoCs,
19 and SoC-specific input clocks for
26 compatible = "marvell,berlin2q-clk";
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