Lines Matching +full:- +full:refclk
1 // SPDX-License-Identifier: GPL-2.0-only
40 int refclk, struct gma_clock_t *best_clock);
44 int refclk, struct gma_clock_t *best_clock);
83 int refclk) in mrst_limit() argument
86 struct drm_device *dev = crtc->dev; in mrst_limit()
91 switch (dev_priv->core_freq) { in mrst_limit()
106 dev_err(dev->dev, "mrst_limit Wrong display type.\n"); in mrst_limit()
112 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
113 static void mrst_lvds_clock(int refclk, struct gma_clock_t *clock) in mrst_lvds_clock() argument
115 clock->dot = (refclk * clock->m) / (14 * clock->p1); in mrst_lvds_clock()
121 clock->dot, clock->m, clock->m1, clock->m2, clock->n, in mrst_print_pll()
122 clock->p1, clock->p2); in mrst_print_pll()
127 int refclk, struct gma_clock_t *best_clock) in mrst_sdvo_find_best_pll() argument
136 for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) { in mrst_sdvo_find_best_pll()
137 for (clock.n = limit->n.min; clock.n <= limit->n.max; in mrst_sdvo_find_best_pll()
139 for (clock.p1 = limit->p1.min; in mrst_sdvo_find_best_pll()
140 clock.p1 <= limit->p1.max; clock.p1++) { in mrst_sdvo_find_best_pll()
142 clock.p = clock.p1 * limit->p2.p2_slow; in mrst_sdvo_find_best_pll()
146 if (target_vco > limit->vco.max) in mrst_sdvo_find_best_pll()
149 if (target_vco < limit->vco.min) in mrst_sdvo_find_best_pll()
152 actual_freq = (refclk * clock.m) / in mrst_sdvo_find_best_pll()
154 freq_error = 10000 - in mrst_sdvo_find_best_pll()
157 if (freq_error < -min_error) { in mrst_sdvo_find_best_pll()
164 freq_error = -freq_error; in mrst_sdvo_find_best_pll()
180 * Returns a set of divisors for the desired target clock with the given refclk,
185 int refclk, struct gma_clock_t *best_clock) in mrst_lvds_find_best_pll() argument
193 for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) { in mrst_lvds_find_best_pll()
194 for (clock.p1 = limit->p1.min; clock.p1 <= limit->p1.max; in mrst_lvds_find_best_pll()
198 mrst_lvds_clock(refclk, &clock); in mrst_lvds_find_best_pll()
200 this_err = abs(clock.dot - target); in mrst_lvds_find_best_pll()
218 struct drm_device *dev = crtc->dev; in oaktrail_crtc_dpms()
221 int pipe = gma_crtc->pipe; in oaktrail_crtc_dpms()
222 const struct psb_offset *map = &dev_priv->regmap[pipe]; in oaktrail_crtc_dpms()
244 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
246 REG_WRITE_WITH_AUX(map->dpll, temp, i); in oaktrail_crtc_dpms()
247 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
250 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
252 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
255 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
257 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
263 temp = REG_READ_WITH_AUX(map->conf, i); in oaktrail_crtc_dpms()
265 REG_WRITE_WITH_AUX(map->conf, in oaktrail_crtc_dpms()
270 temp = REG_READ_WITH_AUX(map->cntr, i); in oaktrail_crtc_dpms()
272 REG_WRITE_WITH_AUX(map->cntr, in oaktrail_crtc_dpms()
276 REG_WRITE_WITH_AUX(map->base, in oaktrail_crtc_dpms()
277 REG_READ_WITH_AUX(map->base, i), i); in oaktrail_crtc_dpms()
296 temp = REG_READ_WITH_AUX(map->cntr, i); in oaktrail_crtc_dpms()
298 REG_WRITE_WITH_AUX(map->cntr, in oaktrail_crtc_dpms()
301 REG_WRITE_WITH_AUX(map->base, in oaktrail_crtc_dpms()
302 REG_READ(map->base), i); in oaktrail_crtc_dpms()
303 REG_READ_WITH_AUX(map->base, i); in oaktrail_crtc_dpms()
307 temp = REG_READ_WITH_AUX(map->conf, i); in oaktrail_crtc_dpms()
309 REG_WRITE_WITH_AUX(map->conf, in oaktrail_crtc_dpms()
311 REG_READ_WITH_AUX(map->conf, i); in oaktrail_crtc_dpms()
316 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
318 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
320 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
344 * or -1 if the panel fitter is not present or not in use
354 return -1; in oaktrail_panel_fitter_pipe()
364 struct drm_device *dev = crtc->dev; in oaktrail_crtc_mode_set()
367 int pipe = gma_crtc->pipe; in oaktrail_crtc_mode_set()
368 const struct psb_offset *map = &dev_priv->regmap[pipe]; in oaktrail_crtc_mode_set()
369 int refclk = 0; in oaktrail_crtc_mode_set() local
389 drm_mode_copy(&gma_crtc->saved_mode, mode); in oaktrail_crtc_mode_set()
390 drm_mode_copy(&gma_crtc->saved_adjusted_mode, adjusted_mode); in oaktrail_crtc_mode_set()
394 if (!connector->encoder || connector->encoder->crtc != crtc) in oaktrail_crtc_mode_set()
399 switch (gma_encoder->type) { in oaktrail_crtc_mode_set()
415 drm_object_property_get_value(&connector->base, in oaktrail_crtc_mode_set()
416 dev->mode_config.scaling_mode_property, &scalingType); in oaktrail_crtc_mode_set()
429 REG_WRITE_WITH_AUX(map->src, ((mode->crtc_hdisplay - 1) << 16) | in oaktrail_crtc_mode_set()
430 (mode->crtc_vdisplay - 1), i); in oaktrail_crtc_mode_set()
439 offsetX = (adjusted_mode->crtc_hdisplay - in oaktrail_crtc_mode_set()
440 mode->crtc_hdisplay) / 2; in oaktrail_crtc_mode_set()
441 offsetY = (adjusted_mode->crtc_vdisplay - in oaktrail_crtc_mode_set()
442 mode->crtc_vdisplay) / 2; in oaktrail_crtc_mode_set()
445 REG_WRITE_WITH_AUX(map->htotal, (mode->crtc_hdisplay - 1) | in oaktrail_crtc_mode_set()
446 ((adjusted_mode->crtc_htotal - 1) << 16), i); in oaktrail_crtc_mode_set()
447 REG_WRITE_WITH_AUX(map->vtotal, (mode->crtc_vdisplay - 1) | in oaktrail_crtc_mode_set()
448 ((adjusted_mode->crtc_vtotal - 1) << 16), i); in oaktrail_crtc_mode_set()
449 REG_WRITE_WITH_AUX(map->hblank, in oaktrail_crtc_mode_set()
450 (adjusted_mode->crtc_hblank_start - offsetX - 1) | in oaktrail_crtc_mode_set()
451 ((adjusted_mode->crtc_hblank_end - offsetX - 1) << 16), i); in oaktrail_crtc_mode_set()
452 REG_WRITE_WITH_AUX(map->hsync, in oaktrail_crtc_mode_set()
453 (adjusted_mode->crtc_hsync_start - offsetX - 1) | in oaktrail_crtc_mode_set()
454 ((adjusted_mode->crtc_hsync_end - offsetX - 1) << 16), i); in oaktrail_crtc_mode_set()
455 REG_WRITE_WITH_AUX(map->vblank, in oaktrail_crtc_mode_set()
456 (adjusted_mode->crtc_vblank_start - offsetY - 1) | in oaktrail_crtc_mode_set()
457 ((adjusted_mode->crtc_vblank_end - offsetY - 1) << 16), i); in oaktrail_crtc_mode_set()
458 REG_WRITE_WITH_AUX(map->vsync, in oaktrail_crtc_mode_set()
459 (adjusted_mode->crtc_vsync_start - offsetY - 1) | in oaktrail_crtc_mode_set()
460 ((adjusted_mode->crtc_vsync_end - offsetY - 1) << 16), i); in oaktrail_crtc_mode_set()
464 REG_WRITE_WITH_AUX(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | in oaktrail_crtc_mode_set()
465 ((adjusted_mode->crtc_htotal - 1) << 16), i); in oaktrail_crtc_mode_set()
466 REG_WRITE_WITH_AUX(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | in oaktrail_crtc_mode_set()
467 ((adjusted_mode->crtc_vtotal - 1) << 16), i); in oaktrail_crtc_mode_set()
468 REG_WRITE_WITH_AUX(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | in oaktrail_crtc_mode_set()
469 ((adjusted_mode->crtc_hblank_end - 1) << 16), i); in oaktrail_crtc_mode_set()
470 REG_WRITE_WITH_AUX(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | in oaktrail_crtc_mode_set()
471 ((adjusted_mode->crtc_hsync_end - 1) << 16), i); in oaktrail_crtc_mode_set()
472 REG_WRITE_WITH_AUX(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | in oaktrail_crtc_mode_set()
473 ((adjusted_mode->crtc_vblank_end - 1) << 16), i); in oaktrail_crtc_mode_set()
474 REG_WRITE_WITH_AUX(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | in oaktrail_crtc_mode_set()
475 ((adjusted_mode->crtc_vsync_end - 1) << 16), i); in oaktrail_crtc_mode_set()
482 crtc->helper_private; in oaktrail_crtc_mode_set()
483 crtc_funcs->mode_set_base(crtc, x, y, old_fb); in oaktrail_crtc_mode_set()
487 pipeconf = REG_READ(map->conf); in oaktrail_crtc_mode_set()
490 dspcntr = REG_READ(map->cntr); in oaktrail_crtc_mode_set()
504 refclk = is_sdvo ? 96000 : dev_priv->core_freq * 1000; in oaktrail_crtc_mode_set()
505 limit = mrst_limit(crtc, refclk); in oaktrail_crtc_mode_set()
506 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, in oaktrail_crtc_mode_set()
507 refclk, &clock); in oaktrail_crtc_mode_set()
511 clock.p1 = (1L << (clock.p1 - 1)); in oaktrail_crtc_mode_set()
512 clock.m -= 2; in oaktrail_crtc_mode_set()
513 clock.n = (1L << (clock.n - 1)); in oaktrail_crtc_mode_set()
524 fp = oaktrail_m_converts[(clock.m - MRST_M_MIN)] << 8; in oaktrail_crtc_mode_set()
538 adjusted_mode->clock / mode->clock; in oaktrail_crtc_mode_set()
542 (sdvo_pixel_multiply - in oaktrail_crtc_mode_set()
549 dpll |= clock.p1 << 16; // dpll |= (1 << (clock.p1 - 1)) << 16; in oaktrail_crtc_mode_set()
551 dpll |= (1 << (clock.p1 - 2)) << 17; in oaktrail_crtc_mode_set()
557 REG_WRITE_WITH_AUX(map->fp0, fp, i); in oaktrail_crtc_mode_set()
558 REG_WRITE_WITH_AUX(map->dpll, dpll & ~DPLL_VCO_ENABLE, i); in oaktrail_crtc_mode_set()
559 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_mode_set()
566 REG_WRITE_WITH_AUX(map->fp0, fp, i); in oaktrail_crtc_mode_set()
567 REG_WRITE_WITH_AUX(map->dpll, dpll, i); in oaktrail_crtc_mode_set()
568 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_mode_set()
572 /* write it again -- the BIOS does, after all */ in oaktrail_crtc_mode_set()
573 REG_WRITE_WITH_AUX(map->dpll, dpll, i); in oaktrail_crtc_mode_set()
574 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_mode_set()
578 REG_WRITE_WITH_AUX(map->conf, pipeconf, i); in oaktrail_crtc_mode_set()
579 REG_READ_WITH_AUX(map->conf, i); in oaktrail_crtc_mode_set()
582 REG_WRITE_WITH_AUX(map->cntr, dspcntr, i); in oaktrail_crtc_mode_set()
594 struct drm_device *dev = crtc->dev; in oaktrail_pipe_set_base()
597 struct drm_framebuffer *fb = crtc->primary->fb; in oaktrail_pipe_set_base()
598 int pipe = gma_crtc->pipe; in oaktrail_pipe_set_base()
599 const struct psb_offset *map = &dev_priv->regmap[pipe]; in oaktrail_pipe_set_base()
607 dev_dbg(dev->dev, "No FB bound\n"); in oaktrail_pipe_set_base()
614 start = to_psb_gem_object(fb->obj[0])->offset; in oaktrail_pipe_set_base()
615 offset = y * fb->pitches[0] + x * fb->format->cpp[0]; in oaktrail_pipe_set_base()
617 REG_WRITE(map->stride, fb->pitches[0]); in oaktrail_pipe_set_base()
619 dspcntr = REG_READ(map->cntr); in oaktrail_pipe_set_base()
622 switch (fb->format->cpp[0] * 8) { in oaktrail_pipe_set_base()
627 if (fb->format->depth == 15) in oaktrail_pipe_set_base()
637 dev_err(dev->dev, "Unknown color depth\n"); in oaktrail_pipe_set_base()
638 ret = -EINVAL; in oaktrail_pipe_set_base()
641 REG_WRITE(map->cntr, dspcntr); in oaktrail_pipe_set_base()
643 REG_WRITE(map->base, offset); in oaktrail_pipe_set_base()
644 REG_READ(map->base); in oaktrail_pipe_set_base()
645 REG_WRITE(map->surf, start); in oaktrail_pipe_set_base()
646 REG_READ(map->surf); in oaktrail_pipe_set_base()