Lines Matching +full:- +full:refclk
1 // SPDX-License-Identifier: MIT
190 * the range value for them is (actual_value - 2).
231 /* LVDS 100mhz refclk limits. */
302 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
303 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
307 * divided-down version of it.
310 int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params() argument
312 clock->m = clock->m2 + 2; in pnv_calc_dpll_params()
313 clock->p = clock->p1 * clock->p2; in pnv_calc_dpll_params()
314 if (WARN_ON(clock->n == 0 || clock->p == 0)) in pnv_calc_dpll_params()
316 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); in pnv_calc_dpll_params()
317 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); in pnv_calc_dpll_params()
319 return clock->dot; in pnv_calc_dpll_params()
324 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
327 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params() argument
329 clock->m = i9xx_dpll_compute_m(clock); in i9xx_calc_dpll_params()
330 clock->p = clock->p1 * clock->p2; in i9xx_calc_dpll_params()
331 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) in i9xx_calc_dpll_params()
333 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); in i9xx_calc_dpll_params()
334 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); in i9xx_calc_dpll_params()
336 return clock->dot; in i9xx_calc_dpll_params()
339 int vlv_calc_dpll_params(int refclk, struct dpll *clock) in vlv_calc_dpll_params() argument
341 clock->m = clock->m1 * clock->m2; in vlv_calc_dpll_params()
342 clock->p = clock->p1 * clock->p2 * 5; in vlv_calc_dpll_params()
343 if (WARN_ON(clock->n == 0 || clock->p == 0)) in vlv_calc_dpll_params()
345 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); in vlv_calc_dpll_params()
346 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); in vlv_calc_dpll_params()
348 return clock->dot; in vlv_calc_dpll_params()
351 int chv_calc_dpll_params(int refclk, struct dpll *clock) in chv_calc_dpll_params() argument
353 clock->m = clock->m1 * clock->m2; in chv_calc_dpll_params()
354 clock->p = clock->p1 * clock->p2 * 5; in chv_calc_dpll_params()
355 if (WARN_ON(clock->n == 0 || clock->p == 0)) in chv_calc_dpll_params()
357 clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), in chv_calc_dpll_params()
358 clock->n << 22); in chv_calc_dpll_params()
359 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); in chv_calc_dpll_params()
361 return clock->dot; in chv_calc_dpll_params()
365 * Returns whether the given set of divisors are valid for a given refclk with
372 if (clock->n < limit->n.min || limit->n.max < clock->n) in intel_pll_is_valid()
374 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) in intel_pll_is_valid()
376 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) in intel_pll_is_valid()
378 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) in intel_pll_is_valid()
382 if (clock->m1 <= clock->m2) in intel_pll_is_valid()
386 if (clock->p < limit->p.min || limit->p.max < clock->p) in intel_pll_is_valid()
388 if (clock->m < limit->m.min || limit->m.max < clock->m) in intel_pll_is_valid()
392 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) in intel_pll_is_valid()
397 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) in intel_pll_is_valid()
408 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in i9xx_select_p2_div()
412 * For LVDS just rely on its current settings for dual-channel. in i9xx_select_p2_div()
417 return limit->p2.p2_fast; in i9xx_select_p2_div()
419 return limit->p2.p2_slow; in i9xx_select_p2_div()
421 if (target < limit->p2.dot_limit) in i9xx_select_p2_div()
422 return limit->p2.p2_slow; in i9xx_select_p2_div()
424 return limit->p2.p2_fast; in i9xx_select_p2_div()
430 * refclk, or FALSE.
440 int target, int refclk, in i9xx_find_best_dpll() argument
444 struct drm_device *dev = crtc_state->uapi.crtc->dev; in i9xx_find_best_dpll()
452 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; in i9xx_find_best_dpll()
454 for (clock.m2 = limit->m2.min; in i9xx_find_best_dpll()
455 clock.m2 <= limit->m2.max; clock.m2++) { in i9xx_find_best_dpll()
458 for (clock.n = limit->n.min; in i9xx_find_best_dpll()
459 clock.n <= limit->n.max; clock.n++) { in i9xx_find_best_dpll()
460 for (clock.p1 = limit->p1.min; in i9xx_find_best_dpll()
461 clock.p1 <= limit->p1.max; clock.p1++) { in i9xx_find_best_dpll()
464 i9xx_calc_dpll_params(refclk, &clock); in i9xx_find_best_dpll()
470 clock.p != match_clock->p) in i9xx_find_best_dpll()
473 this_err = abs(clock.dot - target); in i9xx_find_best_dpll()
488 * refclk, or FALSE.
498 int target, int refclk, in pnv_find_best_dpll() argument
502 struct drm_device *dev = crtc_state->uapi.crtc->dev; in pnv_find_best_dpll()
510 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; in pnv_find_best_dpll()
512 for (clock.m2 = limit->m2.min; in pnv_find_best_dpll()
513 clock.m2 <= limit->m2.max; clock.m2++) { in pnv_find_best_dpll()
514 for (clock.n = limit->n.min; in pnv_find_best_dpll()
515 clock.n <= limit->n.max; clock.n++) { in pnv_find_best_dpll()
516 for (clock.p1 = limit->p1.min; in pnv_find_best_dpll()
517 clock.p1 <= limit->p1.max; clock.p1++) { in pnv_find_best_dpll()
520 pnv_calc_dpll_params(refclk, &clock); in pnv_find_best_dpll()
526 clock.p != match_clock->p) in pnv_find_best_dpll()
529 this_err = abs(clock.dot - target); in pnv_find_best_dpll()
544 * refclk, or FALSE.
554 int target, int refclk, in g4x_find_best_dpll() argument
558 struct drm_device *dev = crtc_state->uapi.crtc->dev; in g4x_find_best_dpll()
569 max_n = limit->n.max; in g4x_find_best_dpll()
571 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { in g4x_find_best_dpll()
573 for (clock.m1 = limit->m1.max; in g4x_find_best_dpll()
574 clock.m1 >= limit->m1.min; clock.m1--) { in g4x_find_best_dpll()
575 for (clock.m2 = limit->m2.max; in g4x_find_best_dpll()
576 clock.m2 >= limit->m2.min; clock.m2--) { in g4x_find_best_dpll()
577 for (clock.p1 = limit->p1.max; in g4x_find_best_dpll()
578 clock.p1 >= limit->p1.min; clock.p1--) { in g4x_find_best_dpll()
581 i9xx_calc_dpll_params(refclk, &clock); in g4x_find_best_dpll()
587 this_err = abs(clock.dot - target); in g4x_find_best_dpll()
618 return calculated_clock->p > best_clock->p; in vlv_PLL_is_optimal()
625 abs(target_freq - calculated_clock->dot), in vlv_PLL_is_optimal()
632 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { in vlv_PLL_is_optimal()
643 * refclk, or FALSE.
648 int target, int refclk, in vlv_find_best_dpll() argument
652 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_find_best_dpll()
653 struct drm_device *dev = crtc->base.dev; in vlv_find_best_dpll()
657 int max_n = min(limit->n.max, refclk / 19200); in vlv_find_best_dpll()
663 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { in vlv_find_best_dpll()
664 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { in vlv_find_best_dpll()
665 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; in vlv_find_best_dpll()
666 clock.p2 -= clock.p2 > 10 ? 2 : 1) { in vlv_find_best_dpll()
669 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { in vlv_find_best_dpll()
673 refclk * clock.m1); in vlv_find_best_dpll()
675 vlv_calc_dpll_params(refclk, &clock); in vlv_find_best_dpll()
701 * refclk, or FALSE.
706 int target, int refclk, in chv_find_best_dpll() argument
710 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_find_best_dpll()
711 struct drm_device *dev = crtc->base.dev; in chv_find_best_dpll()
722 * set to 2. If requires to support 200Mhz refclk, we need to in chv_find_best_dpll()
728 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { in chv_find_best_dpll()
729 for (clock.p2 = limit->p2.p2_fast; in chv_find_best_dpll()
730 clock.p2 >= limit->p2.p2_slow; in chv_find_best_dpll()
731 clock.p2 -= clock.p2 > 10 ? 2 : 1) { in chv_find_best_dpll()
737 refclk * clock.m1); in chv_find_best_dpll()
744 chv_calc_dpll_params(refclk, &clock); in chv_find_best_dpll()
766 int refclk = 100000; in bxt_find_best_dpll() local
769 crtc_state->port_clock, refclk, in bxt_find_best_dpll()
775 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; in i9xx_dpll_compute_fp()
780 return (1 << dpll->n) << 16 | dpll->m2; in pnv_dpll_compute_fp()
787 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_update_pll_dividers()
788 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_update_pll_dividers()
799 crtc_state->dpll_hw_state.fp0 = fp; in i9xx_update_pll_dividers()
800 crtc_state->dpll_hw_state.fp1 = fp2; in i9xx_update_pll_dividers()
807 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_compute_dpll()
808 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_compute_dpll()
822 dpll |= (crtc_state->pixel_multiplier - 1) in i9xx_compute_dpll()
835 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
836 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
838 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; in i9xx_compute_dpll()
839 WARN_ON(reduced_clock->p1 != clock->p1); in i9xx_compute_dpll()
841 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
842 WARN_ON(reduced_clock->p1 != clock->p1); in i9xx_compute_dpll()
845 switch (clock->p2) { in i9xx_compute_dpll()
859 WARN_ON(reduced_clock->p2 != clock->p2); in i9xx_compute_dpll()
864 if (crtc_state->sdvo_tv_clock) in i9xx_compute_dpll()
873 crtc_state->dpll_hw_state.dpll = dpll; in i9xx_compute_dpll()
876 u32 dpll_md = (crtc_state->pixel_multiplier - 1) in i9xx_compute_dpll()
878 crtc_state->dpll_hw_state.dpll_md = dpll_md; in i9xx_compute_dpll()
886 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i8xx_compute_dpll()
887 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i8xx_compute_dpll()
895 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()
897 if (clock->p1 == 2) in i8xx_compute_dpll()
900 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()
901 if (clock->p2 == 4) in i8xx_compute_dpll()
904 WARN_ON(reduced_clock->p1 != clock->p1); in i8xx_compute_dpll()
905 WARN_ON(reduced_clock->p2 != clock->p2); in i8xx_compute_dpll()
913 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)." in i8xx_compute_dpll()
930 crtc_state->dpll_hw_state.dpll = dpll; in i8xx_compute_dpll()
936 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in hsw_crtc_compute_clock()
956 if (!crtc_state->has_pch_encoder) in hsw_crtc_compute_clock()
957 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in hsw_crtc_compute_clock()
965 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in hsw_crtc_get_shared_dpll()
991 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in dg2_crtc_compute_clock()
998 return dpll->m < factor * dpll->n; in ilk_needs_fb_cb_tune()
1005 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ilk_update_pll_dividers()
1006 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_update_pll_dividers()
1014 dev_priv->display.vbt.lvds_ssc_freq == 100000) || in ilk_update_pll_dividers()
1018 } else if (crtc_state->sdvo_tv_clock) { in ilk_update_pll_dividers()
1030 crtc_state->dpll_hw_state.fp0 = fp; in ilk_update_pll_dividers()
1031 crtc_state->dpll_hw_state.fp1 = fp2; in ilk_update_pll_dividers()
1038 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ilk_compute_dpll()
1039 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_compute_dpll()
1051 dpll |= (crtc_state->pixel_multiplier - 1) in ilk_compute_dpll()
1073 * this on ILK at all since it has a fixed DPLL<->pipe mapping. in ilk_compute_dpll()
1080 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ilk_compute_dpll()
1082 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in ilk_compute_dpll()
1084 switch (clock->p2) { in ilk_compute_dpll()
1098 WARN_ON(reduced_clock->p2 != clock->p2); in ilk_compute_dpll()
1108 crtc_state->dpll_hw_state.dpll = dpll; in ilk_compute_dpll()
1114 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in ilk_crtc_compute_clock()
1118 int refclk = 120000; in ilk_crtc_compute_clock() local
1122 if (!crtc_state->has_pch_encoder) in ilk_crtc_compute_clock()
1127 drm_dbg_kms(&dev_priv->drm, in ilk_crtc_compute_clock()
1129 dev_priv->display.vbt.lvds_ssc_freq); in ilk_crtc_compute_clock()
1130 refclk = dev_priv->display.vbt.lvds_ssc_freq; in ilk_crtc_compute_clock()
1134 if (refclk == 100000) in ilk_crtc_compute_clock()
1139 if (refclk == 100000) in ilk_crtc_compute_clock()
1148 if (!crtc_state->clock_set && in ilk_crtc_compute_clock()
1149 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in ilk_crtc_compute_clock()
1150 refclk, NULL, &crtc_state->dpll)) in ilk_crtc_compute_clock()
1151 return -EINVAL; in ilk_crtc_compute_clock()
1153 ilk_compute_dpll(crtc_state, &crtc_state->dpll, in ilk_crtc_compute_clock()
1154 &crtc_state->dpll); in ilk_crtc_compute_clock()
1160 crtc_state->port_clock = crtc_state->dpll.dot; in ilk_crtc_compute_clock()
1161 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in ilk_crtc_compute_clock()
1173 if (!crtc_state->has_pch_encoder) in ilk_crtc_get_shared_dpll()
1181 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_compute_dpll()
1183 crtc_state->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | in vlv_compute_dpll()
1185 if (crtc->pipe != PIPE_A) in vlv_compute_dpll()
1186 crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in vlv_compute_dpll()
1190 crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | in vlv_compute_dpll()
1193 crtc_state->dpll_hw_state.dpll_md = in vlv_compute_dpll()
1194 (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; in vlv_compute_dpll()
1199 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_compute_dpll()
1201 crtc_state->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | in chv_compute_dpll()
1203 if (crtc->pipe != PIPE_A) in chv_compute_dpll()
1204 crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in chv_compute_dpll()
1208 crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; in chv_compute_dpll()
1210 crtc_state->dpll_hw_state.dpll_md = in chv_compute_dpll()
1211 (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; in chv_compute_dpll()
1220 int refclk = 100000; in chv_crtc_compute_clock() local
1222 if (!crtc_state->clock_set && in chv_crtc_compute_clock()
1223 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in chv_crtc_compute_clock()
1224 refclk, NULL, &crtc_state->dpll)) in chv_crtc_compute_clock()
1225 return -EINVAL; in chv_crtc_compute_clock()
1233 crtc_state->port_clock = crtc_state->dpll.dot; in chv_crtc_compute_clock()
1234 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in chv_crtc_compute_clock()
1245 int refclk = 100000; in vlv_crtc_compute_clock() local
1247 if (!crtc_state->clock_set && in vlv_crtc_compute_clock()
1248 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in vlv_crtc_compute_clock()
1249 refclk, NULL, &crtc_state->dpll)) { in vlv_crtc_compute_clock()
1250 return -EINVAL; in vlv_crtc_compute_clock()
1259 crtc_state->port_clock = crtc_state->dpll.dot; in vlv_crtc_compute_clock()
1260 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in vlv_crtc_compute_clock()
1268 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in g4x_crtc_compute_clock()
1272 int refclk = 96000; in g4x_crtc_compute_clock() local
1276 refclk = dev_priv->display.vbt.lvds_ssc_freq; in g4x_crtc_compute_clock()
1277 drm_dbg_kms(&dev_priv->drm, in g4x_crtc_compute_clock()
1279 refclk); in g4x_crtc_compute_clock()
1296 if (!crtc_state->clock_set && in g4x_crtc_compute_clock()
1297 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in g4x_crtc_compute_clock()
1298 refclk, NULL, &crtc_state->dpll)) in g4x_crtc_compute_clock()
1299 return -EINVAL; in g4x_crtc_compute_clock()
1301 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in g4x_crtc_compute_clock()
1302 &crtc_state->dpll); in g4x_crtc_compute_clock()
1304 crtc_state->port_clock = crtc_state->dpll.dot; in g4x_crtc_compute_clock()
1307 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in g4x_crtc_compute_clock()
1315 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in pnv_crtc_compute_clock()
1319 int refclk = 96000; in pnv_crtc_compute_clock() local
1323 refclk = dev_priv->display.vbt.lvds_ssc_freq; in pnv_crtc_compute_clock()
1324 drm_dbg_kms(&dev_priv->drm, in pnv_crtc_compute_clock()
1326 refclk); in pnv_crtc_compute_clock()
1334 if (!crtc_state->clock_set && in pnv_crtc_compute_clock()
1335 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in pnv_crtc_compute_clock()
1336 refclk, NULL, &crtc_state->dpll)) in pnv_crtc_compute_clock()
1337 return -EINVAL; in pnv_crtc_compute_clock()
1339 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in pnv_crtc_compute_clock()
1340 &crtc_state->dpll); in pnv_crtc_compute_clock()
1342 crtc_state->port_clock = crtc_state->dpll.dot; in pnv_crtc_compute_clock()
1343 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in pnv_crtc_compute_clock()
1351 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in i9xx_crtc_compute_clock()
1355 int refclk = 96000; in i9xx_crtc_compute_clock() local
1359 refclk = dev_priv->display.vbt.lvds_ssc_freq; in i9xx_crtc_compute_clock()
1360 drm_dbg_kms(&dev_priv->drm, in i9xx_crtc_compute_clock()
1362 refclk); in i9xx_crtc_compute_clock()
1370 if (!crtc_state->clock_set && in i9xx_crtc_compute_clock()
1371 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in i9xx_crtc_compute_clock()
1372 refclk, NULL, &crtc_state->dpll)) in i9xx_crtc_compute_clock()
1373 return -EINVAL; in i9xx_crtc_compute_clock()
1375 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in i9xx_crtc_compute_clock()
1376 &crtc_state->dpll); in i9xx_crtc_compute_clock()
1378 crtc_state->port_clock = crtc_state->dpll.dot; in i9xx_crtc_compute_clock()
1381 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in i9xx_crtc_compute_clock()
1389 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in i8xx_crtc_compute_clock()
1393 int refclk = 48000; in i8xx_crtc_compute_clock() local
1397 refclk = dev_priv->display.vbt.lvds_ssc_freq; in i8xx_crtc_compute_clock()
1398 drm_dbg_kms(&dev_priv->drm, in i8xx_crtc_compute_clock()
1400 refclk); in i8xx_crtc_compute_clock()
1410 if (!crtc_state->clock_set && in i8xx_crtc_compute_clock()
1411 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in i8xx_crtc_compute_clock()
1412 refclk, NULL, &crtc_state->dpll)) in i8xx_crtc_compute_clock()
1413 return -EINVAL; in i8xx_crtc_compute_clock()
1415 i8xx_compute_dpll(crtc_state, &crtc_state->dpll, in i8xx_crtc_compute_clock()
1416 &crtc_state->dpll); in i8xx_crtc_compute_clock()
1418 crtc_state->port_clock = crtc_state->dpll.dot; in i8xx_crtc_compute_clock()
1419 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in i8xx_crtc_compute_clock()
1465 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_dpll_crtc_compute_clock()
1470 drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state)); in intel_dpll_crtc_compute_clock()
1472 memset(&crtc_state->dpll_hw_state, 0, in intel_dpll_crtc_compute_clock()
1473 sizeof(crtc_state->dpll_hw_state)); in intel_dpll_crtc_compute_clock()
1475 if (!crtc_state->hw.enable) in intel_dpll_crtc_compute_clock()
1478 ret = i915->display.funcs.dpll->crtc_compute_clock(state, crtc); in intel_dpll_crtc_compute_clock()
1480 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n", in intel_dpll_crtc_compute_clock()
1481 crtc->base.base.id, crtc->base.name); in intel_dpll_crtc_compute_clock()
1491 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_dpll_crtc_get_shared_dpll()
1496 drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state)); in intel_dpll_crtc_get_shared_dpll()
1497 drm_WARN_ON(&i915->drm, !crtc_state->hw.enable && crtc_state->shared_dpll); in intel_dpll_crtc_get_shared_dpll()
1499 if (!crtc_state->hw.enable || crtc_state->shared_dpll) in intel_dpll_crtc_get_shared_dpll()
1502 if (!i915->display.funcs.dpll->crtc_get_shared_dpll) in intel_dpll_crtc_get_shared_dpll()
1505 ret = i915->display.funcs.dpll->crtc_get_shared_dpll(state, crtc); in intel_dpll_crtc_get_shared_dpll()
1507 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n", in intel_dpll_crtc_get_shared_dpll()
1508 crtc->base.base.id, crtc->base.name); in intel_dpll_crtc_get_shared_dpll()
1519 dev_priv->display.funcs.dpll = &dg2_dpll_funcs; in intel_dpll_init_clock_hook()
1521 dev_priv->display.funcs.dpll = &hsw_dpll_funcs; in intel_dpll_init_clock_hook()
1523 dev_priv->display.funcs.dpll = &ilk_dpll_funcs; in intel_dpll_init_clock_hook()
1525 dev_priv->display.funcs.dpll = &chv_dpll_funcs; in intel_dpll_init_clock_hook()
1527 dev_priv->display.funcs.dpll = &vlv_dpll_funcs; in intel_dpll_init_clock_hook()
1529 dev_priv->display.funcs.dpll = &g4x_dpll_funcs; in intel_dpll_init_clock_hook()
1531 dev_priv->display.funcs.dpll = &pnv_dpll_funcs; in intel_dpll_init_clock_hook()
1533 dev_priv->display.funcs.dpll = &i9xx_dpll_funcs; in intel_dpll_init_clock_hook()
1535 dev_priv->display.funcs.dpll = &i8xx_dpll_funcs; in intel_dpll_init_clock_hook()
1548 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_enable_pll()
1549 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_enable_pll()
1550 u32 dpll = crtc_state->dpll_hw_state.dpll; in i9xx_enable_pll()
1551 enum pipe pipe = crtc->pipe; in i9xx_enable_pll()
1554 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); in i9xx_enable_pll()
1560 intel_de_write(dev_priv, FP0(pipe), crtc_state->dpll_hw_state.fp0); in i9xx_enable_pll()
1561 intel_de_write(dev_priv, FP1(pipe), crtc_state->dpll_hw_state.fp1); in i9xx_enable_pll()
1577 crtc_state->dpll_hw_state.dpll_md); in i9xx_enable_pll()
1626 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_prepare_pll()
1627 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in vlv_prepare_pll()
1628 enum pipe pipe = crtc->pipe; in vlv_prepare_pll()
1635 bestn = crtc_state->dpll.n; in vlv_prepare_pll()
1636 bestm1 = crtc_state->dpll.m1; in vlv_prepare_pll()
1637 bestm2 = crtc_state->dpll.m2; in vlv_prepare_pll()
1638 bestp1 = crtc_state->dpll.p1; in vlv_prepare_pll()
1639 bestp2 = crtc_state->dpll.p2; in vlv_prepare_pll()
1676 if (crtc_state->port_clock == 162000 || in vlv_prepare_pll()
1716 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in _vlv_enable_pll()
1717 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in _vlv_enable_pll()
1718 enum pipe pipe = crtc->pipe; in _vlv_enable_pll()
1720 intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll); in _vlv_enable_pll()
1725 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe); in _vlv_enable_pll()
1730 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_enable_pll()
1731 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in vlv_enable_pll()
1732 enum pipe pipe = crtc->pipe; in vlv_enable_pll()
1734 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); in vlv_enable_pll()
1739 /* Enable Refclk */ in vlv_enable_pll()
1741 crtc_state->dpll_hw_state.dpll & in vlv_enable_pll()
1744 if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) { in vlv_enable_pll()
1750 crtc_state->dpll_hw_state.dpll_md); in vlv_enable_pll()
1756 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_prepare_pll()
1757 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in chv_prepare_pll()
1758 enum pipe pipe = crtc->pipe; in chv_prepare_pll()
1765 bestn = crtc_state->dpll.n; in chv_prepare_pll()
1766 bestm2_frac = crtc_state->dpll.m2 & 0x3fffff; in chv_prepare_pll()
1767 bestm1 = crtc_state->dpll.m1; in chv_prepare_pll()
1768 bestm2 = crtc_state->dpll.m2 >> 22; in chv_prepare_pll()
1769 bestp1 = crtc_state->dpll.p1; in chv_prepare_pll()
1770 bestp2 = crtc_state->dpll.p2; in chv_prepare_pll()
1771 vco = crtc_state->dpll.vco; in chv_prepare_pll()
1784 /* Feedback post-divider - m2 */ in chv_prepare_pll()
1787 /* Feedback refclk divider - n and m1 */ in chv_prepare_pll()
1852 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in _chv_enable_pll()
1853 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in _chv_enable_pll()
1854 enum pipe pipe = crtc->pipe; in _chv_enable_pll()
1873 intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll); in _chv_enable_pll()
1877 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe); in _chv_enable_pll()
1882 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_enable_pll()
1883 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in chv_enable_pll()
1884 enum pipe pipe = crtc->pipe; in chv_enable_pll()
1886 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); in chv_enable_pll()
1891 /* Enable Refclk and SSC */ in chv_enable_pll()
1893 crtc_state->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); in chv_enable_pll()
1895 if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) { in chv_enable_pll()
1909 crtc_state->dpll_hw_state.dpll_md); in chv_enable_pll()
1911 dev_priv->chv_dpll_md[pipe] = crtc_state->dpll_hw_state.dpll_md; in chv_enable_pll()
1917 drm_WARN_ON(&dev_priv->drm, in chv_enable_pll()
1922 crtc_state->dpll_hw_state.dpll_md); in chv_enable_pll()
1928 * vlv_force_pll_on - forcibly enable just the PLL
1945 return -ENOMEM; in vlv_force_pll_on()
1947 crtc_state->cpu_transcoder = (enum transcoder)pipe; in vlv_force_pll_on()
1948 crtc_state->pixel_multiplier = 1; in vlv_force_pll_on()
1949 crtc_state->dpll = *dpll; in vlv_force_pll_on()
1950 crtc_state->output_types = BIT(INTEL_OUTPUT_EDP); in vlv_force_pll_on()
2009 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_disable_pll()
2010 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_disable_pll()
2011 enum pipe pipe = crtc->pipe; in i9xx_disable_pll()
2018 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); in i9xx_disable_pll()
2026 * vlv_force_pll_off - forcibly disable just the PLL
2041 /* Only for pre-ILK configs */