| /Kernel-v11.1.0/portable/IAR/78K0R/ |
| D | port.c | 37 * interrupts don't accidentally become enabled before the scheduler is started. */
49 * ---------------------- Global Interrupt Flag set (enabled)
65 * with interrupts only being re-enabled if the count is zero.
189 /* First the Timer Array Unit has to be enabled. */ in prvSetupTimerInterrupt()
221 /* Interrupt of Timer Array Unit Channel 5 enabled */ in prvSetupTimerInterrupt()
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| /Kernel-v11.1.0/portable/ThirdParty/GCC/ARC_v1/ |
| D | arc_support.s | 54 * locked, dispatch is enabled.
80 * enabled.
95 * before dispatcher is called, task context | cpu locked | dispatch enabled
99 * i.e. kernel mode, IRQ disabled, dispatch enabled
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| /Kernel-v11.1.0/portable/WizC/PIC18/ |
| D | portmacro.h | 42 #error "QuickCall must be enabled (see ProjectOptions/Optimisations)"
144 * interrupts should be re-enabled. \
183 * value equals zero, interrupts have to be enabled upon exit from the
189 * re-enabled when the interrupted task is switched back in.
376 ; interrupts need to be enabled. This is done via a \
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| /Kernel-v11.1.0/portable/template/ |
| D | port.c | 49 /* Interrupts must have been enabled for the ISR to fire, so we have to in prvTickISR()
50 * save the context with interrupts enabled. */ in prvTickISR()
|
| /Kernel-v11.1.0/portable/GCC/MicroBlaze/ |
| D | portasm.s | 126 /* Are interrupts enabled in the MSR? If so return using an return from
127 interrupt instruction to ensure interrupts are enabled only once the task
161 /* Entered via an interrupt so interrupts must be enabled in msr. */
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| /Kernel-v11.1.0/portable/GCC/ARM_CRx_No_GIC/ |
| D | port.c | 63 …SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
132 * system mode, with interrupts enabled. A few NULLs are added first to ensure in pxPortInitialiseStack()
185 * enabled. */ in pxPortInitialiseStack()
284 * priorities must be re-enabled. */ in vPortExitCritical()
|
| /Kernel-v11.1.0/portable/IAR/ARM_CRx_No_GIC/ |
| D | port.c | 63 …SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
129 * system mode, with interrupts enabled. A few NULLs are added first to ensure in pxPortInitialiseStack()
182 * enabled. */ in pxPortInitialiseStack()
281 * priorities must be re-enabled. */ in vPortExitCritical()
|
| /Kernel-v11.1.0/portable/IAR/STR75x/ |
| D | port.c | 43 …IAL_SPSR ( ( StackType_t ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */
59 * cannot be initialised to 0 as this will cause interrupts to be enabled
129 /* The status register is set for system mode, with interrupts enabled. */ in pxPortInitialiseStack()
227 * re-enabled. */ in vPortExitCritical()
|
| /Kernel-v11.1.0/portable/ThirdParty/GCC/Xtensa_ESP32/ |
| D | xtensa_context.S | 220 /* SPILL_ALL_WINDOWS macro requires window overflow exceptions to be enabled,
394 co-processors. They must remain enabled here, else a co-processor exception
523 /* At entry, CPENABLE should be showing which CPs are enabled. */
525 rsr a2, CPENABLE /* a2 = which CPs are enabled */
536 bbci.l a2, 0, 2f /* CP 0 not enabled */
544 bbci.l a2, 1, 2f /* CP 1 not enabled */
644 bbci.l a2, 0, 2f /* CP 0 not enabled */
652 bbci.l a2, 1, 2f /* CP 1 not enabled */
|
| /Kernel-v11.1.0/portable/ThirdParty/GCC/Xtensa_ESP32/include/ |
| D | xt_asm_utils.h | 24 * EXCM and WOE bit be enabled in PS, and relies on repeated hardware
41 * - If the WOE bit is not enabled (for example, in code written for
|
| /Kernel-v11.1.0/portable/IAR/STR71x/ |
| D | port.c | 46 …ITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
61 * cannot be initialised to 0 as this will cause interrupts to be enabled
134 /* The status register is set for system mode, with interrupts enabled. */ in pxPortInitialiseStack()
248 * re-enabled. */ in vPortExitCritical()
|
| /Kernel-v11.1.0/portable/IAR/AtmelSAM7S64/ |
| D | port.c | 42 …ITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
63 * cannot be initialised to 0 as this will cause interrupts to be enabled
130 /* The status register is set for system mode, with interrupts enabled. */ in pxPortInitialiseStack()
245 * re-enabled. */ in vPortExitCritical()
|
| /Kernel-v11.1.0/portable/IAR/AtmelSAM9XE/ |
| D | port.c | 54 …ITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
78 * cannot be initialised to 0 as this will cause interrupts to be enabled
145 /* The status register is set for system mode, with interrupts enabled. */ in pxPortInitialiseStack()
246 * re-enabled. */ in vPortExitCritical()
|
| /Kernel-v11.1.0/portable/ThirdParty/XCC/Xtensa/ |
| D | xtensa_context.S | 330 co-processors. They must remain enabled here, else a co-processor exception
445 /* At entry, CPENABLE should be showing which CPs are enabled. */
447 rsr a2, CPENABLE /* a2 = which CPs are enabled */
458 bbci.l a2, 0, 2f /* CP 0 not enabled */
466 bbci.l a2, 1, 2f /* CP 1 not enabled */
564 bbci.l a2, 0, 2f /* CP 0 not enabled */
572 bbci.l a2, 1, 2f /* CP 1 not enabled */
|
| /Kernel-v11.1.0/portable/IAR/STR91x/ |
| D | port.c | 51 …INITIAL_SPSR ( ( StackType_t ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */
53 …rtINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
94 * cannot be initialised to 0 as this will cause interrupts to be enabled
174 /* The status register is set for system mode, with interrupts enabled. */ in pxPortInitialiseStack()
424 * re-enabled. */ in vPortExitCritical()
|
| /Kernel-v11.1.0/portable/ThirdParty/GCC/ARC_EM_HS/ |
| D | arc_support.s | 54 * locked, dispatch is enabled.
80 * enabled.
95 * before dispatcher is called, task context | cpu locked | dispatch enabled
99 * i.e. kernel mode, IRQ disabled, dispatch enabled
|
| /Kernel-v11.1.0/portable/IAR/LPC2000/ |
| D | port.c | 56 …ITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
87 * cannot be initialised to 0 as this will cause interrupts to be enabled
150 /* The status register is set for system mode, with interrupts enabled. */ in pxPortInitialiseStack()
307 * re-enabled. */ in vPortExitCritical()
|
| /Kernel-v11.1.0/portable/IAR/ARM_CA5_No_GIC/ |
| D | port.c | 63 …TIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
121 * system mode, with interrupts enabled. A few NULLs are added first to ensure in pxPortInitialiseStack()
174 * enabled. */ in pxPortInitialiseStack()
267 * priorities must be re-enabled. */ in vPortExitCritical()
|
| /Kernel-v11.1.0/portable/GCC/NiosII/ |
| D | port.c | 47 /* Interrupts are enabled. */
182 * when it is registered. Interrupts should only be enabled after the FreeRTOS.org
211 …nable_all(status); This line is removed to prevent the interrupt from being immediately enabled. */ in _alt_ic_isr_register()
|
| /Kernel-v11.1.0/portable/GCC/ARM_CR5/ |
| D | port.c | 78 * __ARM_FP is defined by the c preprocessor when FPU support is enabled,
126 …SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
285 * system mode, with interrupts enabled. A few NULLs are added first to ensure in pxPortInitialiseStack()
339 * enabled. in pxPortInitialiseStack()
557 * priorities must be re-enabled. in vPortExitCritical()
|
| /Kernel-v11.1.0/portable/Paradigm/Tern_EE/large_untested/ |
| D | port.c | 72 /* The timer initialisation functions leave interrupts enabled,
164 /* The timer initialisation functions leave interrupts enabled, in prvDummyISR()
218 function leaves interrupts enabled. */ in prvSetupTimerInterrupt()
|
| /Kernel-v11.1.0/portable/GCC/RL78/ |
| D | port.c | 34 * interrupts don't accidentally become enabled before the scheduler is started. */
46 * ---------------------- Global Interrupt Flag set (enabled)
53 * re-enabled if the count is zero.
|
| /Kernel-v11.1.0/portable/MPLAB/PIC18F/ |
| D | port.c | 130 * enabled when the interrupted task is switched back in.
390 /* INTCON is saved with interrupts enabled. */ in pxPortInitialiseStack()
505 /* This can get called with interrupts either enabled or disabled. We in vPortYield()
562 /* Interrupts must have been enabled for the ISR to fire, so we have to
563 save the context with interrupts enabled. */
|
| /Kernel-v11.1.0/portable/IAR/RL78/ |
| D | port.c | 34 * interrupts don't accidentally become enabled before the scheduler is started. */
46 * ---------------------- Global Interrupt Flag set (enabled)
58 * re-enabled if the count is zero.
|
| /Kernel-v11.1.0/portable/GCC/ARM_CA9/ |
| D | port.c | 99 …SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
229 * system mode, with interrupts enabled. A few NULLs are added first to ensure in pxPortInitialiseStack()
282 * enabled. */ in pxPortInitialiseStack()
448 * priorities must be re-enabled. */ in vPortExitCritical()
|
