1 /*
2 * FreeRTOS Kernel V11.1.0
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /* Standard includes. */
30 #include <stdlib.h>
31
32 /* Scheduler includes. */
33 #include "FreeRTOS.h"
34 #include "task.h"
35
36 /* The critical nesting value is initialised to a non zero value to ensure
37 * interrupts don't accidentally become enabled before the scheduler is started. */
38 #define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 )
39
40 /* Initial PSW value allocated to a newly created task.
41 * 1100011000000000
42 * ||||||||-------------- Fill byte
43 * |||||||--------------- Carry Flag cleared
44 * |||||----------------- In-service priority Flags set to low level
45 * ||||------------------ Register bank Select 0 Flag cleared
46 * |||------------------- Auxiliary Carry Flag cleared
47 * ||-------------------- Register bank Select 1 Flag cleared
48 * |--------------------- Zero Flag set
49 * ---------------------- Global Interrupt Flag set (enabled)
50 */
51 #define portPSW ( 0xc6UL )
52
53 /* We require the address of the pxCurrentTCB variable, but don't want to know
54 * any details of its type. */
55 typedef void TCB_t;
56 extern volatile TCB_t * volatile pxCurrentTCB;
57
58 /* Most ports implement critical sections by placing the interrupt flags on
59 * the stack before disabling interrupts. Exiting the critical section is then
60 * simply a case of popping the flags from the stack. As 78K0 IAR does not use
61 * a frame pointer this cannot be done as modifying the stack will clobber all
62 * the stack variables. Instead each task maintains a count of the critical
63 * section nesting depth. Each time a critical section is entered the count is
64 * incremented. Each time a critical section is left the count is decremented -
65 * with interrupts only being re-enabled if the count is zero.
66 *
67 * usCriticalNesting will get set to zero when the scheduler starts, but must
68 * not be initialised to zero as this will cause problems during the startup
69 * sequence. */
70 volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
71 /*-----------------------------------------------------------*/
72
73 /*
74 * Sets up the periodic ISR used for the RTOS tick.
75 */
76 static void prvSetupTimerInterrupt( void );
77 /*-----------------------------------------------------------*/
78
79 /*
80 * Initialise the stack of a task to look exactly as if a call to
81 * portSAVE_CONTEXT had been called.
82 *
83 * See the header file portable.h.
84 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters)85 StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
86 TaskFunction_t pxCode,
87 void * pvParameters )
88 {
89 uint32_t * pulLocal;
90
91 #if configMEMORY_MODE == 1
92 {
93 /* Parameters are passed in on the stack, and written using a 32bit value
94 * hence a space is left for the second two bytes. */
95 pxTopOfStack--;
96
97 /* Write in the parameter value. */
98 pulLocal = ( uint32_t * ) pxTopOfStack;
99 *pulLocal = ( uint32_t ) pvParameters;
100 pxTopOfStack--;
101
102 /* These values are just spacers. The return address of the function
103 * would normally be written here. */
104 *pxTopOfStack = ( StackType_t ) 0xcdcd;
105 pxTopOfStack--;
106 *pxTopOfStack = ( StackType_t ) 0xcdcd;
107 pxTopOfStack--;
108
109 /* The start address / PSW value is also written in as a 32bit value,
110 * so leave a space for the second two bytes. */
111 pxTopOfStack--;
112
113 /* Task function start address combined with the PSW. */
114 pulLocal = ( uint32_t * ) pxTopOfStack;
115 *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
116 pxTopOfStack--;
117
118 /* An initial value for the AX register. */
119 *pxTopOfStack = ( StackType_t ) 0x1111;
120 pxTopOfStack--;
121 }
122 #else /* if configMEMORY_MODE == 1 */
123 {
124 /* Task function address is written to the stack first. As it is
125 * written as a 32bit value a space is left on the stack for the second
126 * two bytes. */
127 pxTopOfStack--;
128
129 /* Task function start address combined with the PSW. */
130 pulLocal = ( uint32_t * ) pxTopOfStack;
131 *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
132 pxTopOfStack--;
133
134 /* The parameter is passed in AX. */
135 *pxTopOfStack = ( StackType_t ) pvParameters;
136 pxTopOfStack--;
137 }
138 #endif /* if configMEMORY_MODE == 1 */
139
140 /* An initial value for the HL register. */
141 *pxTopOfStack = ( StackType_t ) 0x2222;
142 pxTopOfStack--;
143
144 /* CS and ES registers. */
145 *pxTopOfStack = ( StackType_t ) 0x0F00;
146 pxTopOfStack--;
147
148 /* Finally the remaining general purpose registers DE and BC */
149 *pxTopOfStack = ( StackType_t ) 0xDEDE;
150 pxTopOfStack--;
151 *pxTopOfStack = ( StackType_t ) 0xBCBC;
152 pxTopOfStack--;
153
154 /* Finally the critical section nesting count is set to zero when the task
155 * first starts. */
156 *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
157
158 /* Return a pointer to the top of the stack we have generated so this can
159 * be stored in the task control block for the task. */
160 return pxTopOfStack;
161 }
162 /*-----------------------------------------------------------*/
163
xPortStartScheduler(void)164 BaseType_t xPortStartScheduler( void )
165 {
166 /* Setup the hardware to generate the tick. Interrupts are disabled when
167 * this function is called. */
168 prvSetupTimerInterrupt();
169
170 /* Restore the context of the first task that is going to run. */
171 vPortStart();
172
173 /* Should not get here as the tasks are now running! */
174 return pdTRUE;
175 }
176 /*-----------------------------------------------------------*/
177
vPortEndScheduler(void)178 void vPortEndScheduler( void )
179 {
180 /* It is unlikely that the 78K0R port will get stopped. If required simply
181 * disable the tick interrupt here. */
182 }
183 /*-----------------------------------------------------------*/
184
prvSetupTimerInterrupt(void)185 static void prvSetupTimerInterrupt( void )
186 {
187 /* Setup channel 5 of the TAU to generate the tick interrupt. */
188
189 /* First the Timer Array Unit has to be enabled. */
190 TAU0EN = 1;
191
192 /* To configure the Timer Array Unit all Channels have to first be stopped. */
193 TT0 = 0xff;
194
195 /* Interrupt of Timer Array Unit Channel 5 is disabled to set the interrupt
196 * priority. */
197 TMMK05 = 1;
198
199 /* Clear Timer Array Unit Channel 5 interrupt flag. */
200 TMIF05 = 0;
201
202 /* Set Timer Array Unit Channel 5 interrupt priority */
203 TMPR005 = 0;
204 TMPR105 = 0;
205
206 /* Set Timer Array Unit Channel 5 Mode as interval timer. */
207 TMR05 = 0x0000;
208
209 /* Set the compare match value according to the tick rate we want. */
210 TDR05 = ( TickType_t ) ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
211
212 /* Set Timer Array Unit Channel 5 output mode */
213 TOM0 &= ~0x0020;
214
215 /* Set Timer Array Unit Channel 5 output level */
216 TOL0 &= ~0x0020;
217
218 /* Set Timer Array Unit Channel 5 output enable */
219 TOE0 &= ~0x0020;
220
221 /* Interrupt of Timer Array Unit Channel 5 enabled */
222 TMMK05 = 0;
223
224 /* Start Timer Array Unit Channel 5.*/
225 TS0 |= 0x0020;
226 }
227 /*-----------------------------------------------------------*/
228
