| /Kernel-v11.0.1/portable/Renesas/SH2A_FPU/ |
| D | portasm.src | 5 ; * SPDX-License-Identifier: MIT
49 ;-----------------------------------------------------------
61 ;-----------------------------------------------------------
77 ;-----------------------------------------------------------
89 ;-----------------------------------------------------------
97 ;-----------------------------------------------------------
101 fmov.s fr0, @-r4
102 fmov.s fr1, @-r4
103 fmov.s fr2, @-r4
104 fmov.s fr3, @-r4
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| /Kernel-v11.0.1/portable/ThirdParty/XCC/Xtensa/ |
| D | Makefile | 10 CC = xt-xcc
11 AS = xt-xcc
12 AR = xt-ar
13 XT_CORE = $(patsubst %-params,%,$(notdir $(shell xt-xcc --show-config=core)))
14 CONFIGDIR = $(shell xt-xcc --show-config=config)
16 # For platform-specific commands
22 SRCROOT = $(subst /,$(S),$(CURDIR))
23 TSTROOT = $(abspath $(SRCROOT)$(S)..$(S)..$(S)..$(S)..$(S)..$(S)demos$(S)cadence$(S)sim$(SMALL))
24 BLDROOT = $(TSTROOT)$(S)build
25 BLDDIR = $(BLDROOT)$(S)$(XT_CORE)
[all …]
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| D | xtensa_vectors.S | 3 * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
6 * SPDX-License-Identifier: MIT
37 after user's specific interrupt handlers. These macros are defined in
40 Users can install application-specific interrupt handlers for low and
47 dispatched to the RTOS-specific handler. This timer cannot be hooked
51 run-time, made available by compiling this source file with
52 '-DXT_INTEXC_HOOKS' (useful for automated testing).
58 Users can also install application-specific exception handlers in the
83 1. This file should be assembled with the -mlongcalls option to xt-xcc.
84 2. The -mlongcalls compiler option causes 'call0 dest' to be expanded to
[all …]
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| D | portasm.S | 3 * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
6 * SPDX-License-Identifier: MIT
83 * Implements the Xtensa RTOS porting layer's XT_RTOS_INT_ENTER function for
96 /* Save a12-13 in the stack frame as required by _xt_context_save. */
103 /* Save the rest of the interrupted context (preserves A12-13). */
107 Save interrupted task's SP in TCB only if not nesting.
123 s32i a1, a2, TOPOFSTACK_OFFS /* pxCurrentTCB->pxTopOfStack = SP */
136 * Implements the Xtensa RTOS porting layer's XT_RTOS_INT_EXIT function for
138 * switching, restore the (possibly) new task's context, and return to the
139 * exit dispatcher saved in the task's stack frame at XT_STK_EXIT.
[all …]
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| D | xtensa_context.h | 3 * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
6 * SPDX-License-Identifier: MIT
55 /* Align a value up to nearest n-byte boundary, where n is a power of 2. */
56 #define ALIGNUP( n, val ) ( ( ( val ) + ( n ) - 1 ) & -( n ) )
60 * -------------------------------------------------------------------------------
62 * -------------------------------------------------------------------------------
84 * -------------------------------------------------------------------------------
93 * by user TIE or the use of the MAC16 option in the user's Xtensa config.
94 * The frame size is minimized by omitting regs not applicable to user's config.
96 * For Windowed ABI, this stack frame includes the interruptee's base save area,
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| D | readme_xtensa.txt | 8 ------------
18 --------------------------------------------------
26 NOTE: It may be possible to build and run this with the open-source
27 xtensa-linux tools provided you have the correct overlay for your Xtensa
33 thread-safety on a per task basis (for use in tasks only, not interrupt
48 - Timer interrupt option with at least one interruptible timer.
49 - Interrupt option (implied by the timer interrupt option).
50 - Exception Architecture 2 (XEA2). Please note that XEA1 is NOT supported.
60 interrupt-driven drivers - it is not specific to any RTOS. Note that
63 and drivers for any on-board devices you want to use.
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| /Kernel-v11.0.1/portable/ThirdParty/GCC/Xtensa_ESP32/ |
| D | xtensa_vectors.S | 2 * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc.
4 * SPDX-License-Identifier: MIT
6 * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
9 * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
32 --------------------------------------------------------------------------------
40 after user's specific interrupt handlers. These macros are defined in
43 Users can install application-specific interrupt handlers for low and
50 dispatched to the RTOS-specific handler. This timer cannot be hooked
54 run-time, made available by compiling this source file with
55 '-DXT_INTEXC_HOOKS' (useful for automated testing).
[all …]
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| D | portmux_impl.inc.h | 2 * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
4 * SPDX-License-Identifier: Apache-2.0
54 uint32_t owner = mux->owner;
62 … "ERROR: vPortCPUAcquireMutex: mux %p is uninitialized (0x%X)! Called from %s line %d.\n", mux, ow…
63 mux->owner = portMUX_FREE_VAL;
82 /* mux->owner should be one of portMUX_FREE_VAL, CORE_ID_PRO,
85 * - If portMUX_FREE_VAL, we want to atomically set to 'coreID'.
86 * - If "our" coreID, we can drop through immediately.
87 * - If "otherCoreID", we spin here.
90 PORTMUX_COMPARE_SET_FN_NAME( &mux->owner, portMUX_FREE_VAL, &res );
[all …]
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| D | portasm.S | 2 * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc.
4 * SPDX-License-Identifier: MIT
6 * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
9 * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
97 * Implements the Xtensa RTOS porting layer's XT_RTOS_INT_ENTER function for
110 /* Save a12-13 in the stack frame as required by _xt_context_save. */
117 /* Save the rest of the interrupted context (preserves A12-13). */
121 Save interrupted task's SP in TCB only if not nesting.
141 s32i a1, a2, TOPOFSTACK_OFFS /* pxCurrentTCB->pxTopOfStack = SP */
151 addi sp, sp,-4 /* ISR will manage FPU coprocessor by forcing */
[all …]
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| /Kernel-v11.0.1/portable/ |
| D | CMakeLists.txt | 2 include( GCC/RISC-V/chip_extensions.cmake )
6 include( IAR/RISC-V/chip_extensions.cmake )
9 # FreeRTOS internal cmake file. Do not use it in user top-level project
16 # FreeRTOS internal cmake file. Do not use it in user top-level project
23 # 16-Bit DOS ports for BCC
32 # ARMv7-M port for Texas Instruments Code Composer Studio
37 # ARMv7E-M port for Texas Instruments Code Composer Studio
42 # ARMv7-R port for Texas Instruments Code Composer Studio
44 CCS/ARM_Cortex-R4/port.c
45 CCS/ARM_Cortex-R4/portASM.asm>
[all …]
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| /Kernel-v11.0.1/portable/IAR/RISC-V/chip_specific_extensions/ |
| D | readme.txt | 2 * The FreeRTOS kernel's RISC-V port is split between the the code that is
3 * common across all currently supported RISC-V chips (implementations of the
4 * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
6 * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
7 * is common to all currently supported RISC-V chips. There is only one
8 * portASM.S file because the same file is built for all RISC-V target chips.
11 * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
13 * as there are multiple RISC-V chip implementations.
17 * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
18 * compiler's!) include path. For example, if the chip in use includes a core
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| /Kernel-v11.0.1/portable/IAR/RISC-V/ |
| D | readme.txt | 2 * The FreeRTOS kernel's RISC-V port is split between the the code that is
3 * common across all currently supported RISC-V chips (implementations of the
4 * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
6 * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
7 * is common to all currently supported RISC-V chips. There is only one
8 * portASM.S file because the same file is built for all RISC-V target chips.
11 * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
13 * as there are multiple RISC-V chip implementations.
17 * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
18 * compiler's!) include path. For example, if the chip in use includes a core
[all …]
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| /Kernel-v11.0.1/portable/GCC/RISC-V/ |
| D | readme.txt | 2 * The FreeRTOS kernel's RISC-V port is split between the the code that is
3 * common across all currently supported RISC-V chips (implementations of the
4 * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
6 * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
7 * is common to all currently supported RISC-V chips. There is only one
8 * portASM.S file because the same file is built for all RISC-V target chips.
11 * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
13 * as there are multiple RISC-V chip implementations.
17 * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
18 * compiler's!) include path. For example, if the chip in use includes a core
[all …]
|
| /Kernel-v11.0.1/portable/GCC/RISC-V/chip_specific_extensions/ |
| D | readme.txt | 2 * The FreeRTOS kernel's RISC-V port is split between the the code that is
3 * common across all currently supported RISC-V chips (implementations of the
4 * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
6 * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
7 * is common to all currently supported RISC-V chips. There is only one
8 * portASM.S file because the same file is built for all RISC-V target chips.
11 * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
13 * as there are multiple RISC-V chip implementations.
17 * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
18 * compiler's!) include path. For example, if the chip in use includes a core
[all …]
|
| /Kernel-v11.0.1/portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/ |
| D | freertos_risc_v_chip_specific_extensions.h | 5 * SPDX-License-Identifier: MIT
30 * The FreeRTOS kernel's RISC-V port is split between the the code that is
31 * common across all currently supported RISC-V chips (implementations of the
32 * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
34 * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that
35 * is common to all currently supported RISC-V chips. There is only one
36 * portASM.S file because the same file is built for all RISC-V target chips.
39 * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
41 * as there are multiple RISC-V chip implementations.
45 * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
[all …]
|
| /Kernel-v11.0.1/portable/GCC/RISC-V/chip_specific_extensions/RISCV_no_extensions/ |
| D | freertos_risc_v_chip_specific_extensions.h | 5 * SPDX-License-Identifier: MIT
30 * The FreeRTOS kernel's RISC-V port is split between the the code that is
31 * common across all currently supported RISC-V chips (implementations of the
32 * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
34 * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that
35 * is common to all currently supported RISC-V chips. There is only one
36 * portASM.S file because the same file is built for all RISC-V target chips.
39 * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
41 * as there are multiple RISC-V chip implementations.
45 * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
[all …]
|
| /Kernel-v11.0.1/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/ |
| D | freertos_risc_v_chip_specific_extensions.h | 5 * SPDX-License-Identifier: MIT
30 * The FreeRTOS kernel's RISC-V port is split between the the code that is
31 * common across all currently supported RISC-V chips (implementations of the
32 * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
34 * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
35 * is common to all currently supported RISC-V chips. There is only one
36 * portASM.S file because the same file is built for all RISC-V target chips.
39 * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
41 * as there are multiple RISC-V chip implementations.
45 * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
[all …]
|
| /Kernel-v11.0.1/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/ |
| D | freertos_risc_v_chip_specific_extensions.h | 5 * SPDX-License-Identifier: MIT
30 * The FreeRTOS kernel's RISC-V port is split between the the code that is
31 * common across all currently supported RISC-V chips (implementations of the
32 * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
34 * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
35 * is common to all currently supported RISC-V chips. There is only one
36 * portASM.S file because the same file is built for all RISC-V target chips.
39 * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
41 * as there are multiple RISC-V chip implementations.
45 * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
[all …]
|
| /Kernel-v11.0.1/portable/ARMv8M/ |
| D | copy_files.py | 5 # * SPDX-License-Identifier: MIT
64 # Files to be compiled in the Non-Secure Project
99 'ARM_CM35P' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'portasm.s'),
100 … os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'mpu_wrappers_v2_asm.S'),
102 … 'ARM_CM35P_NTZ' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'portasm.s'),
103 … os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'mpu_wrappers_v2_asm.S'),
105 'ARM_CM55' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'portasm.s'),
106 … os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'mpu_wrappers_v2_asm.S'),
108 … 'ARM_CM55_NTZ' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'portasm.s'),
109 … os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'mpu_wrappers_v2_asm.S'),
[all …]
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| /Kernel-v11.0.1/portable/ThirdParty/xClang/XCOREAI/ |
| D | portasm.S | 24 {set sp, r4 /* Restore the task's SP to save the rest of its context. */
34 /* start saving the thread's context */
58 /* Save the thread's context onto the thread's stack. */
64 /* r0-r3, and r11 need to be saved because the callback may clobber them. */
89 {set sp, r4 /* Restore the task's SP now. */
100 /* Save the rest of the current task's context. */
127 ldw r1, r5[r0] /* Get this core's current TCB pointer into r1. */
128 stw r4, r1[0x0] /* Save the current task's SP to the first */
135 bla r11 /* Finally call vTaskSwitchContext(core_id) now that the task's */
144 ldw r0, r5[r6] /* get this core's current TCB pointer into r0 */
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| /Kernel-v11.0.1/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/ |
| D | freertos_risc_v_chip_specific_extensions.h | 5 * SPDX-License-Identifier: MIT
30 * The FreeRTOS kernel's RISC-V port is split between the the code that is
31 * common across all currently supported RISC-V chips (implementations of the
32 * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
34 * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
35 * is common to all currently supported RISC-V chips. There is only one
36 * portASM.S file because the same file is built for all RISC-V target chips.
39 * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
41 * as there are multiple RISC-V chip implementations.
45 * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
[all …]
|
| /Kernel-v11.0.1/include/ |
| D | task.h | 5 * SPDX-License-Identifier: MIT
39 /* *INDENT-OFF* */
43 /* *INDENT-ON* */
45 /*-----------------------------------------------------------
47 *----------------------------------------------------------*/
116 eSetBits, /* Set bits in the task's notification value. */
117 eIncrement, /* Increment the task's notification value. */
118 …eSetValueWithOverwrite, /* Set the task's notification value to a specific value even if the pre…
119 …eSetValueWithoutOverwrite /* Set the task's notification value if the previous value has been read…
163 …const char * pcTaskName; /* A pointer to the task's name. This value will be…
[all …]
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| D | stream_buffer.h | 5 * SPDX-License-Identifier: MIT
59 /* *INDENT-OFF* */
63 /* *INDENT-ON* */
75 * Type used as a stream buffer's optional callback.
102 * unblocked when a single byte is written to the buffer or the task's block
105 * unblocked until the stream buffer contains at least 10 bytes or the task's
106 * block time expires. If a reading task's block time expires before the
124 * the stream buffer data structures and storage area. A non-NULL value being
125 * returned indicates that the stream buffer has been created successfully -
187 * unblocked when a single byte is written to the buffer or the task's block
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|
| /Kernel-v11.0.1/portable/WizC/PIC18/ |
| D | portmacro.h | 5 * SPDX-License-Identifier: MIT
38 #error "WizC supports FreeRTOS on the Microchip PIC18-series only"
73 /*-----------------------------------------------------------*/
107 /*-----------------------------------------------------------*/
139 ucCriticalNesting--; \
144 * interrupts should be re-enabled. \
152 /*-----------------------------------------------------------*/
157 * compiletime determined, other input is port-defined (see port.c)
170 #define portSTACK_GROWTH ( -1 )
172 /*-----------------------------------------------------------*/
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| /Kernel-v11.0.1/portable/IAR/ARM_CM4F_MPU/ |
| D | portmacro.h | 5 * SPDX-License-Identifier: MIT
33 /* *INDENT-OFF* */
37 /* *INDENT-ON* */
39 /*-----------------------------------------------------------
46 *-----------------------------------------------------------
72 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
79 /* Errata 837070 workaround must be enabled on Cortex-M7 r0p0
84 /*-----------------------------------------------------------*/
98 /* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size
110 * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the
[all …]
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