Lines Matching +full:- +full:s
3 * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
6 * SPDX-License-Identifier: MIT
55 /* Align a value up to nearest n-byte boundary, where n is a power of 2. */
56 #define ALIGNUP( n, val ) ( ( ( val ) + ( n ) - 1 ) & -( n ) )
60 * -------------------------------------------------------------------------------
62 * -------------------------------------------------------------------------------
84 * -------------------------------------------------------------------------------
93 * by user TIE or the use of the MAC16 option in the user's Xtensa config.
94 * The frame size is minimized by omitting regs not applicable to user's config.
96 * For Windowed ABI, this stack frame includes the interruptee's base save area,
99 * -------------------------------------------------------------------------------
172 * -------------------------------------------------------------------------------
173 * This is the frame size. Add space for 4 registers (interruptee's base save
175 * -------------------------------------------------------------------------------
181 * -------------------------------------------------------------------------------
186 * It goes on the current thread's stack.
189 * by the callee according to the compiler's ABI conventions, some space to save
190 * the return address for returning to the caller, and the caller's PS register.
192 * For Windowed ABI, this stack frame includes the caller's base save area.
200 * -------------------------------------------------------------------------------
209 STRUCT_FIELD( long, 4, XT_SOL_A12, a12 ) /* should be on 16-byte alignment */
218 STRUCT_FIELD( long, 4, XT_SOL_A0, a0 ) /* should be on 16-byte alignment */
230 * -------------------------------------------------------------------------------
231 * CO-PROCESSOR STATE SAVE AREA FOR A THREAD
233 * The RTOS must provide an area per thread to save the state of co-processors
234 * when that thread does not have control. Co-processors are context-switched
235 * lazily (on demand) only when a new thread uses a co-processor instruction,
236 * otherwise a thread retains ownership of the co-processor even when it loses
237 * control of the processor. An Xtensa co-processor exception is triggered when
238 * any co-processor instruction is executed by a thread that is not the owner,
239 * and the context switch of that co-processor is then peformed by the handler.
240 * Ownership represents which thread's state is currently in the co-processor.
242 * Co-processors may not be used by interrupt or exception handlers. If an
243 * co-processor instruction is executed by an interrupt or exception handler,
244 * the co-processor exception handler will trigger a kernel panic and freeze.
246 * co-processor state (which can be quite large) and in particular remove that
249 * The co-processor state save area may be in any convenient per-thread location
251 * not be in the interrupt stack frame since interrupts don't use co-processors.
253 * Along with the save area for each co-processor, two bitmasks with flags per
254 * co-processor (laid out as in the CPENABLE reg) help manage context-switching
255 * co-processors as efficiently as possible:
258 * The contents of a non-running thread's CPENABLE register.
259 * It represents the co-processors owned (and whose state is still needed)
261 * When a thread solicits a context-swtich, its CPENABLE is cleared - the
262 * compiler has saved the (caller-saved) co-proc state if it needs to.
263 * When a non-running thread loses ownership of a CP, its bit is cleared.
264 * When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg.
265 * Avoids co-processor exceptions when no change of ownership is needed.
268 * A bitmask with the same layout as CPENABLE, a bit per co-processor.
269 * Indicates whether the state of each co-processor is saved in the state
270 * save area. When a thread enters the kernel, only the state of co-procs
271 * still enabled in CPENABLE is saved. When the co-processor exception
272 * handler assigns ownership of a co-processor to a thread, it restores
276 * A bitmask with the same layout as CPENABLE, a bit per co-processor.
277 * Indicates whether callee-saved state is saved in the state save area.
278 * Callee-saved state is saved by itself on a solicited context switch,
285 * the overall save area (which might only be stack-aligned or TCB-aligned).
288 * -------------------------------------------------------------------------------
307 #define XT_CP_CS_ST 4 /* (2 bytes) coprocessor callee-saved regs stored for this thread */
317 * -------------------------------------------------------------------------------
328 * Note: Because CPP macros expand to a single line, macros requiring multi-line
330 * -------------------------------------------------------------------------------
338 addi sp, sp, -\ size