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Searched refs:LDR (Results 1 – 25 of 27) sorted by relevance

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/Kernel-v11.0.1/portable/GCC/ARM_CR5/
DportASM.S66 LDR R2, ulCriticalNestingConst
67 LDR R1, [R2]
73 LDR R2, ulPortTaskHasFPUContextConst
74 LDR R3, [R2]
87 LDR R0, pxCurrentTCBConst
88 LDR R1, [R0]
98 LDR R0, pxCurrentTCBConst
99 LDR R1, [R0]
100 LDR SP, [R1]
107 LDR R0, ulPortTaskHasFPUContextConst
[all …]
/Kernel-v11.0.1/portable/GCC/ARM_CA9/
DportASM.S66 LDR R2, ulCriticalNestingConst
67 LDR R1, [R2]
72 LDR R2, ulPortTaskHasFPUContextConst
73 LDR R3, [R2]
86 LDR R0, pxCurrentTCBConst
87 LDR R1, [R0]
97 LDR R0, pxCurrentTCBConst
98 LDR R1, [R0]
99 LDR SP, [R1]
103 LDR R0, ulPortTaskHasFPUContextConst
[all …]
/Kernel-v11.0.1/portable/GCC/ARM_CRx_No_GIC/
DportASM.S61 LDR R2, ulCriticalNestingConst
62 LDR R1, [R2]
67 LDR R2, ulPortTaskHasFPUContextConst
68 LDR R3, [R2]
83 LDR R0, pxCurrentTCBConst
84 LDR R1, [R0]
94 LDR R0, pxCurrentTCBConst
95 LDR R1, [R0]
96 LDR SP, [R1]
100 LDR R0, ulPortTaskHasFPUContextConst
[all …]
/Kernel-v11.0.1/portable/IAR/ARM_CRx_No_GIC/
DportASM.s60 LDR R2, =ulCriticalNesting
61 LDR R1, [R2]
66 LDR R2, =ulPortTaskHasFPUContext
67 LDR R3, [R2]
82 LDR R0, =pxCurrentTCB
83 LDR R1, [R0]
93 LDR R0, =pxCurrentTCB
94 LDR R1, [R0]
95 LDR SP, [R1]
99 LDR R0, =ulPortTaskHasFPUContext
[all …]
/Kernel-v11.0.1/portable/IAR/ARM_CA9/
DportASM.h49 LDR R2, = ulCriticalNesting
50 LDR R1, [ R2 ]
59 LDR R2, = ulPortTaskHasFPUContext variable
60 LDR R3, [ R2 ]
87 LDR R0, = pxCurrentTCB
88 LDR R1, [ R0 ]
99 LDR R0, = pxCurrentTCB
100 LDR R1, [ R0 ]
101 LDR SP, [ R1 ]
107 LDR R0, = ulPortTaskHasFPUContext
[all …]
DportASM.s60 LDR R0, =vTaskSwitchContext
94 LDR r3, =ulPortInterruptNesting
95 LDR r1, [r3]
101 LDR r2, =portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS
102 LDR r0, [r2]
112 LDR r1, =vApplicationIRQHandler
120 LDR r4, =portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS
133 LDR r1, =ulPortYieldRequired
134 LDR r0, [r1]
167 LDR r0, =vTaskSwitchContext
/Kernel-v11.0.1/portable/GCC/Arm_AARCH64/
DportASM.S85 LDR X0, ullCriticalNestingConst
86 LDR X3, [X0]
89 LDR X0, ullPortTaskHasFPUContextConst
90 LDR X2, [X0]
116 LDR X0, pxCurrentTCBConst
117 LDR X1, [X0]
134 LDR X0, pxCurrentTCBConst
135 LDR X1, [X0]
136 LDR X0, [X1]
143 LDR X0, ullCriticalNestingConst /* X0 holds the address of ullCriticalNesting. */
[all …]
/Kernel-v11.0.1/portable/IAR/ARM_CA5_No_GIC/
DportASM.h49 LDR R2, = ulCriticalNesting
50 LDR R1, [ R2 ]
59 LDR R2, = ulPortTaskHasFPUContext variable
60 LDR R3, [ R2 ]
89 LDR R0, = pxCurrentTCB
90 LDR R1, [ R0 ]
101 LDR R0, = pxCurrentTCB
102 LDR R1, [ R0 ]
103 LDR SP, [ R1 ]
109 LDR R0, = ulPortTaskHasFPUContext
[all …]
DportASM.s59 LDR R0, =vTaskSwitchContext
98 LDR r3, =ulPortInterruptNesting
99 LDR r1, [r3]
112 LDR r0, =vApplicationIRQHandler
120 LDR r4, =configEOI_ADDRESS
133 LDR r1, =ulPortYieldRequired
134 LDR r0, [r1]
167 LDR r0, =vTaskSwitchContext
/Kernel-v11.0.1/portable/IAR/STR71x/
DISR_Support.h86 LDR R0, = ulCriticalNesting
87 LDR R0, [ R0 ]
95 LDR R1, = pxCurrentTCB
96 LDR R0, [ R1 ]
106 LDR R1, = pxCurrentTCB variable
107 LDR R0, [ R1 ]
108 LDR LR, [ R0 ]
114 LDR R0, = ulCriticalNesting
141 LDR LR, [ LR, # + 60 ]
Dportasm.s7957 LDR R0, =vTaskSwitchContext ; before selecting the next task to execute.
69 LDR R0, =vPortPreemptiveTick ; Increment the tick count - this may wake a task.
/Kernel-v11.0.1/portable/IAR/STR75x/
DISR_Support.h86 LDR R0, = ulCriticalNesting
87 LDR R0, [ R0 ]
95 LDR R1, = pxCurrentTCB
96 LDR R0, [ R1 ]
106 LDR R1, = pxCurrentTCB variable
107 LDR R0, [ R1 ]
108 LDR LR, [ R0 ]
114 LDR R0, = ulCriticalNesting
141 LDR LR, [ LR, # + 60 ]
/Kernel-v11.0.1/portable/IAR/STR91x/
DISR_Support.h86 LDR R0, = ulCriticalNesting
87 LDR R0, [ R0 ]
95 LDR R1, = pxCurrentTCB
96 LDR R0, [ R1 ]
106 LDR R1, = pxCurrentTCB variable
107 LDR R0, [ R1 ]
108 LDR LR, [ R0 ]
114 LDR R0, = ulCriticalNesting
141 LDR LR, [ LR, # + 60 ]
/Kernel-v11.0.1/portable/IAR/AtmelSAM7S64/
DISR_Support.h86 LDR R0, = ulCriticalNesting
87 LDR R0, [ R0 ]
95 LDR R1, = pxCurrentTCB
96 LDR R0, [ R1 ]
106 LDR R1, = pxCurrentTCB variable
107 LDR R0, [ R1 ]
108 LDR LR, [ R0 ]
114 LDR R0, = ulCriticalNesting
141 LDR LR, [ LR, # + 60 ]
Dportasm.s7957 LDR R0, =vTaskSwitchContext ; before selecting the next task to execute.
69 LDR R0, =xTaskIncrementTick ; Increment the tick count - this may wake a task.
75 LDR R0, =vTaskSwitchContext ; Select the next task to execute.
79 LDR R14, =AT91C_BASE_PITC ; Clear the PIT interrupt
80 LDR R0, [R14, #PITC_PIVR ]
82 LDR R14, =AT91C_BASE_AIC ; Mark the End of Interrupt on the AIC
/Kernel-v11.0.1/portable/IAR/AtmelSAM9XE/
DISR_Support.h85 LDR R0, = ulCriticalNesting
86 LDR R0, [ R0 ]
94 LDR R1, = pxCurrentTCB
95 LDR R0, [ R1 ]
105 LDR R1, = pxCurrentTCB variable
106 LDR R0, [ R1 ]
107 LDR LR, [ R0 ]
113 LDR R0, = ulCriticalNesting
140 LDR LR, [ LR, # + 60 ]
Dportasm.s7954 LDR R0, =vTaskSwitchContext ; before selecting the next task to execute.
/Kernel-v11.0.1/portable/IAR/LPC2000/
DISR_Support.h86 LDR R0, = ulCriticalNesting
87 LDR R0, [ R0 ]
95 LDR R1, = pxCurrentTCB
96 LDR R0, [ R1 ]
106 LDR R1, = pxCurrentTCB variable
107 LDR R0, [ R1 ]
108 LDR LR, [ R0 ]
114 LDR R0, = ulCriticalNesting
141 LDR LR, [ LR, # + 60 ]
Dportasm.s7958 LDR R0, =vTaskSwitchContext ; before selecting the next task to execute.
70 LDR R0, =vPortPreemptiveTick; before selecting the next task to execute.
/Kernel-v11.0.1/portable/GCC/Arm_AARCH64_SRE/
DportASM.S83 LDR X0, ullCriticalNestingConst
84 LDR X3, [X0]
87 LDR X0, ullPortTaskHasFPUContextConst
88 LDR X2, [X0]
114 LDR X0, pxCurrentTCBConst
115 LDR X1, [X0]
132 LDR X0, pxCurrentTCBConst
133 LDR X1, [X0]
134 LDR X0, [X1]
141 LDR X0, ullCriticalNestingConst /* X0 holds the address of ullCriticalNesting. */
[all …]
/Kernel-v11.0.1/portable/RVDS/ARM_CA9/
Dportmacro.inc50 LDR R2, =ulCriticalNesting
51 LDR R1, [R2]
56 LDR R2, =ulPortTaskHasFPUContext
57 LDR R3, [R2]
70 LDR R0, =pxCurrentTCB
71 LDR R1, [R0]
82 LDR R0, =pxCurrentTCB
83 LDR R1, [R0]
84 LDR SP, [R1]
88 LDR R0, =ulPortTaskHasFPUContext
[all …]
DportASM.s56 LDR R0, =vTaskSwitchContext
90 LDR r3, =ulPortInterruptNesting
91 LDR r1, [r3]
97 LDR r2, =ulICCIAR
98 LDR r0, [r2]
109 LDR r1, =vApplicationIRQHandler
117 LDR r4, =ulICCEOIR
130 LDR r1, =ulPortYieldRequired
131 LDR r0, [r1]
164 LDR r0, =vTaskSwitchContext
/Kernel-v11.0.1/portable/CCS/ARM_Cortex-R4/
DportASM.asm70 LDR R0, ulFPUContextConst
71 LDR R0, [R0]
88 LDR R0, pxCurrentTCBConst
89 LDR R0, [R0]
99 LDR R0, pxCurrentTCBConst
100 LDR R0, [R0]
101 LDR LR, [R0]
105 LDR R0, ulFPUContextConst
130 LDR LR, [LR, #+60]
/Kernel-v11.0.1/portable/RVDS/ARM7_LPC21xx/
Dportmacro.inc37 LDR R0, =pxCurrentTCB ; Set the LR to the task stack. The location was...
38 LDR R0, [R0] ; ... stored in pxCurrentTCB
39 LDR LR, [R0]
41 LDR R0, =ulCriticalNesting ; The critical nesting depth is the first item on...
51 LDR LR, [LR, #+60] ; Restore the return address
82 LDR R0, =ulCriticalNesting ;
83 LDR R0, [R0] ;
86 LDR R0, =pxCurrentTCB ; Store the new top of stack for the task.
87 LDR R1, [R0] ;
DportASM.s85 LDR R0, =vTaskSwitchContext ; Get the address of the context switch function
105 LDR R0, =xTaskIncrementTick ; Increment the tick count.
111 LDR R0, =vTaskSwitchContext ; Find the highest priority task that
116 LDR R1, =T0IR
119 LDR R0, =VICVECTADDR ; Acknowledge the interrupt

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