Searched +full:runs +full:- +full:on (Results 1 – 25 of 72) sorted by relevance
123
| /Kernel-v11.0.1/.github/workflows/ |
| D | ci.yml | 2 on:
10 runs-on: ubuntu-20.04
12 - uses: actions/checkout@v3
13 - name: Check Formatting of FreeRTOS-Kernel Files
14 uses: FreeRTOS/CI-CD-Github-Actions/formatting@main
16 exclude-dirs: portable
18 spell-check:
19 runs-on: ubuntu-latest
21 - name: Clone This Repo
23 - name: Run spellings check
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| D | kernel-demos.yml | 1 name: FreeRTOS-Kernel Demos
2 on: [push, pull_request]
5 WIN32-MSVC:
7 runs-on: windows-latest
9 - name: Checkout the FreeRTOS/FreeRTOS Repository
15 fetch-depth: 1
18 - name: Checkout Pull Request
23 - name: Add msbuild to PATH
24 uses: microsoft/setup-msbuild@v1.1
26 - name: Build WIN32-MSVC Demo
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| D | git-secrets.yml | 1 name: git-secrets Check
2 on:
7 git-secrets:
8 runs-on: ubuntu-latest
10 - uses: actions/checkout@v3
13 - name: Checkout awslabs/git-secrets
16 repository: awslabs/git-secrets
18 path: git-secrets
19 - name: Install git-secrets
20 run: cd git-secrets && sudo make install && cd ..
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| D | formatting.yml | 3 on:
8 bashPass: \033[32;1mPASSED -
9 bashInfo: \033[33;1mINFO -
10 bashFail: \033[31;1mFAILED -
19 runs-on: ubuntu-20.04
21 - name: Apply Formatting Fix
22 id: check-formatting
23 uses: FreeRTOS/CI-CD-Github-Actions/formatting-bot@main
25 exclude-dirs: portable
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| D | unit-tests.yml | 2 on: [push, pull_request]
6 runs-on: ubuntu-20.04
8 - name: Checkout Parent Repository
14 fetch-depth: 1
17 - name: Checkout Pull Request
22 - name: Setup Python
23 uses: actions/setup-python@master
25 python-version: 3.8
27 - name: Install packages
29 sudo apt-get install lcov cflow ruby doxygen build-essential unifdef
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| D | kernel-checks.yml | 1 name: Kernel-Checker
3 on: [push, pull_request]
6 kernel-checker:
8 runs-on: ubuntu-20.04
11 - name: Tool Setup
12 uses: actions/setup-python@v3
17 - name: Checkout FreeRTOS Tools
21 sparse-checkout: '.github'
26 - name: Checkout Pull Request
32 - name: Collecting changed files
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| D | coverity_scan.yml | 2 on:
3 # Run on every commit to mainline
10 bashPass: \033[32;1mPASSED -
11 bashInfo: \033[33;1mINFO -
12 bashFail: \033[31;1mFAILED -
16 Coverity-Scan:
17 if: ( github.repository == 'FreeRTOS/FreeRTOS-Kernel' )
19 runs-on: ubuntu-latest
21 - name: Checkout the Repository
24 - env:
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| D | auto-release.yml | 1 name: Kernel-Auto-Release
3 on:
15 description: "Version String for task.h on main branch (leave empty to leave as-is)."
20 release-packager:
22 runs-on: ubuntu-latest
25 - name: Tool Setup
26 uses: actions/setup-python@v2
33 - name: Checkout FreeRTOS Release Tools
40 - name: Checkout FreeRTOS Kernel
44 fetch-depth: 0
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| /Kernel-v11.0.1/portable/ThirdParty/GCC/ARM_TFM/ |
| D | README.md | 4 services in Trusted Firmware M(TF-M) through Platform Security Architecture
5 (PSA) API based on the ARM Cortex-M23, Cortex-M33, Cortex-M55 and Cortex-M85
10 …ource Page](https://developer.arm.com/architectures/security-architectures/platform-security-archi…
12 TF-M is an open source project. It provides a reference implementation of PSA
13 for Arm M-profile architecture. Please get the details from this [link](https://git.trustedfirmware…
18 …The implementation of APIs which are defined in ```\ns_interface\os_wrapper\mutex.h``` by tf-m-tes…
19 (tag: TF-Mv1.5.0 & TF-Mv1.6.0). The implementation is based on FreeRTOS mutex type semaphore.
23 To build a project based on this port:
25 * Step 2: build the nonsecure image. Please follow the **Build the Non-Secure Side** for details.
29 ### Get the TF-M source code
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| /Kernel-v11.0.1/portable/MSVC-MingW/ |
| D | port.c | 5 * SPDX-License-Identifier: MIT
53 * a tick interrupt being generated on an embedded target. In this Windows
60 * Process all the simulated interrupts - each represented by a bit in
73 * Exiting a critical section will cause the calling task to block on yield
87 /*-----------------------------------------------------------*/
89 /* The WIN32 simulator runs each task in a thread. The context switching is
119 * initialised to a non-zero value so interrupts do not become enabled during
121 * ulCriticalNesting will get set to zero when the first task runs. This
138 /*-----------------------------------------------------------*/
191 /* The interrupt is now pending - notify the simulated interrupt in prvSimulatedPeripheralTimer()
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| /Kernel-v11.0.1/portable/ThirdParty/XCC/Xtensa/ |
| D | xtensa_timer.h | 3 * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
6 * SPDX-License-Identifier: MIT
39 * tick duration to match timer interrupt to the real-time tick duration.
62 * and priority. User may specify a timer by defining XT_TIMER_INDEX with -D,
64 * not be on a high priority interrupt - an error will be reported in invalid).
119 * If using a supported board via the board-independent API defined in xtbsp.h,
121 * and cached during run-time initialization.
123 * NOTE ON SIMULATOR:
125 * because it depends on the speed of the host and the version of the simulator.
126 * Also because it runs much slower than hardware, it is not possible to achieve
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| /Kernel-v11.0.1/portable/ThirdParty/GCC/Xtensa_ESP32/include/ |
| D | xtensa_timer.h | 2 * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc.
4 * SPDX-License-Identifier: MIT
6 * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
10 * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
42 * tick duration to match timer interrupt to the real-time tick duration.
66 * and priority. User may specify a timer by defining XT_TIMER_INDEX with -D,
68 * not be on a high priority interrupt - an error will be reported in invalid).
123 * If using a supported board via the board-independent API defined in xtbsp.h,
125 * and cached during run-time initialization.
127 * NOTE ON SIMULATOR:
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| /Kernel-v11.0.1/portable/IAR/MSP430X/ |
| D | port.c | 5 * SPDX-License-Identifier: MIT
33 /*-----------------------------------------------------------
35 *----------------------------------------------------------*/
37 /* Constants required for hardware setup. The tick ISR runs off the ACLK,
50 * critical section is exited the count is decremented - with interrupts only
51 * being re-enabled if the count is zero.
57 /*-----------------------------------------------------------*/
65 /*-----------------------------------------------------------*/
81 * Place a few bytes of known values on the bottom of the stack. in pxPortInitialiseStack()
85 * pxTopOfStack--; in pxPortInitialiseStack()
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| /Kernel-v11.0.1/portable/CCS/MSP430X/ |
| D | port.c | 5 * SPDX-License-Identifier: MIT
33 /*-----------------------------------------------------------
35 *----------------------------------------------------------*/
37 /* Constants required for hardware setup. The tick ISR runs off the ACLK,
50 critical section is exited the count is decremented - with interrupts only
51 being re-enabled if the count is zero.
57 /*-----------------------------------------------------------*/
65 /*-----------------------------------------------------------*/
79 Place a few bytes of known values on the bottom of the stack. in pxPortInitialiseStack()
83 pxTopOfStack--; in pxPortInitialiseStack()
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| /Kernel-v11.0.1/portable/Rowley/MSP430F449/ |
| D | port.c | 5 * SPDX-License-Identifier: MIT
33 /*-----------------------------------------------------------
35 *----------------------------------------------------------*/
37 /* Constants required for hardware setup. The tick ISR runs off the ACLK,
50 critical section is exited the count is decremented - with interrupts only
51 being re-enabled if the count is zero.
57 /*-----------------------------------------------------------*/
65 /*-----------------------------------------------------------*/
76 Place a few bytes of known values on the bottom of the stack. in pxPortInitialiseStack()
80 pxTopOfStack--; in pxPortInitialiseStack()
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| /Kernel-v11.0.1/portable/IAR/MSP430/ |
| D | port.c | 5 * SPDX-License-Identifier: MIT
33 /*-----------------------------------------------------------
35 *----------------------------------------------------------*/
37 /* Constants required for hardware setup. The tick ISR runs off the ACLK,
50 * critical section is exited the count is decremented - with interrupts only
51 * being re-enabled if the count is zero.
57 /*-----------------------------------------------------------*/
65 /*-----------------------------------------------------------*/
78 * Place a few bytes of known values on the bottom of the stack. in pxPortInitialiseStack()
82 * pxTopOfStack--; in pxPortInitialiseStack()
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| /Kernel-v11.0.1/portable/IAR/78K0R/ |
| D | portasm.s26 | 5 ; * SPDX-License-Identifier: MIT
30 ;------------------------------------------------------------------------------
40 ;------------------------------------------------------------------------------
45 ;------------------------------------------------------------------------------
50 ;------------------------------------------------------------------------------
61 ;------------------------------------------------------------------------------
64 ; this code runs.
72 ;------------------------------------------------------------------------------
81 ;------------------------------------------------------------------------------
90 ;------------------------------------------------------------------------------
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| /Kernel-v11.0.1/portable/CCS/ARM_CM3/ |
| D | port.c | 5 * SPDX-License-Identifier: MIT
29 /*-----------------------------------------------------------
31 *----------------------------------------------------------*/
38 …LL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
75 /* The systick is a 24-bit counter. */
83 /* For strict compliance with the Cortex-M spec the task start address should
84 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
121 /*-----------------------------------------------------------*/
165 /*-----------------------------------------------------------*/
177 /* Offset added to account for the way the MCU uses the stack on entry/exit in pxPortInitialiseStack()
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| /Kernel-v11.0.1/portable/IAR/ARM_CM7/r0p1/ |
| D | port.c | 5 * SPDX-License-Identifier: MIT
29 /*-----------------------------------------------------------
31 *----------------------------------------------------------*/
45 …LL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
96 /* The systick is a 24-bit counter. */
104 /* For strict compliance with the Cortex-M spec the task start address should
105 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
138 * Turn the VFP on.
152 /*-----------------------------------------------------------*/
192 /*-----------------------------------------------------------*/
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| /Kernel-v11.0.1/portable/CCS/ARM_CM4F/ |
| D | port.c | 5 * SPDX-License-Identifier: MIT
29 /*-----------------------------------------------------------
31 *----------------------------------------------------------*/
42 …LL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
84 /* The systick is a 24-bit counter. */
92 /* For strict compliance with the Cortex-M spec the task start address should
93 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
126 * Turn the VFP on.
135 /*-----------------------------------------------------------*/
179 /*-----------------------------------------------------------*/
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| /Kernel-v11.0.1/portable/RVDS/ARM_CM3/ |
| D | port.c | 5 * SPDX-License-Identifier: MIT
29 /*-----------------------------------------------------------
31 *----------------------------------------------------------*/
38 …LL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
84 /* The systick is a 24-bit counter. */
92 /* For strict compliance with the Cortex-M spec the task start address should
93 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
132 /*-----------------------------------------------------------*/
172 /*-----------------------------------------------------------*/
183 …pxTopOfStack--; /* Offset added to account fo… in pxPortInitialiseStack()
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| /Kernel-v11.0.1/portable/IAR/ARM_CM3/ |
| D | port.c | 5 * SPDX-License-Identifier: MIT
29 /*-----------------------------------------------------------
31 *----------------------------------------------------------*/
41 …LL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
87 /* The systick is a 24-bit counter. */
95 /* For strict compliance with the Cortex-M spec the task start address should
96 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
138 /*-----------------------------------------------------------*/
178 /*-----------------------------------------------------------*/
189 …pxTopOfStack--; /* Offset added to account fo… in pxPortInitialiseStack()
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| /Kernel-v11.0.1/portable/IAR/ARM_CM4F/ |
| D | port.c | 5 * SPDX-License-Identifier: MIT
29 /*-----------------------------------------------------------
31 *----------------------------------------------------------*/
45 …LL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
66 /* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
102 /* The systick is a 24-bit counter. */
110 /* For strict compliance with the Cortex-M spec the task start address should
111 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
144 * Turn the VFP on.
158 /*-----------------------------------------------------------*/
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| /Kernel-v11.0.1/portable/GCC/MSP430F449/ |
| D | port.c | 5 * SPDX-License-Identifier: MIT
43 /*-----------------------------------------------------------
45 *----------------------------------------------------------*/
47 /* Constants required for hardware setup. The tick ISR runs off the ACLK,
58 /* Most ports implement critical sections by placing the interrupt flags on
64 * incremented. Each time a critical section is left the count is decremented -
65 * with interrupts only being re-enabled if the count is zero.
71 /*-----------------------------------------------------------*/
103 * used by the task is retrieved from the stack - followed by the value of all
129 /*-----------------------------------------------------------*/
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| /Kernel-v11.0.1/portable/RVDS/ARM_CM4F/ |
| D | port.c | 5 * SPDX-License-Identifier: MIT
29 /*-----------------------------------------------------------
31 *----------------------------------------------------------*/
42 …LL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
68 /* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
99 /* The systick is a 24-bit counter. */
107 /* For strict compliance with the Cortex-M spec the task start address should
108 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
152 /*-----------------------------------------------------------*/
192 /*-----------------------------------------------------------*/
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