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/Kernel-v11.1.0/portable/ThirdParty/xClang/XCOREAI/
Dportasm.S25 get r11, id} /* Get the logical core ID into r11. */
27 ldw r0, r0[r11] /* Translate to the RTOS core ID into r0 */
91 get r11, id} /* Get the logical core ID into r11. */
93 ldw r0, r0[r11] /* Translate to the RTOS core ID into r0. */
133 mov r6, r0} /* copy the RTOS core ID into r6 so we don't lose it. */
136 /* entire context is saved. Note the core id in r0 is the argument. */
/Kernel-v11.1.0/portable/GCC/NiosII/
Dport.c194 int id = irq; /* IRQ interpreted as the interrupt ID. */ in _alt_ic_isr_register() local
196 if( id < ALT_NIRQ ) in _alt_ic_isr_register()
206 alt_irq[ id ].handler = isr; in _alt_ic_isr_register()
207 alt_irq[ id ].context = isr_context; in _alt_ic_isr_register()
209 rc = ( isr ) ? alt_ic_irq_enable( ic_id, id ) : alt_ic_irq_disable( ic_id, id ); in _alt_ic_isr_register()
/Kernel-v11.1.0/portable/ThirdParty/GCC/Xtensa_ESP32/
Dportmux_impl.h33 /* XOR one core ID with this value to get the other core ID */
/Kernel-v11.1.0/.github/workflows/
Dauto-release.yml7 description: 'Commit ID'
51 - name: create a new branch that references commit id
Dformatting.yml22 id: check-formatting
/Kernel-v11.1.0/portable/template/
Dportmacro.h112 /* Return the core ID on which the code is running. */
121 /* Request the core ID x to yield. */
/Kernel-v11.1.0/portable/GCC/ARM_AARCH64_SRE/
DportASM.S314 /* Read interrupt ID from the interrupt acknowledge register and store it
318 /* Maintain the interrupt ID value across the function call. */
329 /* Restore the interrupt ID value. */
332 /* End IRQ processing by writing interrupt ID value to the EOI register. */
/Kernel-v11.1.0/include/
Dtimers.h196 …* ( void * ) x, // Assign each timer a unique id eq…
313 * // Obtain the address of the variable to increment from the timer ID.
371 * Returns the ID assigned to the timer.
378 * ID can be used as time specific (timer local) storage.
382 * @return The ID assigned to the timer being queried.
393 * Sets the ID assigned to the timer.
399 * ID can be used as time specific (timer local) storage.
403 * @param pvNewID The ID to assign to the timer.
763 …* 0, // The id is not used by the cal…
/Kernel-v11.1.0/portable/GCC/MicroBlazeV8/
Dportmacro.h237 * The ID of the peripheral that will have pxHandler assigned as its interrupt
277 * The ID of the peripheral that will have its interrupt enabled in the
297 * The ID of the peripheral that will have its interrupt disabled in the
/Kernel-v11.1.0/portable/GCC/MicroBlazeV9/
Dportmacro.h252 * The ID of the peripheral that will have pxHandler assigned as its interrupt
292 * The ID of the peripheral that will have its interrupt enabled in the
312 * The ID of the peripheral that will have its interrupt disabled in the
/Kernel-v11.1.0/.github/
Dpull_request_template.md20 <!-- If any, please provide issue ID. -->
/Kernel-v11.1.0/portable/GCC/ARM7_AT91SAM7S/
Dioat91sam7x256.h87 AT91_REG DBGU_CIDR; /* Chip ID Register */
88 AT91_REG DBGU_EXID; /* Chip ID Extension Register */
299 AT91_REG DBGU_CIDR; /* Chip ID Register */
300 AT91_REG DBGU_EXID; /* Chip ID Extension Register */
1076 #define AT91C_PWMC_CHID0 ( ( unsigned int ) 0x1 << 0 ) /* (PWMC) Channel ID 0 */
1077 #define AT91C_PWMC_CHID1 ( ( unsigned int ) 0x1 << 1 ) /* (PWMC) Channel ID 1 */
1078 #define AT91C_PWMC_CHID2 ( ( unsigned int ) 0x1 << 2 ) /* (PWMC) Channel ID 2 */
1079 #define AT91C_PWMC_CHID3 ( ( unsigned int ) 0x1 << 3 ) /* (PWMC) Channel ID 3 */
1345 AT91_REG CAN_MB_MID; /* MailBox ID Register */
1346 AT91_REG CAN_MB_MFID; /* MailBox Family ID Register */
[all …]
DAT91SAM7X256.h87 AT91_REG DBGU_CIDR; /* Chip ID Register */
88 AT91_REG DBGU_EXID; /* Chip ID Extension Register */
299 AT91_REG DBGU_CIDR; /* Chip ID Register */
300 AT91_REG DBGU_EXID; /* Chip ID Extension Register */
1076 #define AT91C_PWMC_CHID0 ( ( unsigned int ) 0x1 << 0 ) /* (PWMC) Channel ID 0 */
1077 #define AT91C_PWMC_CHID1 ( ( unsigned int ) 0x1 << 1 ) /* (PWMC) Channel ID 1 */
1078 #define AT91C_PWMC_CHID2 ( ( unsigned int ) 0x1 << 2 ) /* (PWMC) Channel ID 2 */
1079 #define AT91C_PWMC_CHID3 ( ( unsigned int ) 0x1 << 3 ) /* (PWMC) Channel ID 3 */
1345 AT91_REG CAN_MB_MID; /* MailBox ID Register */
1346 AT91_REG CAN_MB_MFID; /* MailBox Family ID Register */
[all …]
/Kernel-v11.1.0/portable/IAR/AtmelSAM7S64/
DAT91SAM7X256_inc.h126 #define DBGU_CIDR ( 64 ) /* Chip ID Register */
127 #define DBGU_EXID ( 68 ) /* Chip ID Extension Register */
829 #define AT91C_PWMC_CHID0 ( 0x1 << 0 ) /* (PWMC) Channel ID 0 */
830 #define AT91C_PWMC_CHID1 ( 0x1 << 1 ) /* (PWMC) Channel ID 1 */
831 #define AT91C_PWMC_CHID2 ( 0x1 << 2 ) /* (PWMC) Channel ID 2 */
832 #define AT91C_PWMC_CHID3 ( 0x1 << 3 ) /* (PWMC) Channel ID 3 */
1079 #define CAN_MB_MID ( 8 ) /* MailBox ID Register */
1080 #define CAN_MB_MFID ( 12 ) /* MailBox Family ID Register */
1099 /* -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */
1100 /* -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */
[all …]
DAT91SAM7X128_inc.h126 #define DBGU_CIDR ( 64 ) /* Chip ID Register */
127 #define DBGU_EXID ( 68 ) /* Chip ID Extension Register */
829 #define AT91C_PWMC_CHID0 ( 0x1 << 0 ) /* (PWMC) Channel ID 0 */
830 #define AT91C_PWMC_CHID1 ( 0x1 << 1 ) /* (PWMC) Channel ID 1 */
831 #define AT91C_PWMC_CHID2 ( 0x1 << 2 ) /* (PWMC) Channel ID 2 */
832 #define AT91C_PWMC_CHID3 ( 0x1 << 3 ) /* (PWMC) Channel ID 3 */
1079 #define CAN_MB_MID ( 8 ) /* MailBox ID Register */
1080 #define CAN_MB_MFID ( 12 ) /* MailBox Family ID Register */
1099 /* -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */
1100 /* -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */
[all …]
DAT91SAM7X128.h87 AT91_REG DBGU_CIDR; /* Chip ID Register */
88 AT91_REG DBGU_EXID; /* Chip ID Extension Register */
299 AT91_REG DBGU_CIDR; /* Chip ID Register */
300 AT91_REG DBGU_EXID; /* Chip ID Extension Register */
1076 #define AT91C_PWMC_CHID0 ( ( unsigned int ) 0x1 << 0 ) /* (PWMC) Channel ID 0 */
1077 #define AT91C_PWMC_CHID1 ( ( unsigned int ) 0x1 << 1 ) /* (PWMC) Channel ID 1 */
1078 #define AT91C_PWMC_CHID2 ( ( unsigned int ) 0x1 << 2 ) /* (PWMC) Channel ID 2 */
1079 #define AT91C_PWMC_CHID3 ( ( unsigned int ) 0x1 << 3 ) /* (PWMC) Channel ID 3 */
1345 AT91_REG CAN_MB_MID; /* MailBox ID Register */
1346 AT91_REG CAN_MB_MFID; /* MailBox Family ID Register */
[all …]
DAT91SAM7X256.h87 AT91_REG DBGU_CIDR; /* Chip ID Register */
88 AT91_REG DBGU_EXID; /* Chip ID Extension Register */
299 AT91_REG DBGU_CIDR; /* Chip ID Register */
300 AT91_REG DBGU_EXID; /* Chip ID Extension Register */
1076 #define AT91C_PWMC_CHID0 ( ( unsigned int ) 0x1 << 0 ) /* (PWMC) Channel ID 0 */
1077 #define AT91C_PWMC_CHID1 ( ( unsigned int ) 0x1 << 1 ) /* (PWMC) Channel ID 1 */
1078 #define AT91C_PWMC_CHID2 ( ( unsigned int ) 0x1 << 2 ) /* (PWMC) Channel ID 2 */
1079 #define AT91C_PWMC_CHID3 ( ( unsigned int ) 0x1 << 3 ) /* (PWMC) Channel ID 3 */
1345 AT91_REG CAN_MB_MID; /* MailBox ID Register */
1346 AT91_REG CAN_MB_MFID; /* MailBox Family ID Register */
[all …]
/Kernel-v11.1.0/portable/GCC/TriCore_1782/
Dport.c337 * Need to save the lower context as well and copy the PCXI CSA ID into in prvSystemTickHandler()
458 * Need to save the lower context as well and copy the PCXI CSA ID into in prvTrapYield()
505 * Need to save the lower context as well and copy the PCXI CSA ID into in prvInterruptYield()
/Kernel-v11.1.0/portable/IAR/ARM_CM85/secure/
Dsecure_context.h44 * @brief Invalid context ID.
/Kernel-v11.1.0/portable/ARMv8M/secure/context/
Dsecure_context.h44 * @brief Invalid context ID.
/Kernel-v11.1.0/portable/IAR/ARM_CM23/secure/
Dsecure_context.h44 * @brief Invalid context ID.
/Kernel-v11.1.0/portable/IAR/ARM_CM55/secure/
Dsecure_context.h44 * @brief Invalid context ID.
/Kernel-v11.1.0/portable/GCC/ARM_CM35P/secure/
Dsecure_context.h44 * @brief Invalid context ID.
/Kernel-v11.1.0/portable/GCC/ARM_CM33/secure/
Dsecure_context.h44 * @brief Invalid context ID.
/Kernel-v11.1.0/portable/IAR/ARM_CM33/secure/
Dsecure_context.h44 * @brief Invalid context ID.

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