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/Kernel-v11.1.0/portable/GCC/RX600/
Dreadme.txt35 … RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5)
40 … RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5)
58 *5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h.
/Kernel-v11.1.0/portable/GCC/RX600v2/
Dreadme.txt35 … RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5)
40 … RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5)
58 *5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h.
/Kernel-v11.1.0/portable/IAR/RX600/
Dreadme.txt35 … RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5)
40 … RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5)
58 *5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h.
/Kernel-v11.1.0/portable/IAR/RX700v3_DPFPU/
Dreadme.txt35 … RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5)
40 … RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5)
58 *5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h.
/Kernel-v11.1.0/portable/IAR/RX100/
Dreadme.txt35 … RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5)
40 … RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5)
58 *5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h.
/Kernel-v11.1.0/portable/Renesas/RX100/
Dreadme.txt35 … RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5)
40 … RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5)
58 *5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h.
/Kernel-v11.1.0/portable/GCC/RX700v3_DPFPU/
Dreadme.txt35 … RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5)
40 … RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5)
58 *5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h.
/Kernel-v11.1.0/portable/IAR/RXv2/
Dreadme.txt35 … RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5)
40 … RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5)
58 *5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h.
/Kernel-v11.1.0/portable/Renesas/RX700v3_DPFPU/
Dreadme.txt35 … RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5)
40 … RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5)
58 *5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h.
/Kernel-v11.1.0/portable/GCC/RX100/
Dreadme.txt35 … RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5)
40 … RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5)
58 *5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h.
/Kernel-v11.1.0/portable/Renesas/RX200/
Dreadme.txt35 … RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5)
40 … RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5)
58 *5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h.
/Kernel-v11.1.0/portable/Renesas/RX600/
Dreadme.txt35 … RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5)
40 … RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5)
58 *5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h.
/Kernel-v11.1.0/portable/Renesas/RX600v2/
Dreadme.txt35 … RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5)
40 … RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5)
58 *5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h.
/Kernel-v11.1.0/portable/IAR/78K0R/
Dport.c187 /* Setup channel 5 of the TAU to generate the tick interrupt. */ in prvSetupTimerInterrupt()
195 /* Interrupt of Timer Array Unit Channel 5 is disabled to set the interrupt in prvSetupTimerInterrupt()
199 /* Clear Timer Array Unit Channel 5 interrupt flag. */ in prvSetupTimerInterrupt()
202 /* Set Timer Array Unit Channel 5 interrupt priority */ in prvSetupTimerInterrupt()
206 /* Set Timer Array Unit Channel 5 Mode as interval timer. */ in prvSetupTimerInterrupt()
212 /* Set Timer Array Unit Channel 5 output mode */ in prvSetupTimerInterrupt()
215 /* Set Timer Array Unit Channel 5 output level */ in prvSetupTimerInterrupt()
218 /* Set Timer Array Unit Channel 5 output enable */ in prvSetupTimerInterrupt()
221 /* Interrupt of Timer Array Unit Channel 5 enabled */ in prvSetupTimerInterrupt()
224 /* Start Timer Array Unit Channel 5.*/ in prvSetupTimerInterrupt()
/Kernel-v11.1.0/portable/ThirdParty/GCC/Xtensa_ESP32/
Dxtensa_vector_defaults.S33 #define XT_DEBUGCAUSE_DI (5)
177 #if XCHAL_NUM_INTLEVELS >=5 && XCHAL_EXCM_LEVEL <5 && XCHAL_DEBUGLEVEL !=5
192 rfi 5
195 #endif /* Level 5 */
Dxtensa_loadstore_handler.S133 extui a2, a2, 3, 5
329 blti a2, 5, .LSA_stack_reg // a3 contains the target register
456 /* The first 5 entries (80 bytes) of this table are unused (registers
460 .set .LS_jumptable_base, .LS_jumptable - (16 * 5)
462 .org .LS_jumptable_base + (16 * 5)
/Kernel-v11.1.0/portable/GCC/TriCore_1782/
Dporttrap.c59 #define portASSERT_TRAP 5
71 #define portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS 5
80 #define portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS 5
87 #define portTIN_CM_CALL_STACK_UNDERFLOW 5
96 #define portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR 5
/Kernel-v11.1.0/include/
Dtimers.h62 #define tmrCOMMAND_DELETE ( ( BaseType_t ) 5 )
149 * #define NUM_TIMERS 5
306 * // it when the software timer was created. After the 5th increment the
321 * if( *puxVariableToIncrement == 5 )
722 * // When a key is pressed, an LCD back-light is switched on. If 5 seconds pass
732 * // The timer expired, therefore 5 seconds must have passed since a key
741 * // responsible for turning the back-light off after 5 seconds of
759 * // the back-light off if no keys are pressed within a 5 second period.
831 * // key is pressed, an LCD back-light is switched on. If 5 seconds pass
841 * // The timer expired, therefore 5 seconds must have passed since a key
[all …]
/Kernel-v11.1.0/portable/ThirdParty/XCC/Xtensa/
Dxtensa_vectors.S873 extui a4, a0, 16, 5 /* a4 = CP index = n */
882 extui a3, a0, 16, 5 /* a3 = CP index = n */
886 The config-specific HAL macro invoked below destroys a2-5, preserves a0-1.
905 extui a3, a0, 16, 5 /* a3 = CP index = n */
912 The config-specific HAL macro invoked below destroys a2-5, preserves a0-1.
1251 #if XCHAL_EXCM_LEVEL >= 5
1289 movi a0, PS_INTLEVEL(5) | PS_UM
1291 movi a0, PS_INTLEVEL(5) | PS_UM | PS_WOE
1298 dispatch_c_isr 5 XCHAL_INTLEVEL5_MASK
1319 rfi 5
[all …]
/Kernel-v11.1.0/portable/GCC/ARM7_AT91SAM7S/
Dioat91sam7x256.h198 AT91_REG Reserved26[ 5 ]; /* */
210 AT91_REG Reserved27[ 5 ]; /* */
246 #define AT91C_AIC_SRCTYPE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Interrupt…
247 #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) Internal …
248 #define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) External …
249 #define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) Internal …
250 #define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) External …
251 #define AT91C_AIC_SRCTYPE_HIGH_LEVEL ( ( unsigned int ) 0x2 << 5 ) /* (AIC) Internal …
252 #define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Internal …
319 #define AT91C_US_RXDIS ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Receiver Disable */
[all …]
/Kernel-v11.1.0/portable/IAR/AtmelSAM7S64/
DAT91SAM7S64_inc.h166 #define AT91C_AIC_SRCTYPE ( 0x3 << 5 ) /* (AIC) Interrupt Source Type */
167 #define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ( 0x0 << 5 ) /* (AIC) Internal Sources Code La…
168 #define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ( 0x1 << 5 ) /* (AIC) Internal Sources Code La…
169 #define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ( 0x2 << 5 ) /* (AIC) External Sources Code La…
170 #define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ( 0x3 << 5 ) /* (AIC) External Sources Code La…
208 #define AT91C_US_RXDIS ( 0x1 << 5 ) /* (DBGU) Receiver Disable */
229 #define AT91C_US_OVRE ( 0x1 << 5 ) /* (DBGU) Overrun Interrupt */
534 #define AT91C_MC_GPNVM5 ( 0x1 << 13 ) /* (MC) Sector 5 Lock Status */
542 #define AT91C_MC_LOCKS5 ( 0x1 << 21 ) /* (MC) Sector 5 Lock Status */
605 #define AT91C_SPI_ENDTX ( 0x1 << 5 ) /* (SPI) End of Receiver Transfer */
[all …]
/Kernel-v11.1.0/portable/IAR/ARM_CM23_NTZ/non_secure/
Dportasm.s133 movs r3, #5 /* r3 = 5. */
134 str r3, [r1] /* Program RNR = 5. */
305 movs r3, #5 /* r3 = 5. */
306 str r3, [r1] /* Program RNR = 5. */
/Kernel-v11.1.0/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/
Dportasm.c82 " movs r3, #5 \n" /* r3 = 5. */ in vRestoreContextOfFirstTask()
83 " str r3, [r1] \n" /* Program RNR = 5. */ in vRestoreContextOfFirstTask()
336 " movs r3, #5 \n" /* r3 = 5. */ in PendSV_Handler()
337 " str r3, [r1] \n" /* Program RNR = 5. */ in PendSV_Handler()
/Kernel-v11.1.0/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/
Dportasm.s133 movs r3, #5 /* r3 = 5. */
134 str r3, [r1] /* Program RNR = 5. */
305 movs r3, #5 /* r3 = 5. */
306 str r3, [r1] /* Program RNR = 5. */
/Kernel-v11.1.0/portable/GCC/ARM_CM23_NTZ/non_secure/
Dportasm.c82 " movs r3, #5 \n" /* r3 = 5. */ in vRestoreContextOfFirstTask()
83 " str r3, [r1] \n" /* Program RNR = 5. */ in vRestoreContextOfFirstTask()
336 " movs r3, #5 \n" /* r3 = 5. */ in PendSV_Handler()
337 " str r3, [r1] \n" /* Program RNR = 5. */ in PendSV_Handler()

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