Home
last modified time | relevance | path

Searched +full:- +full:- +full:one +full:- +full:top +full:- +full:level (Results 1 – 20 of 20) sorted by relevance

/Kernel-v11.1.0/portable/ThirdParty/XCC/Xtensa/
Dxtensa_vectors.S3 * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
6 * SPDX-License-Identifier: MIT
31 XTENSA VECTORS AND LOW LEVEL HANDLERS FOR AN RTOS
33 Xtensa low level exception and interrupt vectors and handlers for an RTOS.
40 Users can install application-specific interrupt handlers for low and
41 medium level interrupts, by calling xt_set_interrupt_handler(). These
47 dispatched to the RTOS-specific handler. This timer cannot be hooked
50 Optional hooks are also provided to install a handler per level at
51 run-time, made available by compiling this source file with
52 '-DXT_INTEXC_HOOKS' (useful for automated testing).
[all …]
Dreadme_xtensa.txt8 ------------
18 --------------------------------------------------
26 NOTE: It may be possible to build and run this with the open-source
27 xtensa-linux tools provided you have the correct overlay for your Xtensa
33 thread-safety on a per task basis (for use in tasks only, not interrupt
48 - Timer interrupt option with at least one interruptible timer.
49 - Interrupt option (implied by the timer interrupt option).
50 - Exception Architecture 2 (XEA2). Please note that XEA1 is NOT supported.
60 interrupt-driven drivers - it is not specific to any RTOS. Note that
63 and drivers for any on-board devices you want to use.
[all …]
Dportasm.S3 * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
6 * SPDX-License-Identifier: MIT
96 /* Save a12-13 in the stack frame as required by _xt_context_save. */
103 /* Save the rest of the interrupted context (preserves A12-13). */
123 s32i a1, a2, TOPOFSTACK_OFFS /* pxCurrentTCB->pxTopOfStack = SP */
124 movi a1, port_IntStackTop /* a1 = top of intr stack */
157 addi a2, a2, -1 /* decrement nesting count */
164 l32i a1, a2, TOPOFSTACK_OFFS /* SP = pxCurrentTCB->pxTopOfStack */
174 Call0 ABI callee-saved regs a12-15 need to be saved before possible preemption.
175 However a12-13 were already saved by _frxt_int_enter().
[all …]
/Kernel-v11.1.0/portable/ThirdParty/GCC/Xtensa_ESP32/
Dxtensa_vectors.S2 * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc.
4 * SPDX-License-Identifier: MIT
6 * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
9 * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
32 --------------------------------------------------------------------------------
34 XTENSA VECTORS AND LOW LEVEL HANDLERS FOR AN RTOS
36 Xtensa low level exception and interrupt vectors and handlers for an RTOS.
43 Users can install application-specific interrupt handlers for low and
44 medium level interrupts, by calling xt_set_interrupt_handler(). These
50 dispatched to the RTOS-specific handler. This timer cannot be hooked
[all …]
Dport.c2 * SPDX-FileCopyrightText: 2020 Amazon.com, Inc. or its affiliates
3 * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc.
5 * SPDX-License-Identifier: MIT
7 * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
39 * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
101 /*-----------------------------------------------------------*/
104 unsigned port_interruptNesting[ portNUM_PROCESSORS ] = { 0 }; /* Interrupt nesting level. Increased…
106 /*-----------------------------------------------------------*/
127 /* *INDENT-OFF* */
138 /* *INDENT-ON* */ in pxPortInitialiseStack()
[all …]
Dportasm.S2 * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc.
4 * SPDX-License-Identifier: MIT
6 * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
9 * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
57 .space portNUM_PROCESSORS*4 /* One flag for each individual CPU. */
110 /* Save a12-13 in the stack frame as required by _xt_context_save. */
117 /* Save the rest of the interrupted context (preserves A12-13). */
141 s32i a1, a2, TOPOFSTACK_OFFS /* pxCurrentTCB->pxTopOfStack = SP */
142 movi a1, port_IntStack+configISR_STACK_SIZE /* a1 = top of intr stack for CPU 0 */
143 …movi a2, configISR_STACK_SIZE /* add configISR_STACK_SIZE * cpu_num to arrive at top of stac…
[all …]
/Kernel-v11.1.0/include/
Dstream_buffer.h5 * SPDX-License-Identifier: MIT
30 * Stream buffers are used to send a continuous stream of data from one task or
37 * are built on top of stream buffers) assumes there is only one task or
38 * interrupt that will write to the buffer (the writer), and only one task or
59 /* *INDENT-OFF* */
63 /* *INDENT-ON* */
105 * able to hold at any one time.
110 * of an empty stream buffer that has a trigger level of 1 then the task will be
113 * stream buffer that has a trigger level of 10 then the task will not be
116 * trigger level is reached then the task will still receive however many bytes
[all …]
/Kernel-v11.1.0/.github/workflows/
Dcoverity_scan.yml10 bashPass: \033[32;1mPASSED -
11 bashInfo: \033[33;1mINFO -
12 bashFail: \033[31;1mFAILED -
16 Coverity-Scan:
17 if: ( github.repository == 'FreeRTOS/FreeRTOS-Kernel' )
19 runs-on: ubuntu-latest
21 - name: Checkout the Repository
24 - env:
29 echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
31 sudo apt-get -y update
[all …]
/Kernel-v11.1.0/
DCMakeLists.txt3 # User is responsible to one mandatory option:
6 # User is responsible for one library target:
9 # DEPRECATED: FREERTOS_CONFIG_FILE_DIRECTORY - but still supported if no freertos_config defined fo…
31 …message(WARNING " Using deprecated 'FREERTOS_CONFIG_FILE_DIRECTORY' - please update your project C…
44 …message(WARNING " FREERTOS_PORT is not set. Please specify it from top-level CMake file (example):…
47 " -DFREERTOS_PORT=GCC_ARM_CM4F\n"
50 " A_CUSTOM_PORT - Compiler: User Defined Target: User Defined\n"
51 " BCC_16BIT_DOS_FLSH186 - Compiler: BCC Target: 16 bit DOS Flsh186\n"
52 " BCC_16BIT_DOS_PC - Compiler: BCC Target: 16 bit DOS PC\n"
53 " CCS_ARM_CM3 - Compiler: CCS Target: ARM Cortex-M3\n"
[all …]
DHistory.txt5 + Add ARMv7-R port with Memory Protection Unit (MPU) support.
6 + Add Memory Protection Unit (MPU) support to the Cortex-M0 port.
8 buffer when a task reads from a non-empty buffer:
9 - The task reading from a non-empty stream buffer returns immediately
11 - The task reading from a non-empty steam batching buffer blocks until the
12 amount of data in the buffer exceeds the trigger level or the block time
37 + Add 64-bit support to the FreeRTOS Windows Simulator port. We thank @watsk
39 + Add support for 64-bit Microblaze processor to the MicroblazeV9 port. We
43 compilers. We thank @Forty-Bot for their contribution.
54 POSIX timers to address issues with signal handling in non-FreeRTOS
[all …]
Dtasks.c5 * SPDX-License-Identifier: MIT
44 /* The default definitions are only available for non-MPU ports. The
89 if( pxCurrentTCB->uxPriority < ( pxTCB )->uxPriority ) \
102 …#define taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxTCB ) prvYieldCore( ( pxTCB )->xTaskRunState…
175 /*-----------------------------------------------------------*/
186 --uxTopPriority; \
200 /*-----------------------------------------------------------*/
217 /*-----------------------------------------------------------*/
229 /*-----------------------------------------------------------*/
244 /*-----------------------------------------------------------*/
[all …]
/Kernel-v11.1.0/portable/GCC/MicroBlaze/
Dport.c5 * SPDX-License-Identifier: MIT
29 /*-----------------------------------------------------------
31 *----------------------------------------------------------*/
53 /* Tasks are started with a critical section nesting of 0 - however prior
54 * to the scheduler being commenced we don't want the critical nesting level
58 /* Our hardware setup only uses one counter. */
74 /*-----------------------------------------------------------*/
81 /*-----------------------------------------------------------*/
103 pxTopOfStack--; in pxPortInitialiseStack()
105 pxTopOfStack--; in pxPortInitialiseStack()
[all …]
/Kernel-v11.1.0/portable/GCC/IA32_flat/
Dport.c5 * SPDX-License-Identifier: MIT
92 /*-----------------------------------------------------------*/
105 * Complete one descriptor in the IDT.
137 /*-----------------------------------------------------------*/
192 /* Don't use the very top of the system stack so the return address
194 …ystemStack __attribute__( ( used ) ) = ( uint32_t ) &( ulSystemStack[ configISR_STACK_SIZE - 5 ] );
206 /*-----------------------------------------------------------*/
220 pxTopOfStack--; in pxPortInitialiseStack()
222 pxTopOfStack--; in pxPortInitialiseStack()
226 pxTopOfStack--; in pxPortInitialiseStack()
[all …]
/Kernel-v11.1.0/portable/IAR/AtmelSAM7S64/
DAT91SAM7X256_inc.h1 /* ---------------------------------------------------------------------------- */
2 /* ATMEL Microcontroller Software Support - ROUSSET - */
3 /* ---------------------------------------------------------------------------- */
6 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
14 /* ---------------------------------------------------------------------------- */
44 /* ---------------------------------------------------------------------------- */
74 /* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */
75 #define AT91C_AIC_PRIOR ( 0x7 << 0 ) /* (AIC) Priority Level */
76 #define AT91C_AIC_PRIOR_LOWEST ( 0x0 ) /* (AIC) Lowest priority level */
77 #define AT91C_AIC_PRIOR_HIGHEST ( 0x7 ) /* (AIC) Highest priority level */
[all …]
DAT91SAM7X128_inc.h1 /* ---------------------------------------------------------------------------- */
2 /* ATMEL Microcontroller Software Support - ROUSSET - */
3 /* ---------------------------------------------------------------------------- */
6 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
14 /* ---------------------------------------------------------------------------- */
44 /* ---------------------------------------------------------------------------- */
74 /* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */
75 #define AT91C_AIC_PRIOR ( 0x7 << 0 ) /* (AIC) Priority Level */
76 #define AT91C_AIC_PRIOR_LOWEST ( 0x0 ) /* (AIC) Lowest priority level */
77 #define AT91C_AIC_PRIOR_HIGHEST ( 0x7 ) /* (AIC) Highest priority level */
[all …]
DAT91SAM7X128.h1 /* ---------------------------------------------------------------------------- */
2 /* ATMEL Microcontroller Software Support - ROUSSET - */
3 /* ---------------------------------------------------------------------------- */
6 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
14 /* ---------------------------------------------------------------------------- */
44 /* ---------------------------------------------------------------------------- */
122 AT91_REG PIOA_MDER; /* Multi-driver Enable Register */
123 AT91_REG PIOA_MDDR; /* Multi-driver Disable Register */
124 AT91_REG PIOA_MDSR; /* Multi-driver Status Register */
126 AT91_REG PIOA_PPUDR; /* Pull-up Disable Register */
[all …]
DAT91SAM7X256.h1 /* ---------------------------------------------------------------------------- */
2 /* ATMEL Microcontroller Software Support - ROUSSET - */
3 /* ---------------------------------------------------------------------------- */
6 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
14 /* ---------------------------------------------------------------------------- */
44 /* ---------------------------------------------------------------------------- */
122 AT91_REG PIOA_MDER; /* Multi-driver Enable Register */
123 AT91_REG PIOA_MDDR; /* Multi-driver Disable Register */
124 AT91_REG PIOA_MDSR; /* Multi-driver Status Register */
126 AT91_REG PIOA_PPUDR; /* Pull-up Disable Register */
[all …]
/Kernel-v11.1.0/portable/GCC/ARM7_AT91SAM7S/
Dioat91sam7x256.h1 /* - ---------------------------------------------------------------------------- */
2 /* - ATMEL Microcontroller Software Support - ROUSSET - */
3 /* - ---------------------------------------------------------------------------- */
4 /* - DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
5 /* - IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
6 /* - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
7 /* - DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
8 /* - INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
9 /* - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
10 /* - OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
[all …]
DAT91SAM7X256.h1 /* ---------------------------------------------------------------------------- */
2 /* ATMEL Microcontroller Software Support - ROUSSET - */
3 /* ---------------------------------------------------------------------------- */
6 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
14 /* ---------------------------------------------------------------------------- */
44 /* ---------------------------------------------------------------------------- */
122 AT91_REG PIOA_MDER; /* Multi-driver Enable Register */
123 AT91_REG PIOA_MDDR; /* Multi-driver Disable Register */
124 AT91_REG PIOA_MDSR; /* Multi-driver Status Register */
126 AT91_REG PIOA_PPUDR; /* Pull-up Disable Register */
[all …]
/Kernel-v11.1.0/portable/GCC/ARM_CRx_MPU/
Dport.c5 * SPDX-License-Identifier: MIT
51 #define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) )
52 /* ----------------------------------------------------------------------------------- */
89 /* -------------------------- Private Function Declarations -------------------------- */
130 /* -------------------------- Exported Function Declarations -------------------------- */
146 /* ----------------------------------------------------------------------------------- */
153 * @param pxTopOfStack Top of stack.
170 UBaseType_t ulIndex = CONTEXT_SIZE - 1U; in pxPortInitialiseStack()
176 xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; in pxPortInitialiseStack()
178 xMPUSettings->ulContext[ ulIndex ] = SYS_MODE; in pxPortInitialiseStack()
[all …]