1 /*
2  * Copyright (c) 2018 ARM Limited
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  *     http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
17 #ifndef __TARGET_CFG_H__
18 #define __TARGET_CFG_H__
19 
20 #include "uart_stdout.h"
21 #include "tfm_peripherals_def.h"
22 
23 #define TFM_DRIVER_STDIO    Driver_USART0
24 #define NS_DRIVER_STDIO     Driver_USART0
25 
26 /*
27 // <o>Floating Point Unit usage
28 //     <0=> Secure state only
29 //     <3=> Secure and Non-Secure state
30 //   <i> Value for SCB->NSACR register bits CP10, CP11
31 */
32 #define SCB_NSACR_CP10_11_VAL       3
33 
34 /*
35 // <o>Treat floating-point registers as Secure
36 //     <0=> Disabled
37 //     <1=> Enabled
38 //   <i> Value for FPU->FPCCR register bit TS
39 */
40 #define FPU_FPCCR_TS_VAL            0
41 
42 /*
43 // <o>Clear on return (CLRONRET) accessibility
44 //     <0=> Secure and Non-Secure state
45 //     <1=> Secure state only
46 //   <i> Value for FPU->FPCCR register bit CLRONRETS
47 */
48 #define FPU_FPCCR_CLRONRETS_VAL     0
49 
50 /*
51 // <o>Clear floating-point caller saved registers on exception return
52 //     <0=> Disabled
53 //     <1=> Enabled
54 //   <i> Value for FPU->FPCCR register bit CLRONRET
55 */
56 #define FPU_FPCCR_CLRONRET_VAL      1
57 
58 
59 
60 typedef enum
61 {
62   TFM_FALSE = 0U,
63   TFM_TRUE = !TFM_FALSE
64 } TFM_BoolTypeDef;
65 
66 typedef enum
67 {
68   TFM_DISABLE = 0U,
69   TFM_ENABLE = !TFM_DISABLE
70 } TFM_FunctionalState;
71 
72 struct sau_cfg_t {
73     uint32_t RNR;
74     uint32_t RBAR;
75     uint32_t RLAR;
76     TFM_BoolTypeDef nsc;
77 #ifdef FLOW_CONTROL
78     uint32_t flow_step_enable;
79     uint32_t flow_ctrl_enable;
80     uint32_t flow_step_check;
81     uint32_t flow_ctrl_check;
82 #endif
83 };
84 
85 /**
86   * \brief Store the addresses of memory regions
87   */
88 struct memory_region_limits
89 {
90   uint32_t non_secure_code_start;
91   uint32_t non_secure_partition_base;
92   uint32_t non_secure_partition_limit;
93   uint32_t veneer_base;
94   uint32_t veneer_limit;
95 };
96 
97 /**
98  * \brief Holds the data necessary to do isolation for a specific peripheral.
99  */
100 struct platform_data_t
101 {
102     uint32_t periph_start;
103     uint32_t periph_limit;
104     int16_t periph_ppc_bank;
105     int16_t periph_ppc_loc;
106 };
107 
108 /**
109  * \brief Configures the Memory Protection Controller.
110  */
111 //void gtzc_init_cfg(void);
112 
113 
114 /**
115  * \brief pin mux configuration for non secure access
116  * */
117 void pinmux_init_cfg(void);
118 
119 
120 /**
121  * \brief Configures SAU and IDAU.
122  */
123 void sau_and_idau_cfg(void);
124 
125 /**
126  * \brief Enable Fault handling.
127  */
128 enum tfm_plat_err_t enable_fault_handlers(void);
129 
130 /**
131  * \brief Set NVIC interrupt target state to NS.
132  */
133 enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void);
134 
135 #endif /* __TARGET_CFG_H__ */
136