1 /*
2 * SPDX-License-Identifier: BSD-3-Clause
3 * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors
4 *
5 */
6
7 #include "tfm_hal_device_header.h"
8 #include "tfm_peripherals_def.h"
9 #include "common_target_cfg.h"
10 #include "tfm_hal_platform.h"
11 #include "uart_stdout.h"
12 #include "region.h"
13 #include "region_defs.h"
14 #include "pico/bootrom.h"
15
16 #include "hardware/structs/psm.h"
17 #ifdef TFM_MULTI_CORE_TOPOLOGY
18 #include "platform_multicore.h"
19 #include "hardware/structs/sio.h"
20 #endif
21
22 #if defined(TFM_PARTITION_SLIH_TEST) || defined(TFM_PARTITION_FLIH_TEST)
23 #include "hardware/irq.h"
24 extern void tfm_plat_test_secure_timer_irq_handler(void);
25 #endif
26
27 /* The section names come from the scatter file */
28 REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base);
29 REGION_DECLARE(Image$$, ER_VENEER, $$Base);
30 REGION_DECLARE(Image$$, VENEER_ALIGN, $$Limit);
31 #ifdef BL2
32 REGION_DECLARE(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base);
33 #endif /* BL2 */
34
35 const struct memory_region_limits memory_regions = {
36 .non_secure_code_start =
37 (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) +
38 BL2_HEADER_SIZE,
39
40 .non_secure_partition_base =
41 (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base),
42
43 .non_secure_partition_limit =
44 (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) +
45 NS_PARTITION_SIZE - 1,
46
47 .veneer_base =
48 (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base),
49
50 .veneer_limit =
51 (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit) - 1,
52
53 #ifdef BL2
54 .secondary_partition_base =
55 (uint32_t)®ION_NAME(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base),
56
57 .secondary_partition_limit =
58 (uint32_t)®ION_NAME(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base) +
59 SECONDARY_PARTITION_SIZE - 1,
60 #endif /* BL2 */
61 };
62
63 extern __NO_RETURN void MemManage_Handler(void);
64 extern __NO_RETURN void BusFault_Handler(void);
65 extern __NO_RETURN void UsageFault_Handler(void);
66 extern __NO_RETURN void SecureFault_Handler(void);
67
tfm_hal_platform_init(void)68 enum tfm_hal_status_t tfm_hal_platform_init(void)
69 {
70 NVIC_SetVector(MemoryManagement_IRQn, (uint32_t) MemManage_Handler);
71 NVIC_SetVector(BusFault_IRQn, (uint32_t) BusFault_Handler);
72 NVIC_SetVector(UsageFault_IRQn, (uint32_t) UsageFault_Handler);
73 NVIC_SetVector(SecureFault_IRQn, (uint32_t) SecureFault_Handler);
74
75 stdio_init();
76
77 #if defined(TFM_PARTITION_SLIH_TEST) || defined(TFM_PARTITION_FLIH_TEST)
78 irq_set_exclusive_handler(TFM_TIMER0_IRQ, tfm_plat_test_secure_timer_irq_handler);
79 #endif
80
81 #ifdef PSA_API_TEST_IPC
82 irq_set_exclusive_handler(FF_TEST_UART_IRQ, FF_TEST_UART_IRQ_Handler);
83 #endif
84
85 /* Reset everything apart from ROSC and XOSC */
86 hw_set_bits(&psm_hw->wdsel, PSM_WDSEL_BITS & ~(PSM_WDSEL_ROSC_BITS | PSM_WDSEL_XOSC_BITS));
87
88 __enable_irq();
89 return TFM_HAL_SUCCESS;
90 }
91
tfm_hal_get_ns_VTOR(void)92 uint32_t tfm_hal_get_ns_VTOR(void)
93 {
94 return memory_regions.non_secure_code_start;
95 }
96
tfm_hal_get_ns_MSP(void)97 uint32_t tfm_hal_get_ns_MSP(void)
98 {
99 return *((uint32_t *)memory_regions.non_secure_code_start);
100 }
101
tfm_hal_get_ns_entry_point(void)102 uint32_t tfm_hal_get_ns_entry_point(void)
103 {
104 return *((uint32_t *)(memory_regions.non_secure_code_start + 4));
105 }
106
tfm_hal_system_reset(void)107 void tfm_hal_system_reset(void)
108 {
109 __disable_irq();
110
111 NVIC_SystemReset();
112 }
113
tfm_hal_system_halt(void)114 void tfm_hal_system_halt(void)
115 {
116 __disable_irq();
117
118 #ifdef TFM_MULTI_CORE_TOPOLOGY
119 /* Signal Core1 to wait for flash */
120 sio_hw->doorbell_out_set = HALT_DOORBELL_MASK;
121 #endif
122
123 while (1) {
124 __WFE();
125 }
126
127 }
128
