1 /*
2  *  SPDX-License-Identifier: BSD-3-Clause
3  *  SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors
4  *
5  */
6 
7 #ifndef __TARGET_CFG_H__
8 #define __TARGET_CFG_H__
9 
10 #include <stdint.h>
11 
12 #define TFM_DRIVER_STDIO    driver_usart0
13 #define NS_DRIVER_STDIO     driver_usart0
14 
15 /**
16  * \brief Defines the word offsets of Slave Peripheral Protection Controller
17  *        Registers
18  */
19 typedef enum
20 {
21     PPC_SP_DO_NOT_CONFIGURE = -1,
22 } ppc_bank_t;
23 
24 typedef enum
25 {
26     AC_LOCK = 0x0,
27     AC_FORCE_CORE_NS = 0x4,
28     AC_CFGRESET = 0x8,
29     AC_GPIO_NSMASK0 = 0xC,
30     AC_GPIO_NSMASK1 = 0x10,
31     AC_ROM = 0x14,
32     AC_XIP_MAIN = 0x18,
33     AC_SRAM0 = 0x1C,
34     AC_SRAM1 = 0x20,
35     AC_SRAM2 = 0x24,
36     AC_SRAM3 = 0x28,
37     AC_SRAM4 = 0x2C,
38     AC_SRAM5 = 0x30,
39     AC_SRAM6 = 0x34,
40     AC_SRAM7 = 0x38,
41     AC_SRAM8 = 0x3C,
42     AC_SRAM9 = 0x40,
43     AC_DMA = 0x44,
44     AC_USBCTRL = 0x48,
45     AC_PIO0 = 0x4C,
46     AC_PIO1 = 0x50,
47     AC_PIO2 = 0x54,
48     AC_CORESIGHT_TRACE = 0x58,
49     AC_CORESIGHT_PERIPH = 0x5C,
50     AC_SYSINFO = 0x60,
51     AC_RESETS = 0x64,
52     AC_IO_BANK0 = 0x68,
53     AC_IO_BANK1 = 0x6C,
54     AC_PADS_BANK0 = 0x70,
55     AC_PADS_QSPI = 0x74,
56     AC_BUSCTRL = 0x78,
57     AC_ADC0 = 0x7C,
58     AC_HSTX = 0x80,
59     AC_I2C0 = 0x84,
60     AC_I2C1 = 0x88,
61     AC_PWM = 0x8C,
62     AC_SPI0 = 0x90,
63     AC_SPI1 = 0x94,
64     AC_TIMER0 = 0x98,
65     AC_TIMER1 = 0x9C,
66     AC_UART0 = 0xA0,
67     AC_UART1 = 0xA4,
68     AC_OTP = 0xA8,
69     AC_TBMAN = 0xAC,
70     AC_POWMAN = 0xB0,
71     AC_TRNG = 0xB4,
72     AC_SHA256 = 0xB8,
73     AC_SYSCFG = 0xBC,
74     AC_CLOCKS_BANK_DEFAULT = 0xC0,
75     AC_XOSC = 0xC4,
76     AC_ROSC = 0xC8,
77     AC_PLL_SYS = 0xCC,
78     AC_PLL_USB = 0xD0,
79     AC_TICKS = 0xD4,
80     AC_WATCHDOG = 0xD8,
81     AC_RSM = 0xDC,
82     AC_XIP_CTRL = 0xE0,
83     AC_XIP_QMI = 0xE4,
84     AC_XIP_AUX = 0xE8,
85     AC_DO_NOT_CONFIGURE = 0xFFFF,
86 } access_ctrl_reg_offset;
87 
88 /**
89  * \brief Initialize SAU.
90  */
91 void sau_and_idau_cfg(void);
92 
93 /**
94  * \brief Configure access control for bus endpoints.
95  */
96 enum tfm_plat_err_t bus_filter_cfg(void);
97 
98 /**
99  * \brief Configure DMA channels' security
100  */
101 enum tfm_plat_err_t dma_security_config(void);
102 
103 /**
104  * \brief Configure bus endpoint to be secure privileged accessible for core0
105  */
106 void access_ctrl_configure_to_secure_privileged(access_ctrl_reg_offset offset);
107 
108 
109 /**
110  * \brief Configure bus endpoint to be secure unprivileged accessible for core0
111  */
112 void access_ctrl_configure_to_secure_unprivileged(access_ctrl_reg_offset offset);
113 
114 #endif /* __TARGET_CFG_H__ */
115