1 /*
2 * Copyright (c) 2018-2022 Arm Limited. All rights reserved.
3 * Copyright 2019-2023 NXP. All rights reserved.
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 */
17
18 #include <assert.h>
19
20 #include "target_cfg.h"
21 #include "Driver_Common.h"
22 #include "platform_description.h"
23 #include "device_definition.h"
24 #include "region_defs.h"
25 #include "tfm_plat_defs.h"
26 #include "utilities.h"
27 #include "tfm_spm_log.h"
28
29 extern const struct memory_region_limits memory_regions;
30
31 struct platform_data_t tfm_peripheral_std_uart = {
32 USART0_BASE_NS,
33 USART0_BASE_NS + 0xFFF,
34 0,
35 0
36 };
37
38 struct platform_data_t tfm_peripheral_timer0 = {
39 CTIMER2_BASE,
40 CTIMER2_BASE + 0xFFF,
41 &(AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE1_MEM_CTRL1),
42 AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT
43 };
44
45 /*------------------- Memory configuration functions -------------------------*/
46
mpc_init_cfg(void)47 int32_t mpc_init_cfg(void)
48 {
49 uint32_t ns_region_id = 0;
50 uint32_t ns_region_start_id = 0;
51 uint32_t ns_region_end_id = 0;
52
53 /*
54 * Starts changing actual configuration so issue DMB to ensure every
55 * transaction has completed by now
56 */
57 __DMB();
58
59 /* Configuration of AHB Secure Controller
60 * Possible values for every memory sector or peripheral rule:
61 * 0 Non-secure, user access allowed.
62 * 1 Non-secure, privileged access allowed.
63 * 2 Secure, user access allowed.
64 * 3 Secure, privileged access allowed. */
65
66 /* == Flash region == */
67
68 /* The regions have to be alligned to 32 kB to cover the AHB Flash Region. */
69 assert((memory_regions.non_secure_partition_base % FLASH_SUBREGION_SIZE) == 0);
70 assert(((memory_regions.non_secure_partition_limit+1) % FLASH_SUBREGION_SIZE) == 0);
71
72 /* Flash region is divided into 20 sub-regions (sector). Each flash sub-regions (sector) is 32 kbytes. */
73 /* 1) Set FLASH memory security access rule configuration to init value (0x3 = all regions set to secure and privileged user access) */
74 AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[0] = 0x33333333U;
75 AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[1] = 0x33333333U;
76 AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[2] = 0x33333333U;
77
78 /* 2) Set FLASH memory security access rule configuration (set to non-secure and non-privileged user access allowed).*/
79 ns_region_start_id = memory_regions.non_secure_partition_base/FLASH_SUBREGION_SIZE;
80 ns_region_end_id = (memory_regions.non_secure_partition_limit+1)/FLASH_SUBREGION_SIZE;
81
82 /* Set to non-secure and non-privileged user access allowed */
83 for(ns_region_id = ns_region_start_id; ns_region_id < ns_region_end_id; ns_region_id++)
84 {
85 if(ns_region_id < 8)
86 {
87 /* Set regions the AHB controller for flash memory 0x0000_0000 - 0x0004_0000 */
88 AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[0] &= ~(0xF << (ns_region_id*4));
89 }
90 else if((ns_region_id >= 8) && (ns_region_id < 16))
91 {
92 /* Set regions in the AHB controller for flash memory 0x0004_0000 - 0x0008_0000 */
93 AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[1] &= ~(0xF << ((ns_region_id-8)*4));
94 }else if((ns_region_id >= 16) && (ns_region_id < 24))
95 {
96 /* Set regions the AHB controller for flash memory 0x0008_0000 - 0x0009_8000 */
97 AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[2] &= ~(0xF << ((ns_region_id-16)*4));
98 }
99 }
100
101 #ifdef BL2 /* Set secondary image region to NS, when BL2 is enabled */
102 /* The regions have to be alligned to 32 kB to cover the AHB Flash Region. */
103 assert((memory_regions.secondary_partition_base % FLASH_SUBREGION_SIZE) == 0);
104 assert(((memory_regions.secondary_partition_limit+1) % FLASH_SUBREGION_SIZE) == 0);
105
106 /* 2) Set FLASH memory security access rule configuration (set to non-secure and non-privileged user access allowed).*/
107 ns_region_start_id = memory_regions.secondary_partition_base/FLASH_SUBREGION_SIZE;
108 ns_region_end_id = (memory_regions.secondary_partition_limit+1)/FLASH_SUBREGION_SIZE;
109
110 /* Set to non-secure and non-privileged user access allowed */
111 for(ns_region_id = ns_region_start_id; ns_region_id < ns_region_end_id; ns_region_id++)
112 {
113 if(ns_region_id < 8)
114 {
115 /* Set regions the AHB controller for flash memory 0x0000_0000 - 0x0004_0000 */
116 AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[0] &= ~(0xF << (ns_region_id*4));
117 }
118 else if((ns_region_id >= 8) && (ns_region_id < 16))
119 {
120 /* Set regions in the AHB controller for flash memory 0x0004_0000 - 0x0008_0000 */
121 AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[1] &= ~(0xF << ((ns_region_id-8)*4));
122 }else if((ns_region_id >= 16) && (ns_region_id < 24))
123 {
124 /* Set regions the AHB controller for flash memory 0x0008_0000 - 0x0009_8000 */
125 AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[2] &= ~(0xF << ((ns_region_id-16)*4));
126 }
127 }
128 #endif
129
130 /* == ROM region == */
131
132 /* Each ROM sector is 4 kbytes. There are 32 ROM sectors in total. */
133 /* Security control ROM memory configuration (0x3 = all regions set to secure and privileged user access). */
134 AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_ROM_MEM_RULE[0] = 0x33333333U;
135 AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_ROM_MEM_RULE[1] = 0x33333333U;
136 AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_ROM_MEM_RULE[2] = 0x33333333U;
137 AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_ROM_MEM_RULE[3] = 0x33333333U;
138
139 /* == RAMX region == */
140
141 /* Each RAMX sub region is 4 kbytes.*/
142 /* Security access rules for RAMX (0x3 = all regions set to secure and privileged user access). */
143 AHB_SECURE_CTRL->SEC_CTRL_RAMX[0].MEM_RULE[0]= 0x33333333U; /* 0x0400_0000 - 0x0400_7FFF */
144
145 /* == SRAM region == */
146
147 /* The regions have to be alligned to 4 kB to cover the AHB RAM Region */
148 assert((S_DATA_SIZE % DATA_SUBREGION_SIZE) == 0);
149 assert(((S_DATA_SIZE + NS_DATA_SIZE) % DATA_SUBREGION_SIZE) == 0);
150
151 /* Security access rules for RAM (0x3 = all regions set to secure and privileged user access*/
152 AHB_SECURE_CTRL->SEC_CTRL_RAM0[0].MEM_RULE[0]= 0x33333333U; /* 0x2000_0000 - 0x2000_7FFF */
153 AHB_SECURE_CTRL->SEC_CTRL_RAM0[0].MEM_RULE[1]= 0x33333333U; /* 0x2000_8000 - 0x2000_FFFF */
154 AHB_SECURE_CTRL->SEC_CTRL_RAM1[0].MEM_RULE[0]= 0x33333333U; /* 0x2001_0000 - 0x2001_7FFF */
155 AHB_SECURE_CTRL->SEC_CTRL_RAM1[0].MEM_RULE[1]= 0x33333333U; /* 0x2001_8000 - 0x2001_FFFF */
156 AHB_SECURE_CTRL->SEC_CTRL_RAM2[0].MEM_RULE[0]= 0x33333333U; /* 0x2002_0000 - 0x2002_7FFF */
157 AHB_SECURE_CTRL->SEC_CTRL_RAM2[0].MEM_RULE[1]= 0x33333333U; /* 0x2002_8000 - 0x2002_FFFF */
158 AHB_SECURE_CTRL->SEC_CTRL_RAM3[0].MEM_RULE[0]= 0x33333333U; /* 0x2003_0000 - 0x2003_7FFF */
159 AHB_SECURE_CTRL->SEC_CTRL_RAM3[0].MEM_RULE[1]= 0x33333333U; /* 0x2003_8000 - 0x2003_FFFF */
160 AHB_SECURE_CTRL->SEC_CTRL_RAM4[0].MEM_RULE[0]= 0x33333333U; /* 0x2004_0000 - 0x2004_3FFF */
161
162 /* RAM memory configuration (set according to region_defs.h and flash_layout.h) */
163 ns_region_start_id = S_DATA_SIZE/DATA_SUBREGION_SIZE; /* NS starts after S */
164 ns_region_end_id = (S_DATA_SIZE + NS_DATA_SIZE)/DATA_SUBREGION_SIZE;
165
166 for(ns_region_id = ns_region_start_id; ns_region_id < ns_region_end_id; ns_region_id++)
167 {
168 /* Set regions the AHB controller for ram memory 0x2000_0000 - 0x2000_7FFF */
169 if(ns_region_id < 8) {
170 AHB_SECURE_CTRL->SEC_CTRL_RAM0[0].MEM_RULE[0] &= ~(0xF << (ns_region_id*4));
171 }
172 /* Set regions the AHB controller for ram memory 0x2000_8000 - 0x2000_FFFF */
173 else if((ns_region_id >= 8) && (ns_region_id < 16)) {
174 AHB_SECURE_CTRL->SEC_CTRL_RAM0[0].MEM_RULE[1] &= ~(0xF << ((ns_region_id-8)*4));
175 }
176 /* Set regions the AHB controller for ram memory 0x2001_0000 - 0x2001_7FFF */
177 else if((ns_region_id >= 16) && (ns_region_id < 24)) {
178 AHB_SECURE_CTRL->SEC_CTRL_RAM1[0].MEM_RULE[0] &= ~(0xF << ((ns_region_id-16)*4));
179 }
180 /* Set regions the AHB controller for ram memory 0x2001_8000 - 0x2001_FFFF */
181 else if((ns_region_id >= 24) && (ns_region_id < 32)) {
182 AHB_SECURE_CTRL->SEC_CTRL_RAM1[0].MEM_RULE[1] &= ~(0xF << ((ns_region_id-24)*4));
183 }
184 /* Set regions the AHB controller for ram memory 0x2002_0000 - 0x2002_7FFF */
185 else if((ns_region_id >= 32) && (ns_region_id < 40)) {
186 AHB_SECURE_CTRL->SEC_CTRL_RAM2[0].MEM_RULE[0] &= ~(0xF << ((ns_region_id-32)*4));
187 }
188 /* Set regions the AHB controller for ram memory 0x2002_8000 - 0x2002_FFFF */
189 else if((ns_region_id >= 40) && (ns_region_id < 48)) {
190 AHB_SECURE_CTRL->SEC_CTRL_RAM2[0].MEM_RULE[1] &= ~(0xF << ((ns_region_id-40)*4));
191 }
192 /* Set regions the AHB controller for ram memory 0x2003_0000 - 0x2003_7FFF */
193 else if((ns_region_id >= 48) && (ns_region_id < 56)) {
194 AHB_SECURE_CTRL->SEC_CTRL_RAM3[0].MEM_RULE[0] &= ~(0xF << ((ns_region_id-48)*4));
195 }
196 /* Set regions the AHB controller for ram memory 0x2003_8000 - 0x2003_FFFF */
197 else if((ns_region_id >= 56) && (ns_region_id < 64)) {
198 AHB_SECURE_CTRL->SEC_CTRL_RAM3[0].MEM_RULE[1] &= ~(0xF << ((ns_region_id-56)*4));
199 }
200 /* Set regions the AHB controller for ram memory 0x2004_0000 - 0x2004_3FFF */
201 else if((ns_region_id >= 64) && (ns_region_id < 72)) {
202 AHB_SECURE_CTRL->SEC_CTRL_RAM4[0].MEM_RULE[0] &= ~(0xF << ((ns_region_id-64)*4));
203 }
204 }
205
206 /* Security access rules for USB-HS RAM sub region 0_0 to 0_3. Each USB-HS RAM sub region is 4 kbytes */
207 AHB_SECURE_CTRL->SEC_CTRL_USB_HS[0].MEM_RULE[0] =
208 AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE(0x0U) | /* Address space: 0x4010_0000 - 0x4010_0FFF */
209 AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE(0x0U) | /* Address space: 0x4010_1000 - 0x4010_1FFF */
210 AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE(0x0U) | /* Address space: 0x4010_2000 - 0x4010_2FFF */
211 AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE(0x0U); /* Address space: 0x4010_3000 - 0x4010_3FFF */
212
213 #if TARGET_DEBUG_LOG
214 SPMLOG_DBGMSG("=== [AHB MPC NS] =======\r\n");
215 SPMLOG_DBGMSGVAL("NS ROM starts from : ",
216 memory_regions.non_secure_partition_base);
217 SPMLOG_DBGMSGVAL("NS ROM ends at : ",
218 memory_regions.non_secure_partition_base +
219 memory_regions.non_secure_partition_limit);
220 SPMLOG_DBGMSGVAL("NS DATA start from : ", NS_DATA_START);
221 SPMLOG_DBGMSGVAL("NS DATA ends at : ", NS_DATA_START + NS_DATA_LIMIT);
222 #endif
223
224 /* Add barriers to assure the MPC configuration is done before continue
225 * the execution.
226 */
227 __DSB();
228 __ISB();
229
230 return ARM_DRIVER_OK;
231 }
232
233 /*---------------------- PPC configuration functions -------------------------*/
234
ppc_init_cfg(void)235 int32_t ppc_init_cfg(void)
236 {
237 /* Configuration of AHB Secure Controller. Grant user access to peripherals.
238 * Possible values for every memory sector or peripheral rule:
239 * 0 Non-secure, user access allowed.
240 * 1 Non-secure, privileged access allowed.
241 * 2 Secure, user access allowed.
242 * 3 Secure, privileged access allowed. */
243
244 /* Write access attributes for AHB_SECURE_CTRL module are tier-4 (secure privileged). */
245
246 /* Security access rules for APB Bridge 0 peripherals. */
247 AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 =
248 (0x30000000U) | /* Bits have to be set to '1' according to UM.*/
249 AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(0x0U) | /* System configuration */
250 AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(0x0U) | /* I/O configuration */
251 AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(0x0U) | /* GPIO input Interrupt 0 */
252 AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(0x0U) | /* GPIO input Interrupt 1 */
253 AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(0x0U) | /* Pin Interrupt and Pattern match */
254 AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(0x0U) | /* Secure Pin Interrupt and Pattern match */
255 AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE(0x0U); /* Peripheral Input Multiplexing. */
256
257 AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 =
258 (0x30003300U) | /* Bits have to be set to '1' according to UM.*/
259 AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(0x0U) | /* Standard counter/Timer 0 */
260 AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(0x0U) | /* Standard counter/Timer 1 */
261 AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(0x0U) | /* Windowed watchdog Timer */
262 AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(0x0U) | /* Multi-rate Timer */
263 AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(0x0U); /* Micro-Timer */
264
265 AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 =
266 (0x33330333U) | /* Bits have to be set to '1' according to UM.*/
267 AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(0x0U); /* Analog modules controller */
268
269 /* Security access rules for APB Bridge 1 peripherals. */
270 AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 =
271 (0x33330330U) | /* Bits have to be set to '1' according to UM.*/
272 AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(0x0U) | /* Power Management Controller */
273 AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(0x0U); /* System Controller */
274
275 AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 =
276 (0x33003000U) | /* Bits have to be set to '1' according to UM.*/
277 AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(0x0U) | /* Standard counter/Timer 2 */
278 AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(0x0U) | /* Standard counter/Timer 3 */
279 AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(0x0U) | /* Standard counter/Timer 4 */
280 AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(0x0U) | /* Real Time Counter */
281 AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(0x0U); /* OS Event Timer */
282
283 AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 =
284 (0x33003333U) | /* Bits have to be set to '1' according to UM.*/
285 AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(0x3U) | /* Flash controller = S*/
286 AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(0x3U); /* PRINCE = S */
287
288 AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 =
289 /* 0x0F000000U | */
290 (0x33030030U) | /* Bits have to be set to '1' according to UM.*/
291 AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE(0x0U) | /* USB High Speed Phy controller */
292 AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(0x3U) | /* True Random Number Generator = S */
293 AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE(0x3U) | /* PUF = S*/
294 AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(0x0U); /* Programmable Look-Up logic */
295
296 /* Security access rules for AHB peripherals on AHB Slave Port P8*/
297 AHB_SECURE_CTRL->SEC_CTRL_AHB_PORT8_SLAVE0_RULE =
298 (0x00003033U) | /* Bits have to be set to '1' according to UM.*/
299 AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE(0x0U) | /* DMA0 */
300 AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE(0x0U) | /* USB */
301 AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE(0x0U) | /* SCT */
302 AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE(0x0U) | /* FLEXCOMM0 */
303 AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE(0x0U); /* FLEXCOMM1 */
304
305 AHB_SECURE_CTRL->SEC_CTRL_AHB_PORT8_SLAVE1_RULE =
306 (0x00300000U) | /* Bits have to be set to '1' according to UM.*/
307 AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE(0x0U) | /* FLEXCOMM2 */
308 AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE(0x0U) | /* FLEXCOMM3 */
309 AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE(0x0U) | /* FLEXCOMM4 */
310 AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE(0x0U) | /* MAILBOX */
311 AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE(0x0U); /* High Speed GPIO */
312
313 /* Security access rules for AHB peripherals on AHB Slave Port P9 */
314 AHB_SECURE_CTRL->SEC_CTRL_AHB_PORT9_SLAVE0_RULE =
315 (0x00003333U) | /* Bits have to be set to '1' according to UM.*/
316 AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE(0x0U) | /* USB high Speed device registers */
317 AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE(0x0U) | /* CRC engine */
318 AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE(0x0U) | /* FLEXCOMM5 */
319 AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE(0x0U); /* FLEXCOMM6 */
320
321 AHB_SECURE_CTRL->SEC_CTRL_AHB_PORT9_SLAVE1_RULE =
322 (0x03300330U) | /* Bits have to be set to '1' according to UM.*/
323 AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE(0x0U) | /* FLEXCOMM7 */
324 AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE(0x0U) | /* SDIO */
325 AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE(0x0U) | /* Debug mailbox (aka ISP-AP) */
326 AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE(0x0U); /* High Speed SPI */
327
328 /* Security access rules for AHB peripherals on AHB Slave Port P10. */
329 AHB_SECURE_CTRL->SEC_CTRL_AHB_PORT10[0].SLAVE0_RULE =
330 (0x00000030U) | /* Bits have to be set to '1' according to UM.*/
331 AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE(0x0U) | /* ADC */
332 AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE(0x0U) | /* USB Full Speed Host registers. */
333 AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE(0x0U) | /* USB High speed host registers */
334 AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE(0x3U) | /* SHA-2 crypto registers = S*/
335 AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE(0x3U) | /* RSA/ECC crypto accelerator = S */
336 AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE(0x0U) | /* Power Quad (CM33 processor hardware accelerator) */
337 AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE(0x0U); /* DMA Controller (Secure) */
338
339 AHB_SECURE_CTRL->SEC_CTRL_AHB_PORT10[0].SLAVE1_RULE =
340 AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE(0x0U) | /* Secure High Speed GPIO */
341 AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE(0x3U); /* AHB Secure Controller = S */
342
343 /* Security access rules for AHB secure control. */
344 AHB_SECURE_CTRL->SEC_CTRL_AHB_PORT10[0].SEC_CTRL_AHB_SEC_CTRL_MEM_RULE[0] =
345 AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(0x0U) | /* Address space: 0x400A_C000 - 0x400A_CFFF */
346 AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(0x0U) | /* Address space: 0x400A_D000 - 0x400A_DFFF */
347 AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(0x0U) | /* Address space: 0x400A_E000 - 0x400A_EFFF */
348 AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(0x0U); /* Address space: 0x400A_F000 - 0x400A_FFFF */
349
350 /* This register has the security access rules for the slave port P11 on AHB multilayer. This
351 slave port allows access to USB-HS RAM memories. This rule supersedes more granular
352 security rules as in SEC_CTRL_USB_HS_SLAVE_RULE */
353 AHB_SECURE_CTRL->SEC_CTRL_USB_HS[0].SLAVE_RULE =
354 AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE(0x0U);
355
356 /* Enable AHB secure controller check */
357 AHB_SECURE_CTRL->MISC_CTRL_REG = (AHB_SECURE_CTRL->MISC_CTRL_REG & ~(AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK | 0)) |
358 /* AHB bus matrix enable secure checking (restrictive mode). */
359 AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(0x1U);
360 /* Other default values:
361 - Write lock - secure_ctrl_group_rule registers and this register itself can be written.
362 - AHB bus matrix enable secure privilege check - disabled
363 - AHB bus matrix enable non-secure privilege check - disabled
364 - The violation detected by the secure checker causes abort.
365 - Simple master in strict mode. Can read and write to memories at same level only. (Mode recommended by ARM).
366 - Smart masters in strict mode. Can execute, read and write to memories at same level only. (Mode recommended by ARM.).
367 – IDAU is enabled.
368 */
369 /* Secure control duplicate register */
370 AHB_SECURE_CTRL->MISC_CTRL_DP_REG = (AHB_SECURE_CTRL->MISC_CTRL_DP_REG & ~( AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK | 0)) |
371 /* AHB bus matrix enable secure checking (restrictive mode). */
372 AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(0x1U);
373
374 return ARM_DRIVER_OK;
375 }
376
