1 /**************************************************************************//** 2 * @file epwm.h 3 * @version V3.00 4 * @brief M2354 series EPWM driver header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __EPWM_H__ 10 #define __EPWM_H__ 11 12 #ifdef __cplusplus 13 extern "C" 14 { 15 #endif 16 17 18 /** @addtogroup Standard_Driver Standard Driver 19 @{ 20 */ 21 22 /** @addtogroup EPWM_Driver EPWM Driver 23 @{ 24 */ 25 26 /** @addtogroup EPWM_EXPORTED_CONSTANTS EPWM Exported Constants 27 @{ 28 */ 29 #define EPWM_CHANNEL_NUM (6UL) /*!< EPWM channel number */ 30 #define EPWM_CH_0_MASK (0x1UL) /*!< EPWM channel 0 mask \hideinitializer */ 31 #define EPWM_CH_1_MASK (0x2UL) /*!< EPWM channel 1 mask \hideinitializer */ 32 #define EPWM_CH_2_MASK (0x4UL) /*!< EPWM channel 2 mask \hideinitializer */ 33 #define EPWM_CH_3_MASK (0x8UL) /*!< EPWM channel 3 mask \hideinitializer */ 34 #define EPWM_CH_4_MASK (0x10UL) /*!< EPWM channel 4 mask \hideinitializer */ 35 #define EPWM_CH_5_MASK (0x20UL) /*!< EPWM channel 5 mask \hideinitializer */ 36 37 /*---------------------------------------------------------------------------------------------------------*/ 38 /* Counter Type Constant Definitions */ 39 /*---------------------------------------------------------------------------------------------------------*/ 40 #define EPWM_UP_COUNTER (0UL) /*!< Up counter type */ 41 #define EPWM_DOWN_COUNTER (1UL) /*!< Down counter type */ 42 #define EPWM_UP_DOWN_COUNTER (2UL) /*!< Up-Down counter type */ 43 44 /*---------------------------------------------------------------------------------------------------------*/ 45 /* Aligned Type Constant Definitions */ 46 /*---------------------------------------------------------------------------------------------------------*/ 47 #define EPWM_EDGE_ALIGNED (1UL) /*!< EPWM working in edge aligned type(down count) */ 48 #define EPWM_CENTER_ALIGNED (2UL) /*!< EPWM working in center aligned type */ 49 50 /*---------------------------------------------------------------------------------------------------------*/ 51 /* Output Level Constant Definitions */ 52 /*---------------------------------------------------------------------------------------------------------*/ 53 #define EPWM_OUTPUT_NOTHING (0UL) /*!< EPWM output nothing */ 54 #define EPWM_OUTPUT_LOW (1UL) /*!< EPWM output low */ 55 #define EPWM_OUTPUT_HIGH (2UL) /*!< EPWM output high */ 56 #define EPWM_OUTPUT_TOGGLE (3UL) /*!< EPWM output toggle */ 57 58 /*---------------------------------------------------------------------------------------------------------*/ 59 /* Synchronous Start Function Control Constant Definitions */ 60 /*---------------------------------------------------------------------------------------------------------*/ 61 #define EPWM_SSCTL_SSRC_EPWM0 (0UL<<EPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from EPWM0 */ 62 #define EPWM_SSCTL_SSRC_EPWM1 (1UL<<EPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from EPWM1 */ 63 #define EPWM_SSCTL_SSRC_BPWM0 (2UL<<EPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from BPWM0 */ 64 #define EPWM_SSCTL_SSRC_BPWM1 (3UL<<EPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from BPWM1 */ 65 66 /*---------------------------------------------------------------------------------------------------------*/ 67 /* Trigger Source Select Constant Definitions */ 68 /*---------------------------------------------------------------------------------------------------------*/ 69 #define EPWM_TRG_ADC_EVEN_ZERO (0UL) /*!< EPWM trigger ADC while counter of even channel matches zero point */ 70 #define EPWM_TRG_ADC_EVEN_PERIOD (1UL) /*!< EPWM trigger ADC while counter of even channel matches period point */ 71 #define EPWM_TRG_ADC_EVEN_ZERO_PERIOD (2UL) /*!< EPWM trigger ADC while counter of even channel matches zero or period point */ 72 #define EPWM_TRG_ADC_EVEN_COMPARE_UP (3UL) /*!< EPWM trigger ADC while counter of even channel matches up count to comparator point */ 73 #define EPWM_TRG_ADC_EVEN_COMPARE_DOWN (4UL) /*!< EPWM trigger ADC while counter of even channel matches down count to comparator point */ 74 #define EPWM_TRG_ADC_ODD_ZERO (5UL) /*!< EPWM trigger ADC while counter of odd channel matches zero point */ 75 #define EPWM_TRG_ADC_ODD_PERIOD (6UL) /*!< EPWM trigger ADC while counter of odd channel matches period point */ 76 #define EPWM_TRG_ADC_ODD_ZERO_PERIOD (7UL) /*!< EPWM trigger ADC while counter of odd channel matches zero or period point */ 77 #define EPWM_TRG_ADC_ODD_COMPARE_UP (8UL) /*!< EPWM trigger ADC while counter of odd channel matches up count to comparator point */ 78 #define EPWM_TRG_ADC_ODD_COMPARE_DOWN (9UL) /*!< EPWM trigger ADC while counter of odd channel matches down count to comparator point */ 79 #define EPWM_TRG_ADC_CH_0_FREE_CMP_UP (10UL) /*!< EPWM trigger ADC while counter of channel 0 matches up count to free comparator point */ 80 #define EPWM_TRG_ADC_CH_0_FREE_CMP_DOWN (11UL) /*!< EPWM trigger ADC while counter of channel 0 matches down count to free comparator point */ 81 #define EPWM_TRG_ADC_CH_2_FREE_CMP_UP (12UL) /*!< EPWM trigger ADC while counter of channel 2 matches up count to free comparator point */ 82 #define EPWM_TRG_ADC_CH_2_FREE_CMP_DOWN (13UL) /*!< EPWM trigger ADC while counter of channel 2 matches down count to free comparator point */ 83 #define EPWM_TRG_ADC_CH_4_FREE_CMP_UP (14UL) /*!< EPWM trigger ADC while counter of channel 4 matches up count to free comparator point */ 84 #define EPWM_TRG_ADC_CH_4_FREE_CMP_DOWN (15UL) /*!< EPWM trigger ADC while counter of channel 4 matches down count to free comparator point */ 85 86 #define EPWM_TRIGGER_DAC_ZERO (0x1UL) /*!< EPWM trigger DAC while counter down count to 0 \hideinitializer */ 87 #define EPWM_TRIGGER_DAC_PERIOD (0x100UL) /*!< EPWM trigger DAC while counter matches (PERIOD + 1) \hideinitializer */ 88 #define EPWM_TRIGGER_DAC_COMPARE_UP (0x10000UL) /*!< EPWM trigger DAC while counter up count to CMPDAT \hideinitializer */ 89 #define EPWM_TRIGGER_DAC_COMPARE_DOWN (0x1000000UL) /*!< EPWM trigger DAC while counter down count to CMPDAT \hideinitializer */ 90 91 /*---------------------------------------------------------------------------------------------------------*/ 92 /* Fail brake Control Constant Definitions */ 93 /*---------------------------------------------------------------------------------------------------------*/ 94 #define EPWM_FB_EDGE_ACMP0 (EPWM_BRKCTL0_1_CPO0EBEN_Msk) /*!< Comparator 0 as edge-detect fault brake source */ 95 #define EPWM_FB_EDGE_ACMP1 (EPWM_BRKCTL0_1_CPO1EBEN_Msk) /*!< Comparator 1 as edge-detect fault brake source */ 96 #define EPWM_FB_EDGE_BKP0 (EPWM_BRKCTL0_1_BRKP0EEN_Msk) /*!< BKP0 pin as edge-detect fault brake source */ 97 #define EPWM_FB_EDGE_BKP1 (EPWM_BRKCTL0_1_BRKP1EEN_Msk) /*!< BKP1 pin as edge-detect fault brake source */ 98 #define EPWM_FB_EDGE_ADCRM (EPWM_BRKCTL0_1_EADCEBEN_Msk) /*!< ADC Result Monitor (ADCRM) as edge-detect fault brake source */ 99 #define EPWM_FB_EDGE_SYS_CSS (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as edge-detect fault brake source */ 100 #define EPWM_FB_EDGE_SYS_BOD (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as edge-detect fault brake source */ 101 #define EPWM_FB_EDGE_SYS_RAM (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_RAMBRKEN_Msk) /*!< System fail condition: SRAM parity error detection as edge-detect fault brake source */ 102 #define EPWM_FB_EDGE_SYS_COR (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_CORBRKEN_Msk) /*!< System fail condition: core lockup detection as edge-detect fault brake source */ 103 104 #define EPWM_FB_LEVEL_ACMP0 (EPWM_BRKCTL0_1_CPO0LBEN_Msk) /*!< Comparator 0 as level-detect fault brake source */ 105 #define EPWM_FB_LEVEL_ACMP1 (EPWM_BRKCTL0_1_CPO1LBEN_Msk) /*!< Comparator 1 as level-detect fault brake source */ 106 #define EPWM_FB_LEVEL_BKP0 (EPWM_BRKCTL0_1_BRKP0LEN_Msk) /*!< BKP0 pin as level-detect fault brake source */ 107 #define EPWM_FB_LEVEL_BKP1 (EPWM_BRKCTL0_1_BRKP1LEN_Msk) /*!< BKP1 pin as level-detect fault brake source */ 108 #define EPWM_FB_LEVEL_ADCRM (EPWM_BRKCTL0_1_EADCLBEN_Msk) /*!< ADC Result Monitor (ADCRM) as level-detect fault brake source */ 109 #define EPWM_FB_LEVEL_SYS_CSS (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as level-detect fault brake source */ 110 #define EPWM_FB_LEVEL_SYS_BOD (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as level-detect fault brake source */ 111 #define EPWM_FB_LEVEL_SYS_RAM (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_RAMBRKEN_Msk) /*!< System fail condition: SRAM parity error detection as level-detect fault brake source */ 112 #define EPWM_FB_LEVEL_SYS_COR (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_CORBRKEN_Msk) /*!< System fail condition: core lockup detection as level-detect fault brake source */ 113 114 #define EPWM_FB_EDGE (0UL) /*!< edge-detect fault brake */ 115 #define EPWM_FB_LEVEL (8UL) /*!< level-detect fault brake */ 116 117 /*---------------------------------------------------------------------------------------------------------*/ 118 /* Leading Edge Blanking Control Constant Definitions */ 119 /*---------------------------------------------------------------------------------------------------------*/ 120 #define EPWM_LEBCTL_TRGTYPE_RISING (0UL<<EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM Leading Edge Blanking Trigger Type Is Rising Edge \hideinitializer */ 121 #define EPWM_LEBCTL_TRGTYPE_FALLING (1UL<<EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM Leading Edge Blanking Trigger Type Is Falling Edge \hideinitializer */ 122 #define EPWM_LEBCTL_TRGTYPE_RISING_OR_FALLING (2UL<<EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM Leading Edge Blanking Trigger Type Is Rising or Falling Edge \hideinitializer */ 123 #define EPWM_LEBCTL_SRCEN0 (EPWM_LEBCTL_SRCEN0_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH0 Enable \hideinitializer */ 124 #define EPWM_LEBCTL_SRCEN2 (EPWM_LEBCTL_SRCEN2_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH2 Enable \hideinitializer */ 125 #define EPWM_LEBCTL_SRCEN4 (EPWM_LEBCTL_SRCEN4_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH4 Enable \hideinitializer */ 126 #define EPWM_LEBCTL_SRCEN0_2 (EPWM_LEBCTL_SRCEN0_Msk|EPWM_LEBCTL_SRCEN2_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH0 and EPWMx_CH2 Enable \hideinitializer */ 127 #define EPWM_LEBCTL_SRCEN0_4 (EPWM_LEBCTL_SRCEN0_Msk|EPWM_LEBCTL_SRCEN4_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH0 and EPWMx_CH4 Enable \hideinitializer */ 128 #define EPWM_LEBCTL_SRCEN2_4 (EPWM_LEBCTL_SRCEN2_Msk|EPWM_LEBCTL_SRCEN4_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH2 and EPWMx_CH4 Enable \hideinitializer */ 129 #define EPWM_LEBCTL_SRCEN0_2_4 (EPWM_LEBCTL_SRCEN0_Msk|EPWM_LEBCTL_SRCEN2_Msk|EPWM_LEBCTL_SRCEN4_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH0, EPWMx_CH2 and EPWMx_CH4 Enable \hideinitializer */ 130 131 /*---------------------------------------------------------------------------------------------------------*/ 132 /* Capture Control Constant Definitions */ 133 /*---------------------------------------------------------------------------------------------------------*/ 134 #define EPWM_CAPTURE_INT_RISING_LATCH (1UL) /*!< EPWM capture interrupt if channel has rising transition */ 135 #define EPWM_CAPTURE_INT_FALLING_LATCH (0x100UL) /*!< EPWM capture interrupt if channel has falling transition */ 136 137 #define EPWM_CAPTURE_PDMA_RISING_LATCH (0x2UL) /*!< EPWM capture rising latched data transfer by PDMA */ 138 #define EPWM_CAPTURE_PDMA_FALLING_LATCH (0x4UL) /*!< EPWM capture falling latched data transfer by PDMA */ 139 #define EPWM_CAPTURE_PDMA_RISING_FALLING_LATCH (0x6UL) /*!< EPWM capture rising and falling latched data transfer by PDMA */ 140 141 /*---------------------------------------------------------------------------------------------------------*/ 142 /* Duty Interrupt Type Constant Definitions */ 143 /*---------------------------------------------------------------------------------------------------------*/ 144 #define EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP (EPWM_INTEN0_CMPDIEN0_Msk) /*!< EPWM duty interrupt triggered if down count match comparator */ 145 #define EPWM_DUTY_INT_UP_COUNT_MATCH_CMP (EPWM_INTEN0_CMPUIEN0_Msk) /*!< EPWM duty interrupt triggered if up down match comparator */ 146 147 /*---------------------------------------------------------------------------------------------------------*/ 148 /* Interrupt Flag Accumulator Constant Definitions */ 149 /*---------------------------------------------------------------------------------------------------------*/ 150 #define EPWM_IFA_ZERO_POINT (0UL) /*!< EPWM counter equal to zero */ 151 #define EPWM_IFA_PERIOD_POINT (1UL) /*!< EPWM counter equal to period */ 152 #define EPWM_IFA_COMPARE_UP_COUNT_POINT (2UL) /*!< EPWM counter up count to comparator value */ 153 #define EPWM_IFA_COMPARE_DOWN_COUNT_POINT (3UL) /*!< EPWM counter down count to comparator value */ 154 155 /*---------------------------------------------------------------------------------------------------------*/ 156 /* Load Mode Constant Definitions */ 157 /*---------------------------------------------------------------------------------------------------------*/ 158 #define EPWM_LOAD_MODE_IMMEDIATE (EPWM_CTL0_IMMLDEN0_Msk) /*!< EPWM immediately load mode \hideinitializer */ 159 #define EPWM_LOAD_MODE_WINDOW (EPWM_CTL0_WINLDEN0_Msk) /*!< EPWM window load mode \hideinitializer */ 160 #define EPWM_LOAD_MODE_CENTER (EPWM_CTL0_CTRLD0_Msk) /*!< EPWM center load mode \hideinitializer */ 161 162 /*---------------------------------------------------------------------------------------------------------*/ 163 /* Synchronize Control Constant Definitions */ 164 /*---------------------------------------------------------------------------------------------------------*/ 165 #define EPWM_SYNC_OUT_FROM_SYNCIN_SWSYNC (0UL) /*!< Synchronize source from SYNC_IN or SWSYNC \hideinitializer */ 166 #define EPWM_SYNC_OUT_FROM_COUNT_TO_ZERO (1UL) /*!< Synchronize source from counter equal to 0 \hideinitializer */ 167 #define EPWM_SYNC_OUT_FROM_COUNT_TO_COMPARATOR (2UL) /*!< Synchronize source from counter equal to CMPDAT1, CMPDAT3, CMPDAT5 \hideinitializer */ 168 #define EPWM_SYNC_OUT_DISABLE (3UL) /*!< SYNC_OUT will not be generated \hideinitializer */ 169 #define EPWM_PHS_DIR_DECREMENT (0UL) /*!< EPWM counter count decrement \hideinitializer */ 170 #define EPWM_PHS_DIR_INCREMENT (1UL) /*!< EPWM counter count increment \hideinitializer */ 171 172 /*---------------------------------------------------------------------------------------------------------*/ 173 /* Noise Filter Clock Divide Select Constant Definitions */ 174 /*---------------------------------------------------------------------------------------------------------*/ 175 #define EPWM_NF_CLK_DIV_1 (0UL) /*!< Noise filter clock is HCLK divide by 1 \hideinitializer */ 176 #define EPWM_NF_CLK_DIV_2 (1UL) /*!< Noise filter clock is HCLK divide by 2 \hideinitializer */ 177 #define EPWM_NF_CLK_DIV_4 (2UL) /*!< Noise filter clock is HCLK divide by 4 \hideinitializer */ 178 #define EPWM_NF_CLK_DIV_8 (3UL) /*!< Noise filter clock is HCLK divide by 8 \hideinitializer */ 179 #define EPWM_NF_CLK_DIV_16 (4UL) /*!< Noise filter clock is HCLK divide by 16 \hideinitializer */ 180 #define EPWM_NF_CLK_DIV_32 (5UL) /*!< Noise filter clock is HCLK divide by 32 \hideinitializer */ 181 #define EPWM_NF_CLK_DIV_64 (6UL) /*!< Noise filter clock is HCLK divide by 64 \hideinitializer */ 182 #define EPWM_NF_CLK_DIV_128 (7UL) /*!< Noise filter clock is HCLK divide by 128 \hideinitializer */ 183 184 /*---------------------------------------------------------------------------------------------------------*/ 185 /* Clock Source Select Constant Definitions */ 186 /*---------------------------------------------------------------------------------------------------------*/ 187 #define EPWM_CLKSRC_EPWM_CLK (0UL) /*!< EPWM Clock source selects to EPWM0_CLK or EPWM1_CLK \hideinitializer */ 188 #define EPWM_CLKSRC_TIMER0 (1UL) /*!< EPWM Clock source selects to TIMER0 overflow \hideinitializer */ 189 #define EPWM_CLKSRC_TIMER1 (2UL) /*!< EPWM Clock source selects to TIMER1 overflow \hideinitializer */ 190 #define EPWM_CLKSRC_TIMER2 (3UL) /*!< EPWM Clock source selects to TIMER2 overflow \hideinitializer */ 191 #define EPWM_CLKSRC_TIMER3 (4UL) /*!< EPWM Clock source selects to TIMER3 overflow \hideinitializer */ 192 193 /*---------------------------------------------------------------------------------------------------------*/ 194 /* Fault Detect Clock Source Select Constant Definitions */ 195 /*---------------------------------------------------------------------------------------------------------*/ 196 #define EPWM_FDCTL_FDCKSEL_CLK_DIV_1 (0UL << EPWM_FDCTL0_FDCKSEL_Pos) /*!< Fault detect clock selects to fault detect clock divided by 1 \hideinitializer */ 197 #define EPWM_FDCTL_FDCKSEL_CLK_DIV_2 (1UL << EPWM_FDCTL0_FDCKSEL_Pos) /*!< Fault detect clock selects to fault detect clock divided by 2 \hideinitializer */ 198 #define EPWM_FDCTL_FDCKSEL_CLK_DIV_4 (2UL << EPWM_FDCTL0_FDCKSEL_Pos) /*!< Fault detect clock selects to fault detect clock divided by 4 \hideinitializer */ 199 #define EPWM_FDCTL_FDCKSEL_CLK_DIV_8 (3UL << EPWM_FDCTL0_FDCKSEL_Pos) /*!< Fault detect clock selects to fault detect clock divided by 8 \hideinitializer */ 200 201 202 203 /**@}*/ /* end of group EPWM_EXPORTED_CONSTANTS */ 204 205 206 /** @addtogroup EPWM_EXPORTED_FUNCTIONS EPWM Exported Functions 207 @{ 208 */ 209 210 /** 211 * @brief This macro enable complementary mode 212 * @param[in] epwm The pointer of the specified EPWM module 213 * @return None 214 * @details This macro is used to enable complementary mode of EPWM module. 215 * \hideinitializer 216 */ 217 #define EPWM_ENABLE_COMPLEMENTARY_MODE(epwm) ((epwm)->CTL1 = (epwm)->CTL1 | (0x7ul<<EPWM_CTL1_OUTMODE0_Pos)) 218 219 /** 220 * @brief This macro disable complementary mode, and enable independent mode. 221 * @param[in] epwm The pointer of the specified EPWM module 222 * @return None 223 * @details This macro is used to disable complementary mode of EPWM module. 224 * \hideinitializer 225 */ 226 #define EPWM_DISABLE_COMPLEMENTARY_MODE(epwm) ((epwm)->CTL1 = (epwm)->CTL1 & ~(0x7ul<<EPWM_CTL1_OUTMODE0_Pos)) 227 228 /** 229 * @brief This macro enable group mode 230 * @param[in] epwm The pointer of the specified EPWM module 231 * @return None 232 * @details This macro is used to enable group mode of EPWM module. 233 * \hideinitializer 234 */ 235 #define EPWM_ENABLE_GROUP_MODE(epwm) ((epwm)->CTL0 = (epwm)->CTL0 | EPWM_CTL0_GROUPEN_Msk) 236 237 /** 238 * @brief This macro disable group mode 239 * @param[in] epwm The pointer of the specified EPWM module 240 * @return None 241 * @details This macro is used to disable group mode of EPWM module. 242 * \hideinitializer 243 */ 244 #define EPWM_DISABLE_GROUP_MODE(epwm) ((epwm)->CTL0 = (epwm)->CTL0 & ~EPWM_CTL0_GROUPEN_Msk) 245 246 /** 247 * @brief Enable timer synchronous start counting function of specified channel(s) 248 * @param[in] epwm The pointer of the specified EPWM module 249 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 250 * Bit 0 represents channel 0, bit 1 represents channel 1... 251 * @param[in] u32SyncSrc Synchronous start source selection, valid values are: 252 * - \ref EPWM_SSCTL_SSRC_EPWM0 253 * - \ref EPWM_SSCTL_SSRC_EPWM1 254 * - \ref EPWM_SSCTL_SSRC_BPWM0 255 * - \ref EPWM_SSCTL_SSRC_BPWM1 256 * @return None 257 * @details This macro is used to enable timer synchronous start counting function of specified channel(s). 258 * \hideinitializer 259 */ 260 #define EPWM_ENABLE_TIMER_SYNC(epwm, u32ChannelMask, u32SyncSrc) ((epwm)->SSCTL = ((epwm)->SSCTL & ~EPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | (u32ChannelMask)) 261 262 /** 263 * @brief Disable timer synchronous start counting function of specified channel(s) 264 * @param[in] epwm The pointer of the specified EPWM module 265 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 266 * Bit 0 represents channel 0, bit 1 represents channel 1... 267 * @return None 268 * @details This macro is used to disable timer synchronous start counting function of specified channel(s). 269 * \hideinitializer 270 */ 271 #define EPWM_DISABLE_TIMER_SYNC(epwm, u32ChannelMask) \ 272 do{ \ 273 int i;\ 274 for(i = 0; i < 6; i++) { \ 275 if((u32ChannelMask) & (1UL << i)) \ 276 { \ 277 (epwm)->SSCTL &= ~(1UL << i); \ 278 } \ 279 } \ 280 }while(0) 281 282 /** 283 * @brief This macro enable EPWM counter synchronous start counting function. 284 * @param[in] epwm The pointer of the specified EPWM module 285 * @return None 286 * @details This macro is used to make selected EPWM0 and EPWM1 channel(s) start counting at the same time. 287 * To configure synchronous start counting channel(s) by EPWM_ENABLE_TIMER_SYNC() and EPWM_DISABLE_TIMER_SYNC(). 288 * \hideinitializer 289 */ 290 #define EPWM_TRIGGER_SYNC_START(epwm) ((epwm)->SSTRG = EPWM_SSTRG_CNTSEN_Msk) 291 292 /** 293 * @brief This macro enable output inverter of specified channel(s) 294 * @param[in] epwm The pointer of the specified EPWM module 295 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 296 * Bit 0 represents channel 0, bit 1 represents channel 1... 297 * @return None 298 * @details This macro is used to enable output inverter of specified channel(s). 299 * \hideinitializer 300 */ 301 #define EPWM_ENABLE_OUTPUT_INVERTER(epwm, u32ChannelMask) ((epwm)->POLCTL = (u32ChannelMask)) 302 303 /** 304 * @brief This macro get captured rising data 305 * @param[in] epwm The pointer of the specified EPWM module 306 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 307 * @return None 308 * @details This macro is used to get captured rising data of specified channel. 309 * \hideinitializer 310 */ 311 #define EPWM_GET_CAPTURE_RISING_DATA(epwm, u32ChannelNum) ((epwm)->CAPDAT[(u32ChannelNum)].RCAPDAT) 312 313 /** 314 * @brief This macro get captured falling data 315 * @param[in] epwm The pointer of the specified EPWM module 316 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 317 * @return None 318 * @details This macro is used to get captured falling data of specified channel. 319 * \hideinitializer 320 */ 321 #define EPWM_GET_CAPTURE_FALLING_DATA(epwm, u32ChannelNum) ((epwm)->CAPDAT[(u32ChannelNum)].FCAPDAT) 322 323 /** 324 * @brief This macro mask output logic to high or low 325 * @param[in] epwm The pointer of the specified EPWM module 326 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 327 * Bit 0 represents channel 0, bit 1 represents channel 1... 328 * @param[in] u32LevelMask Output logic to high or low 329 * @return None 330 * @details This macro is used to mask output logic to high or low of specified channel(s). 331 * @note If u32ChannelMask parameter is 0, then mask function will be disabled. 332 * \hideinitializer 333 */ 334 #define EPWM_MASK_OUTPUT(epwm, u32ChannelMask, u32LevelMask) \ 335 do{ \ 336 (epwm)->MSKEN = (u32ChannelMask); \ 337 (epwm)->MSK = (u32LevelMask); \ 338 }while(0) 339 340 /** 341 * @brief This macro set the prescaler of the selected channel 342 * @param[in] epwm The pointer of the specified EPWM module 343 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 344 * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF 345 * @return None 346 * @details This macro is used to set the prescaler of specified channel. 347 * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected. 348 * The clock of EPWM counter is divided by (u32Prescaler + 1). 349 * \hideinitializer 350 */ 351 #define EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescaler) ((epwm)->CLKPSC[(u32ChannelNum) >> 1] = (u32Prescaler)) 352 353 /** 354 * @brief This macro get the prescaler of the selected channel 355 * @param[in] epwm The pointer of the specified EPWM module 356 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 357 * @return Return Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF 358 * @details This macro is used to get the prescaler of specified channel. 359 * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected. 360 * The clock of EPWM counter is divided by (u32Prescaler + 1). 361 * \hideinitializer 362 */ 363 #define EPWM_GET_PRESCALER(epwm, u32ChannelNum) ((epwm)->CLKPSC[(u32ChannelNum) >> 1U]) 364 365 /** 366 * @brief This macro set the comparator of the selected channel 367 * @param[in] epwm The pointer of the specified EPWM module 368 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 369 * @param[in] u32CMR Comparator of specified channel. Valid values are between 0~0xFFFF 370 * @return None 371 * @details This macro is used to set the comparator of specified channel. 372 * @note This new setting will take effect on next EPWM period. 373 * \hideinitializer 374 */ 375 #define EPWM_SET_CMR(epwm, u32ChannelNum, u32CMR) ((epwm)->CMPDAT[(u32ChannelNum)]= (u32CMR)) 376 377 /** 378 * @brief This macro get the comparator of the selected channel 379 * @param[in] epwm The pointer of the specified EPWM module 380 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 381 * @return Return the comparator of specified channel. Valid values are between 0~0xFFFF 382 * @details This macro is used to get the comparator of specified channel. 383 * \hideinitializer 384 */ 385 #define EPWM_GET_CMR(epwm, u32ChannelNum) ((epwm)->CMPDAT[(u32ChannelNum)]) 386 387 /** 388 * @brief This macro set the free trigger comparator of the selected channel 389 * @param[in] epwm The pointer of the specified EPWM module 390 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 391 * @param[in] u32FTCMR Free trigger comparator of specified channel. Valid values are between 0~0xFFFF 392 * @return None 393 * @details This macro is used to set the free trigger comparator of specified channel. 394 * @note This new setting will take effect on next EPWM period. 395 * \hideinitializer 396 */ 397 #define EPWM_SET_FTCMR(epwm, u32ChannelNum, u32FTCMR) (((epwm)->FTCMPDAT[((u32ChannelNum) >> 1U)]) = (u32FTCMR)) 398 399 /** 400 * @brief This macro set the period of the selected channel 401 * @param[in] epwm The pointer of the specified EPWM module 402 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 403 * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF 404 * @return None 405 * @details This macro is used to set the period of specified channel. 406 * @note This new setting will take effect on next EPWM period. 407 * @note EPWM counter will stop if period length set to 0. 408 * \hideinitializer 409 */ 410 #define EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR) ((epwm)->PERIOD[(u32ChannelNum)] = (u32CNR)) 411 412 /** 413 * @brief This macro get the period of the selected channel 414 * @param[in] epwm The pointer of the specified EPWM module 415 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 416 * @return Return the period of specified channel. Valid values are between 0~0xFFFF 417 * @details This macro is used to get the period of specified channel. 418 * \hideinitializer 419 */ 420 #define EPWM_GET_CNR(epwm, u32ChannelNum) ((epwm)->PERIOD[(u32ChannelNum)]) 421 422 /** 423 * @brief This macro set the EPWM aligned type 424 * @param[in] epwm The pointer of the specified EPWM module 425 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 426 * Bit 0 represents channel 0, bit 1 represents channel 1... 427 * @param[in] u32AlignedType EPWM aligned type, valid values are: 428 * - \ref EPWM_EDGE_ALIGNED 429 * - \ref EPWM_CENTER_ALIGNED 430 * @return None 431 * @details This macro is used to set the EPWM aligned type of specified channel(s). 432 * \hideinitializer 433 */ 434 #define EPWM_SET_ALIGNED_TYPE(epwm, u32ChannelMask, u32AlignedType) \ 435 do{ \ 436 uint32_t i; \ 437 for(i = 0UL; i < 6UL; i++) { \ 438 if((u32ChannelMask) & (1UL << i)) \ 439 { \ 440 (epwm)->CTL1 = (((epwm)->CTL1 & ~(3UL << (i << 1))) | ((u32AlignedType) << (i << 1))); \ 441 } \ 442 } \ 443 }while(0) 444 445 /** 446 * @brief Set load window of window loading mode for specified channel(s) 447 * @param[in] epwm The pointer of the specified EPWM module 448 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 449 * Bit 0 represents channel 0, bit 1 represents channel 1... 450 * @return None 451 * @details This macro is used to set load window of window loading mode for specified channel(s). 452 * \hideinitializer 453 */ 454 #define EPWM_SET_LOAD_WINDOW(epwm, u32ChannelMask) ((epwm)->LOAD |= (u32ChannelMask)) 455 456 /** 457 * @brief Trigger synchronous event from specified channel(s) 458 * @param[in] epwm The pointer of the specified EPWM module 459 * @param[in] u32ChannelNum EPWM channel number. Valid values are 0, 2, 4 460 * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4 461 * @return None 462 * @details This macro is used to trigger synchronous event from specified channel(s). 463 * \hideinitializer 464 */ 465 #define EPWM_TRIGGER_SYNC(epwm, u32ChannelNum) ((epwm)->SWSYNC |= (1U << ((u32ChannelNum) >> 1))) 466 467 /** 468 * @brief Clear counter of specified channel(s) 469 * @param[in] epwm The pointer of the specified EPWM module 470 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 471 * Bit 0 represents channel 0, bit 1 represents channel 1... 472 * @return None 473 * @details This macro is used to clear counter of specified channel(s). 474 * \hideinitializer 475 */ 476 #define EPWM_CLR_COUNTER(epwm, u32ChannelMask) ((epwm)->CNTCLR |= (u32ChannelMask)) 477 478 /** 479 * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s) 480 * @param[in] epwm The pointer of the specified EPWM module 481 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 482 * Bit 0 represents channel 0, bit 1 represents channel 1... 483 * @param[in] u32ZeroLevel output level at zero point, valid values are: 484 * - \ref EPWM_OUTPUT_NOTHING 485 * - \ref EPWM_OUTPUT_LOW 486 * - \ref EPWM_OUTPUT_HIGH 487 * - \ref EPWM_OUTPUT_TOGGLE 488 * @param[in] u32CmpUpLevel output level at compare up point, valid values are: 489 * - \ref EPWM_OUTPUT_NOTHING 490 * - \ref EPWM_OUTPUT_LOW 491 * - \ref EPWM_OUTPUT_HIGH 492 * - \ref EPWM_OUTPUT_TOGGLE 493 * @param[in] u32PeriodLevel output level at period(center) point, valid values are: 494 * - \ref EPWM_OUTPUT_NOTHING 495 * - \ref EPWM_OUTPUT_LOW 496 * - \ref EPWM_OUTPUT_HIGH 497 * - \ref EPWM_OUTPUT_TOGGLE 498 * @param[in] u32CmpDownLevel output level at compare down point, valid values are: 499 * - \ref EPWM_OUTPUT_NOTHING 500 * - \ref EPWM_OUTPUT_LOW 501 * - \ref EPWM_OUTPUT_HIGH 502 * - \ref EPWM_OUTPUT_TOGGLE 503 * @return None 504 * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s). 505 * \hideinitializer 506 */ 507 #define EPWM_SET_OUTPUT_LEVEL(epwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \ 508 do{ \ 509 uint32_t i; \ 510 for(i = 0UL; i < 6UL; i++) { \ 511 if((u32ChannelMask) & (1UL << i)) { \ 512 (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (i << 1))) | ((u32ZeroLevel) << (i << 1))); \ 513 (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))) | ((u32PeriodLevel) << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))); \ 514 (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (i << 1))) | ((u32CmpUpLevel) << (i << 1))); \ 515 (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))) | ((u32CmpDownLevel) << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))); \ 516 } \ 517 } \ 518 }while(0) 519 520 /** 521 * @brief Trigger brake event from specified channel(s) 522 * @param[in] epwm The pointer of the specified EPWM module 523 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 524 * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4 525 * @param[in] u32BrakeType Type of brake trigger. 526 * - \ref EPWM_FB_EDGE 527 * - \ref EPWM_FB_LEVEL 528 * @return None 529 * @details This macro is used to trigger brake event from specified channel(s). 530 * \hideinitializer 531 */ 532 #define EPWM_TRIGGER_BRAKE(epwm, u32ChannelMask, u32BrakeType) ((epwm)->SWBRK |= ((u32ChannelMask) << (u32BrakeType))) 533 534 /** 535 * @brief Set Dead zone clock source 536 * @param[in] epwm The pointer of the specified EPWM module 537 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 538 * @param[in] u32AfterPrescaler Dead zone clock source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler). 539 * @return None 540 * @details This macro is used to set Dead zone clock source. Every two channels share the same setting. 541 * @note The write-protection function should be disabled before using this function. 542 * \hideinitializer 543 */ 544 #define EPWM_SET_DEADZONE_CLK_SRC(epwm, u32ChannelNum, u32AfterPrescaler) \ 545 (((epwm)->DTCTL[(u32ChannelNum) >> 1]) = ((epwm)->DTCTL[(u32ChannelNum) >> 1] & ~EPWM_DTCTL0_1_DTCKSEL_Msk) | \ 546 ((u32AfterPrescaler) << EPWM_DTCTL0_1_DTCKSEL_Pos)) 547 548 /*---------------------------------------------------------------------------------------------------------*/ 549 /* Define EPWM functions prototype */ 550 /*---------------------------------------------------------------------------------------------------------*/ 551 uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge); 552 uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle); 553 void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask); 554 void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask); 555 void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask); 556 void EPWM_EnableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); 557 void EPWM_DisableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum); 558 int32_t EPWM_EnableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Prescale, uint32_t u32PrescaleCnt); 559 void EPWM_DisableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum); 560 void EPWM_ClearADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); 561 uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 562 void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); 563 void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum); 564 void EPWM_ClearDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); 565 uint32_t EPWM_GetDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 566 void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource); 567 void EPWM_EnableCapture(EPWM_T *epwm, uint32_t u32ChannelMask); 568 void EPWM_DisableCapture(EPWM_T *epwm, uint32_t u32ChannelMask); 569 void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask); 570 void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask); 571 void EPWM_EnablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode); 572 void EPWM_DisablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum); 573 void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration); 574 void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum); 575 void EPWM_EnableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); 576 void EPWM_DisableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); 577 void EPWM_ClearCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); 578 uint32_t EPWM_GetCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 579 void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType); 580 void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum); 581 void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 582 uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 583 void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource); 584 void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource); 585 void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource); 586 uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource); 587 void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType); 588 void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum); 589 void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 590 uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 591 void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum); 592 void EPWM_DisableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum); 593 void EPWM_ClearZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 594 uint32_t EPWM_GetZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 595 void EPWM_EnableAcc(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc); 596 void EPWM_DisableAcc(EPWM_T *epwm, uint32_t u32ChannelNum); 597 void EPWM_EnableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); 598 void EPWM_DisableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); 599 void EPWM_ClearAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); 600 uint32_t EPWM_GetAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); 601 void EPWM_EnableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum); 602 void EPWM_DisableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum); 603 void EPWM_EnableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum); 604 void EPWM_DisableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum); 605 void EPWM_ClearFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 606 uint32_t EPWM_GetFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 607 void EPWM_EnableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); 608 void EPWM_DisableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); 609 void EPWM_ConfigSyncPhase(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase); 610 void EPWM_EnableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask); 611 void EPWM_DisableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask); 612 void EPWM_EnableSyncNoiseFilter(EPWM_T *epwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel); 613 void EPWM_DisableSyncNoiseFilter(EPWM_T *epwm); 614 void EPWM_EnableSyncPinInverse(EPWM_T *epwm); 615 void EPWM_DisableSyncPinInverse(EPWM_T *epwm); 616 void EPWM_SetClockSource(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel); 617 void EPWM_EnableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel); 618 void EPWM_DisableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum); 619 void EPWM_EnableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum); 620 void EPWM_DisableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum); 621 void EPWM_SetBrakePinSource(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule); 622 void EPWM_SetLeadingEdgeBlanking(EPWM_T *epwm, uint32_t u32TrigSrcSel, uint32_t u32TrigType, uint32_t u32BlankingCnt, uint32_t u32BlankingEnable); 623 uint32_t EPWM_GetWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 624 void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 625 void EPWM_EnableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32AfterPrescaler, uint32_t u32ClkSel); 626 void EPWM_DisableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum); 627 void EPWM_EnableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum); 628 void EPWM_DisableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum); 629 void EPWM_EnableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32DeglitchSmpCycle); 630 void EPWM_DisableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum); 631 void EPWM_EnableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32MaskCnt); 632 void EPWM_DisableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum); 633 void EPWM_EnableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); 634 void EPWM_DisableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); 635 void EPWM_ClearFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); 636 uint32_t EPWM_GetFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); 637 638 639 /**@}*/ /* end of group EPWM_EXPORTED_FUNCTIONS */ 640 641 /**@}*/ /* end of group EPWM_Driver */ 642 643 /**@}*/ /* end of group Standard_Driver */ 644 645 #ifdef __cplusplus 646 } 647 #endif 648 649 #endif /* __EPWM_H__ */ 650
