1 /****************************************************************************** 2 * @file eadc.h 3 * @version V0.10 4 * @brief M2354 series EADC driver header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __EADC_H__ 10 #define __EADC_H__ 11 12 #ifdef __cplusplus 13 extern "C" 14 { 15 #endif 16 17 18 /** @addtogroup Standard_Driver Standard Driver 19 @{ 20 */ 21 22 /** @addtogroup EADC_Driver EADC Driver 23 @{ 24 */ 25 26 /** @addtogroup EADC_EXPORTED_CONSTANTS EADC Exported Constants 27 @{ 28 */ 29 30 /*---------------------------------------------------------------------------------------------------------*/ 31 /* EADC_CTL Constant Definitions */ 32 /*---------------------------------------------------------------------------------------------------------*/ 33 #define EADC_CTL_DIFFEN_SINGLE_END (0UL<<EADC_CTL_DIFFEN_Pos) /*!< Single-end input mode */ 34 #define EADC_CTL_DIFFEN_DIFFERENTIAL (1UL<<EADC_CTL_DIFFEN_Pos) /*!< Differential input mode */ 35 36 #define EADC_CTL_DMOF_STRAIGHT_BINARY (0UL<<EADC_CTL_DMOF_Pos) /*!< Select the straight binary format as the output format of the conversion result */ 37 #define EADC_CTL_DMOF_TWOS_COMPLEMENT (1UL<<EADC_CTL_DMOF_Pos) /*!< Select the 2's complement format as the output format of the conversion result */ 38 39 40 /*---------------------------------------------------------------------------------------------------------*/ 41 /* EADC_SCTL Constant Definitions */ 42 /*---------------------------------------------------------------------------------------------------------*/ 43 #define EADC_SCTL_CHSEL(x) ((x) << EADC_SCTL_CHSEL_Pos) /*!< A/D sample module channel selection */ 44 #define EADC_SCTL_TRGDLYDIV(x) ((x) << EADC_SCTL_TRGDLYDIV_Pos) /*!< A/D sample module start of conversion trigger delay clock divider selection */ 45 #define EADC_SCTL_TRGDLYCNT(x) ((x) << EADC_SCTL_TRGDLYCNT_Pos) /*!< A/D sample module start of conversion trigger delay time */ 46 47 #define EADC_SOFTWARE_TRIGGER (0UL<<EADC_SCTL_TRGSEL_Pos) /*!< Software trigger */ 48 #define EADC_FALLING_EDGE_TRIGGER (EADC_SCTL_EXTFEN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin falling edge trigger */ 49 #define EADC_RISING_EDGE_TRIGGER (EADC_SCTL_EXTREN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin rising edge trigger */ 50 #define EADC_FALLING_RISING_EDGE_TRIGGER (EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin both falling and rising edge trigger */ 51 #define EADC_ADINT0_TRIGGER (2UL<<EADC_SCTL_TRGSEL_Pos) /*!< ADC ADINT0 interrupt EOC pulse trigger */ 52 #define EADC_ADINT1_TRIGGER (3UL<<EADC_SCTL_TRGSEL_Pos) /*!< ADC ADINT1 interrupt EOC pulse trigger */ 53 #define EADC_TIMER0_TRIGGER (4UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer0 overflow pulse trigger */ 54 #define EADC_TIMER1_TRIGGER (5UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer1 overflow pulse trigger */ 55 #define EADC_TIMER2_TRIGGER (6UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer2 overflow pulse trigger */ 56 #define EADC_TIMER3_TRIGGER (7UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer3 overflow pulse trigger */ 57 #define EADC_TIMER4_TRIGGER (8UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer4 overflow pulse trigger */ 58 #define EADC_TIMER5_TRIGGER (9UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer5 overflow pulse trigger */ 59 #define EADC_PWM0TG0_TRIGGER (0xAUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG0 trigger */ 60 #define EADC_PWM0TG1_TRIGGER (0xBUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG1 trigger */ 61 #define EADC_PWM0TG2_TRIGGER (0xCUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG2 trigger */ 62 #define EADC_PWM0TG3_TRIGGER (0xDUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG3 trigger */ 63 #define EADC_PWM0TG4_TRIGGER (0xEUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG4 trigger */ 64 #define EADC_PWM0TG5_TRIGGER (0xFUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG5 trigger */ 65 #define EADC_PWM1TG0_TRIGGER (0x10UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG0 trigger */ 66 #define EADC_PWM1TG1_TRIGGER (0x11UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG1 trigger */ 67 #define EADC_PWM1TG2_TRIGGER (0x12UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG2 trigger */ 68 #define EADC_PWM1TG3_TRIGGER (0x13UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG3 trigger */ 69 #define EADC_PWM1TG4_TRIGGER (0x14UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG4 trigger */ 70 #define EADC_PWM1TG5_TRIGGER (0x15UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG5 trigger */ 71 #define EADC_BPWM0TG_TRIGGER (0x16UL<<EADC_SCTL_TRGSEL_Pos) /*!< BPWM0TG trigger */ 72 #define EADC_BPWM1TG_TRIGGER (0x17UL<<EADC_SCTL_TRGSEL_Pos) /*!< BPWM1TG trigger */ 73 74 #define EADC_SCTL_TRGDLYDIV_DIVIDER_1 (0UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/1 */ 75 #define EADC_SCTL_TRGDLYDIV_DIVIDER_2 (0x1UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/2 */ 76 #define EADC_SCTL_TRGDLYDIV_DIVIDER_4 (0x2UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/4 */ 77 #define EADC_SCTL_TRGDLYDIV_DIVIDER_16 (0x3UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/16 */ 78 79 80 /*---------------------------------------------------------------------------------------------------------*/ 81 /* EADC_CMP Constant Definitions */ 82 /*---------------------------------------------------------------------------------------------------------*/ 83 #define EADC_CMP_CMPCOND_LESS_THAN (0UL<<EADC_CMP_CMPCOND_Pos) /*!< The compare condition is "less than" */ 84 #define EADC_CMP_CMPCOND_GREATER_OR_EQUAL (1UL<<EADC_CMP_CMPCOND_Pos) /*!< The compare condition is "greater than or equal to" */ 85 #define EADC_CMP_CMPWEN_ENABLE (EADC_CMP_CMPWEN_Msk) /*!< Compare window mode enable */ 86 #define EADC_CMP_CMPWEN_DISABLE (~EADC_CMP_CMPWEN_Msk) /*!< Compare window mode disable */ 87 #define EADC_CMP_ADCMPIE_ENABLE (EADC_CMP_ADCMPIE_Msk) /*!< A/D result compare interrupt enable */ 88 #define EADC_CMP_ADCMPIE_DISABLE (~EADC_CMP_ADCMPIE_Msk) /*!< A/D result compare interrupt disable */ 89 90 /**@}*/ /* end of group EADC_EXPORTED_CONSTANTS */ 91 92 /** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions 93 @{ 94 */ 95 /*---------------------------------------------------------------------------------------------------------*/ 96 /* EADC Macro Definitions */ 97 /*---------------------------------------------------------------------------------------------------------*/ 98 99 /** 100 * @brief A/D Converter Control Circuits Reset. 101 * @param[in] eadc The pointer of the specified EADC module. 102 * @return None 103 * @details ADCRST bit (EADC_CT[1]) remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0. 104 */ 105 #define EADC_CONV_RESET(eadc) ((eadc)->CTL |= EADC_CTL_ADCRST_Msk) 106 107 /** 108 * @brief Enable Sample Module PDMA transfer. 109 * @param[in] eadc The pointer of the specified EADC module. 110 * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. 111 * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF. 112 * @return None 113 * @details When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, 114 * user can enable this bit to generate a PDMA data transfer request. 115 * \hideinitializer 116 */ 117 #define EADC_ENABLE_SAMPLE_MODULE_PDMA(eadc, u32ModuleMask) ((eadc)->PDMACTL |= u32ModuleMask) 118 119 /** 120 * @brief Disable Sample Module PDMA transfer. 121 * @param[in] eadc The pointer of the specified EADC module. 122 * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. 123 * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF. 124 * @return None 125 * @details This macro is used to disable sample module PDMA transfer. 126 * \hideinitializer 127 */ 128 #define EADC_DISABLE_SAMPLE_MODULE_PDMA(eadc, u32ModuleMask) ((eadc)->PDMACTL &= (~u32ModuleMask)) 129 130 /** 131 * @brief Enable double buffer mode. 132 * @param[in] eadc The pointer of the specified EADC module. 133 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3. 134 * @return None 135 * @details The ADC controller supports a double buffer mode in sample module 0~3. 136 * If user enable DBMEN (EADC_SCTLn[23], n=0~3), the double buffer mode will enable. 137 */ 138 #define EADC_ENABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_DBMEN_Msk) 139 140 /** 141 * @brief Disable double buffer mode. 142 * @param[in] eadc The pointer of the specified EADC module. 143 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3. 144 * @return None 145 * @details Sample has one sample result register. 146 */ 147 #define EADC_DISABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_DBMEN_Msk) 148 149 /** 150 * @brief Set ADIFn at A/D end of conversion. 151 * @param[in] eadc The pointer of the specified EADC module. 152 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. 153 * @return None 154 * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the start of conversion. 155 */ 156 #define EADC_ENABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_INTPOS_Msk) 157 158 /** 159 * @brief Set ADIFn at A/D start of conversion. 160 * @param[in] eadc The pointer of the specified EADC module. 161 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. 162 * @return None 163 * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the end of conversion. 164 */ 165 #define EADC_DISABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_INTPOS_Msk) 166 167 /** 168 * @brief Enable the interrupt. 169 * @param[in] eadc The pointer of the specified EADC module. 170 * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status. 171 * This parameter decides which interrupts will be enabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3. 172 * @return None 173 * @details The A/D converter generates a conversion end ADIFn (EADC_STATUS2[n]) upon the end of specific sample module A/D conversion. 174 * If ADCIENn bit (EADC_CTL[n+2]) is set then conversion end interrupt request ADINTn is generated (n=0~3). 175 */ 176 #define EADC_ENABLE_INT(eadc, u32Mask) ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos)) 177 178 /** 179 * @brief Disable the interrupt. 180 * @param[in] eadc The pointer of the specified EADC module. 181 * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status. 182 * This parameter decides which interrupts will be disabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3. 183 * @return None 184 * @details Specific sample module A/D ADINT0 interrupt function Disabled. 185 */ 186 #define EADC_DISABLE_INT(eadc, u32Mask) ((eadc)->CTL &= ~((u32Mask) << EADC_CTL_ADCIEN0_Pos)) 187 188 /** 189 * @brief Enable the sample module interrupt. 190 * @param[in] eadc The pointer of the specified EADC module. 191 * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3. 192 * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. 193 * This parameter decides which sample module interrupts will be enabled, valid range are between 1~0x7FFFF. 194 * @return None 195 * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address. 196 */ 197 #define EADC_ENABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] |= (u32ModuleMask)) 198 199 /** 200 * @brief Disable the sample module interrupt. 201 * @param[in] eadc The pointer of the specified EADC module. 202 * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3. 203 * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. 204 * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF. 205 * @return None 206 * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address. 207 */ 208 #define EADC_DISABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] &= (uint32_t)(~(u32ModuleMask))) 209 210 /** 211 * @brief Set the input mode output format. 212 * @param[in] eadc The pointer of the specified EADC module. 213 * @param[in] u32Format Decides the output format. Valid values are: 214 * - \ref EADC_CTL_DMOF_STRAIGHT_BINARY :Select the straight binary format as the output format of the conversion result. 215 * - \ref EADC_CTL_DMOF_TWOS_COMPLEMENT :Select the 2's complement format as the output format of the conversion result. 216 * @return None 217 * @details The macro is used to set A/D input mode output format. 218 */ 219 #define EADC_SET_DMOF(eadc, u32Format) ((eadc)->CTL = ((eadc)->CTL & ~EADC_CTL_DMOF_Msk) | (u32Format)) 220 221 /** 222 * @brief Start the A/D conversion. 223 * @param[in] eadc The pointer of the specified EADC module. 224 * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module. 225 * This parameter decides which sample module will be conversion, valid range are between 1~0x7FFFF. 226 * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module 18. 227 * @return None 228 * @details After write EADC_SWTRG register to start ADC conversion, the EADC_PENDSTS register will show which SAMPLE will conversion. 229 */ 230 #define EADC_START_CONV(eadc, u32ModuleMask) ((eadc)->SWTRG = (u32ModuleMask)) 231 232 /** 233 * @brief Cancel the conversion for sample module. 234 * @param[in] eadc The pointer of the specified EADC module. 235 * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module. 236 * This parameter decides which sample module will stop the conversion, valid range are between 1~0x7FFFF. 237 * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module18. 238 * @return None 239 * @details If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it. 240 */ 241 #define EADC_STOP_CONV(eadc, u32ModuleMask) ((eadc)->PENDSTS = (u32ModuleMask)) 242 243 /** 244 * @brief Get the conversion pending flag. 245 * @param[in] eadc The pointer of the specified EADC module. 246 * @return Return the conversion pending sample module. 247 * @details This STPFn(EADC_PENDSTS[18:0]) bit remains 1 during pending state, when the respective ADC conversion is end, 248 * the STPFn (n=0~18) bit is automatically cleared to 0. 249 */ 250 #define EADC_GET_PENDING_CONV(eadc) ((eadc)->PENDSTS) 251 252 /** 253 * @brief Get the conversion data of the user-specified sample module. 254 * @param[in] eadc The pointer of the specified EADC module. 255 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18. 256 * @return Return the conversion data of the user-specified sample module. 257 * @details This macro is used to read RESULT bit (EADC_DATn[15:0], n=0~18) field to get conversion data. 258 */ 259 #define EADC_GET_CONV_DATA(eadc, u32ModuleNum) ((eadc)->DAT[(u32ModuleNum)] & EADC_DAT_RESULT_Msk) 260 261 /** 262 * @brief Get the data overrun flag of the user-specified sample module. 263 * @param[in] eadc The pointer of the specified EADC module. 264 * @param[in] u32ModuleMask The combination of data overrun status bits. Each bit corresponds to a data overrun status, valid range are between 1~0x7FFFF. 265 * @return Return the data overrun flag of the user-specified sample module. 266 * @details This macro is used to read OV bit (EADC_STATUS0[31:16], EADC_STATUS1[18:16]) field to get data overrun status. 267 */ 268 #define EADC_GET_DATA_OVERRUN_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) | ((eadc)->STATUS1 & EADC_STATUS1_OV_Msk)) & (u32ModuleMask)) 269 270 /** 271 * @brief Get the data valid flag of the user-specified sample module. 272 * @param[in] eadc The pointer of the specified EADC module. 273 * @param[in] u32ModuleMask The combination of data valid status bits. Each bit corresponds to a data valid status, valid range are between 1~0x7FFFF. 274 * @return Return the data valid flag of the user-specified sample module. 275 * @details This macro is used to read VALID bit (EADC_STATUS0[15:0], EADC_STATUS1[2:0]) field to get data valid status. 276 */ 277 #define EADC_GET_DATA_VALID_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) | (((eadc)->STATUS1 & EADC_STATUS1_VALID_Msk) << 16)) & (u32ModuleMask)) 278 279 /** 280 * @brief Get the double data of the user-specified sample module. 281 * @param[in] eadc The pointer of the specified EADC module. 282 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18. 283 * @return Return the double data of the user-specified sample module. 284 * @details This macro is used to read RESULT bit (EADC_DDATn[15:0], n=0~3) field to get conversion data. 285 */ 286 #define EADC_GET_DOUBLE_DATA(eadc, u32ModuleNum) ((eadc)->DDAT[(u32ModuleNum)] & EADC_DDAT0_RESULT_Msk) 287 288 /** 289 * @brief Get the user-specified interrupt flags. 290 * @param[in] eadc The pointer of the specified EADC module. 291 * @param[in] u32Mask The combination of interrupt status bits. Each bit corresponds to a interrupt status. 292 * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. 293 * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3. 294 * @return Return the user-specified interrupt flags. 295 * @details This macro is used to get the user-specified interrupt flags. 296 */ 297 #define EADC_GET_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 & (u32Mask)) 298 299 /** 300 * @brief Get the user-specified sample module overrun flags. 301 * @param[in] eadc The pointer of the specified EADC module. 302 * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status, valid range are between 1~0x7FFFF. 303 * @return Return the user-specified sample module overrun flags. 304 * @details This macro is used to get the user-specified sample module overrun flags. 305 */ 306 #define EADC_GET_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS & (u32ModuleMask)) 307 308 /** 309 * @brief Clear the selected interrupt status bits. 310 * @param[in] eadc The pointer of the specified EADC module. 311 * @param[in] u32Mask The combination of compare interrupt status bits. Each bit corresponds to a compare interrupt status. 312 * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. 313 * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3. 314 * @return None 315 * @details This macro is used to clear clear the selected interrupt status bits. 316 */ 317 #define EADC_CLR_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 = (u32Mask)) 318 319 /** 320 * @brief Clear the selected sample module overrun status bits. 321 * @param[in] eadc The pointer of the specified EADC module. 322 * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status. 323 * Bit 0 is SPOVF0, bit 1 is SPOVF1..., bit 18 is SPOVF18. 324 * @return None 325 * @details This macro is used to clear the selected sample module overrun status bits. 326 */ 327 #define EADC_CLR_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS = (u32ModuleMask)) 328 329 /** 330 * @brief Check all sample module A/D result data register overrun flags. 331 * @param[in] eadc The pointer of the specified EADC module. 332 * @retval 0 None of sample module data register overrun flag is set to 1. 333 * @retval 1 Any one of sample module data register overrun flag is set to 1. 334 * @details The AOV bit (EADC_STATUS2[27]) will keep 1 when any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. 335 */ 336 #define EADC_IS_DATA_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AOV_Msk) >> EADC_STATUS2_AOV_Pos) 337 338 /** 339 * @brief Check all sample module A/D result data register valid flags. 340 * @param[in] eadc The pointer of the specified EADC module. 341 * @retval 0 None of sample module data register valid flag is set to 1. 342 * @retval 1 Any one of sample module data register valid flag is set to 1. 343 * @details The AVALID bit (EADC_STATUS2[26]) will keep 1 when any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. 344 */ 345 #define EADC_IS_DATA_VALID(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AVALID_Msk) >> EADC_STATUS2_AVALID_Pos) 346 347 /** 348 * @brief Check all A/D sample module start of conversion overrun flags. 349 * @param[in] eadc The pointer of the specified EADC module. 350 * @retval 0 None of sample module event overrun flag is set to 1. 351 * @retval 1 Any one of sample module event overrun flag is set to 1. 352 * @details The STOVF bit (EADC_STATUS2[25]) will keep 1 when any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. 353 */ 354 #define EADC_IS_SAMPLE_MODULE_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_STOVF_Msk) >> EADC_STATUS2_STOVF_Pos) 355 356 /** 357 * @brief Check all A/D interrupt flag overrun bits. 358 * @param[in] eadc The pointer of the specified EADC module. 359 * @retval 0 None of ADINT interrupt flag is overwritten to 1. 360 * @retval 1 Any one of ADINT interrupt flag is overwritten to 1. 361 * @details The ADOVIF bit (EADC_STATUS2[24]) will keep 1 when any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1. 362 */ 363 #define EADC_IS_INT_FLAG_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_ADOVIF_Msk) >> EADC_STATUS2_ADOVIF_Pos) 364 365 /** 366 * @brief Get the busy state of EADC. 367 * @param[in] eadc The pointer of the specified EADC module. 368 * @retval 0 Idle state. 369 * @retval 1 Busy state. 370 * @details This macro is used to read BUSY bit (EADC_STATUS2[23]) to get busy state. 371 */ 372 #define EADC_IS_BUSY(eadc) (((eadc)->STATUS2 & EADC_STATUS2_BUSY_Msk) >> EADC_STATUS2_BUSY_Pos) 373 374 /** 375 * @brief Configure the comparator 0 and enable it. 376 * @param[in] eadc The pointer of the specified EADC module. 377 * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. 378 * @param[in] u32Condition specifies the compare condition. Valid values are: 379 * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" 380 * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value 381 * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. 382 * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. 383 * @return None 384 * @details For example, ADC_ENABLE_CMP0(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE); 385 * Means EADC will assert comparator 0 flag if sample module 5 conversion result is greater or 386 * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. 387 */ 388 #define EADC_ENABLE_CMP0(eadc,\ 389 u32ModuleNum,\ 390 u32Condition,\ 391 u16CMPData,\ 392 u32MatchCount) ((eadc)->CMP[0] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ 393 (u32Condition) |\ 394 ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ 395 (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\ 396 EADC_CMP_ADCMPEN_Msk)) 397 398 /** 399 * @brief Configure the comparator 1 and enable it. 400 * @param[in] eadc The pointer of the specified EADC module. 401 * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. 402 * @param[in] u32Condition specifies the compare condition. Valid values are: 403 * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" 404 * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value 405 * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. 406 * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. 407 * @return None 408 * @details For example, ADC_ENABLE_CMP1(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE); 409 * Means EADC will assert comparator 1 flag if sample module 5 conversion result is greater or 410 * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. 411 */ 412 #define EADC_ENABLE_CMP1(eadc,\ 413 u32ModuleNum,\ 414 u32Condition,\ 415 u16CMPData,\ 416 u32MatchCount) ((eadc)->CMP[1] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ 417 (u32Condition) |\ 418 ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ 419 (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\ 420 EADC_CMP_ADCMPEN_Msk)) 421 422 /** 423 * @brief Configure the comparator 2 and enable it. 424 * @param[in] eadc The pointer of the specified EADC module. 425 * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. 426 * @param[in] u32Condition specifies the compare condition. Valid values are: 427 * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" 428 * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value 429 * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. 430 * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. 431 * @return None 432 * @details For example, ADC_ENABLE_CMP2(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE); 433 * Means EADC will assert comparator 2 flag if sample module 5 conversion result is greater or 434 * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. 435 */ 436 #define EADC_ENABLE_CMP2(eadc,\ 437 u32ModuleNum,\ 438 u32Condition,\ 439 u16CMPData,\ 440 u32MatchCount) ((eadc)->CMP[2] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ 441 (u32Condition) |\ 442 ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ 443 (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\ 444 EADC_CMP_ADCMPEN_Msk)) 445 446 /** 447 * @brief Configure the comparator 3 and enable it. 448 * @param[in] eadc The pointer of the specified EADC module. 449 * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. 450 * @param[in] u32Condition specifies the compare condition. Valid values are: 451 * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" 452 * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value 453 * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. 454 * @param[in] u32MatchCount specifies the match count setting, valid range are between 1~0xF. 455 * @return None 456 * @details For example, ADC_ENABLE_CMP3(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE); 457 * Means EADC will assert comparator 3 flag if sample module 5 conversion result is greater or 458 * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. 459 */ 460 #define EADC_ENABLE_CMP3(eadc,\ 461 u32ModuleNum,\ 462 u32Condition,\ 463 u16CMPData,\ 464 u32MatchCount) ((eadc)->CMP[3] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ 465 (u32Condition) |\ 466 ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ 467 (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\ 468 EADC_CMP_ADCMPEN_Msk)) 469 470 /** 471 * @brief Enable the compare window mode. 472 * @param[in] eadc The pointer of the specified EADC module. 473 * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2. 474 * @return None 475 * @details ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched. 476 */ 477 #define EADC_ENABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_CMPWEN_Msk) 478 479 /** 480 * @brief Disable the compare window mode. 481 * @param[in] eadc The pointer of the specified EADC module. 482 * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2. 483 * @return None 484 * @details ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched. 485 */ 486 #define EADC_DISABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_CMPWEN_Msk) 487 488 /** 489 * @brief Enable the compare interrupt. 490 * @param[in] eadc The pointer of the specified EADC module. 491 * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3. 492 * @return None 493 * @details If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) 494 * and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, 495 * if ADCMPIE is set to 1, a compare interrupt request is generated. 496 */ 497 #define EADC_ENABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_ADCMPIE_Msk) 498 499 /** 500 * @brief Disable the compare interrupt. 501 * @param[in] eadc The pointer of the specified EADC module. 502 * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3. 503 * @return None 504 * @details This macro is used to disable the compare interrupt. 505 */ 506 #define EADC_DISABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_ADCMPIE_Msk) 507 508 /** 509 * @brief Disable comparator 0. 510 * @param[in] eadc The pointer of the specified EADC module. 511 * @return None 512 * @details This macro is used to disable comparator 0. 513 */ 514 #define EADC_DISABLE_CMP0(eadc) ((eadc)->CMP[0] = 0UL) 515 516 /** 517 * @brief Disable comparator 1. 518 * @param[in] eadc The pointer of the specified EADC module. 519 * @return None 520 * @details This macro is used to disable comparator 1. 521 */ 522 #define EADC_DISABLE_CMP1(eadc) ((eadc)->CMP[1] = 0UL) 523 524 /** 525 * @brief Disable comparator 2. 526 * @param[in] eadc The pointer of the specified EADC module. 527 * @return None 528 * @details This macro is used to disable comparator 2. 529 */ 530 #define EADC_DISABLE_CMP2(eadc) ((eadc)->CMP[2] = 0UL) 531 532 /** 533 * @brief Disable comparator 3. 534 * @param[in] eadc The pointer of the specified EADC module. 535 * @return None 536 * @details This macro is used to disable comparator 3. 537 */ 538 #define EADC_DISABLE_CMP3(eadc) ((eadc)->CMP[3] = 0UL) 539 540 /*---------------------------------------------------------------------------------------------------------*/ 541 /* Define EADC functions prototype */ 542 /*---------------------------------------------------------------------------------------------------------*/ 543 void EADC_Open(EADC_T *eadc, uint32_t u32InputMode); 544 void EADC_Close(EADC_T *eadc); 545 void EADC_ConfigSampleModule(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerSrc, uint32_t u32Channel); 546 void EADC_SetTriggerDelayTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerDelayTime, uint32_t u32DelayClockDivider); 547 void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime); 548 549 /**@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */ 550 551 /**@}*/ /* end of group EADC_Driver */ 552 553 /**@}*/ /* end of group Standard_Driver */ 554 555 #ifdef __cplusplus 556 } 557 #endif 558 559 #endif /* __EADC_H__ */ 560
