1 /**************************************************************************//**
2 * @file partition_M2351.c
3 * @version V3.00
4 * @brief SAU configuration for secure/nonsecure region settings.
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
8 *
9 ******************************************************************************/
10
11 #ifndef PARTITION_M2351
12 #define PARTITION_M2351
13
14
15 #include "region_defs.h"
16
17 /*
18 //-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
19 */
20
21
22 /*
23 SRAMNSSET
24 */
25 /*
26 // Bit 0..16
27 // <o.0..16> Secure SRAM Size <0=> 0 KB
28 // <0x2000=> 8KB
29 // <0x4000=> 16KB
30 // <0x6000=> 24KB
31 // <0x8000=> 32KB
32 // <0xa000=> 40KB
33 // <0xc000=> 48KB
34 // <0xe000=> 56KB
35 // <0x10000=> 64KB
36 // <0x12000=> 72KB
37 // <0x14000=> 80KB
38 // <0x16000=> 88KB
39 // <0x18000=> 96KB
40 */
41 #define SCU_SECURE_SRAM_SIZE S_DATA_SIZE
42 #define NON_SECURE_SRAM_BASE (0x30000000 + SCU_SECURE_SRAM_SIZE)
43
44
45
46 /*--------------------------------------------------------------------------------------------------------*/
47
48 /*
49 NSBA
50 */
51 #define FMC_INIT_NSBA 1
52 /*
53 <o>Secure Flash ROM Size <0x800-0x7FFFF:0x800>
54 */
55
56 #define FMC_SECURE_ROM_SIZE (FLASH_AREA_0_OFFSET + FLASH_AREA_0_SIZE)
57
58 #define FMC_NON_SECURE_BASE (NS_ROM_ALIAS_BASE + FMC_SECURE_ROM_SIZE)
59
FMC_NSBA_Setup(void)60 __STATIC_INLINE void FMC_NSBA_Setup(void)
61 {
62 /* Skip NSBA Setupt according config */
63 if(FMC_INIT_NSBA == 0)
64 return;
65
66 /* Check if NSBA value with current active NSBA */
67 if(SCU->FNSADDR != FMC_SECURE_ROM_SIZE)
68 {
69 /* Unlock Protected Register */
70 SYS_UnlockReg();
71
72 /* Enable ISP and config update */
73 FMC->ISPCTL = FMC_ISPCTL_ISPEN_Msk | FMC_ISPCTL_CFGUEN_Msk;
74
75 /* Config Base of NSBA */
76 FMC->ISPADDR = 0x200800;
77
78 /* Read Non-secure base address config */
79 FMC->ISPCMD = FMC_ISPCMD_READ;
80 FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
81 while(FMC->ISPTRG);
82
83 /* Setting NSBA when it is empty */
84 if(FMC->ISPDAT == 0xfffffffful)
85 {
86 FMC->ISPDAT = FMC_SECURE_ROM_SIZE;
87 FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
88 FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
89 while(FMC->ISPTRG);
90
91 /* Force Chip Reset to valid new setting */
92 SYS->IPRST0 = SYS_IPRST0_CHIPRST_Msk;
93 }
94
95 /* Fatal Error:
96 FMC NSBA setting is different to FMC_INIT_NSBA_VAL.
97 User must double confirm which one is wrong.
98
99 If user need to change NSBA config of FMC, user must do Mass-erase by
100 ISP or ICP.
101 */
102 while(1);
103 }
104
105 }
106
107
108 /*--------------------------------------------------------------------------------------------------------*/
109
110
111 /*
112 // <h> Peripheral Secure Attribution Configuration
113 */
114
115 /*
116 PNSSET0
117 */
118 /*
119 // Module 0..31
120 // <o.9> USBH <0=> Secure <1=> Non-Secure
121 // <o.13> SD0 <0=> Secure <1=> Non-Secure
122 // <o.16> EBI <0=> Secure <1=> Non-Secure
123 // <o.24> PDMA1 <0=> Secure <1=> Non-Secure
124 */
125 #define SCU_INIT_PNSSET0_VAL 0x0
126 /*
127 PNSSET1
128 */
129 /*
130 // Module 0..31
131 // <o.17> CRC <0=> Secure <1=> Non-Secure
132 // <o.18> CRPT <0=> Secure <1=> Non-Secure
133 */
134 #define SCU_INIT_PNSSET1_VAL 0x0
135 /*
136 PNSSET2
137 */
138 /*
139 // Module 0..31
140 // <o.1> RTC <0=> Secure <1=> Non-Secure
141 // <o.3> EADC <0=> Secure <1=> Non-Secure
142 // <o.5> ACMP01 <0=> Secure <1=> Non-Secure
143 //
144 // <o.7> DAC <0=> Secure <1=> Non-Secure
145 // <o.8> I2S0 <0=> Secure <1=> Non-Secure
146 // <o.13> OTG <0=> Secure <1=> Non-Secure
147 // <o.17> TMR23 <0=> Secure <1=> Non-Secure
148 // <h> EPWM
149 // <o.24> EPWM0 <0=> Secure <1=> Non-Secure
150 // <o.25> EPWM1 <0=> Secure <1=> Non-Secure
151 // <o.26> BPWM0 <0=> Secure <1=> Non-Secure
152 // <o.27> BPWM1 <0=> Secure <1=> Non-Secure
153 // </h>
154 */
155 #define SCU_INIT_PNSSET2_VAL 0x0
156 /*
157 PNSSET3
158 */
159 /*
160 // Module 0..31
161 // <h> SPI
162 // <o.0> QSPI0 <0=> Secure <1=> Non-Secure
163 // <o.1> SPI0 <0=> Secure <1=> Non-Secure
164 // <o.2> SPI1 <0=> Secure <1=> Non-Secure
165 // <o.3> SPI2 <0=> Secure <1=> Non-Secure
166 // <o.4> SPI3 <0=> Secure <1=> Non-Secure
167 // </h>
168 // <h> UART
169 // <o.16> UART0 <0=> Secure <1=> Non-Secure
170 // <o.17> UART1 <0=> Secure <1=> Non-Secure
171 // <o.18> UART2 <0=> Secure <1=> Non-Secure
172 // <o.19> UART3 <0=> Secure <1=> Non-Secure
173 // <o.20> UART4 <0=> Secure <1=> Non-Secure
174 // <o.21> UART5 <0=> Secure <1=> Non-Secure
175 // </h>
176 */
177 #define SCU_INIT_PNSSET3_VAL 0x10004
178 /*
179 PNSSET4
180 */
181 /*
182 // Module 0..31
183 // <h> I2C
184 // <o.0> I2C0 <0=> Secure <1=> Non-Secure
185 // <o.1> I2C1 <0=> Secure <1=> Non-Secure
186 // <o.2> I2C2 <0=> Secure <1=> Non-Secure
187 // </h>
188 // <h> Smart Card
189 // <o.16> SC0 <0=> Secure <1=> Non-Secure
190 // <o.17> SC1 <0=> Secure <1=> Non-Secure
191 // <o.18> SC2 <0=> Secure <1=> Non-Secure
192 // </h>
193 */
194 #define SCU_INIT_PNSSET4_VAL 0x0
195 /*
196 PNSSET5
197 */
198 /*
199 // Module 0..31
200 // <o.0> CAN0 <0=> Secure <1=> Non-Secure
201 // <h> QEI
202 // <o.16> QEI0 <0=> Secure <1=> Non-Secure
203 // <o.17> QEI1 <0=> Secure <1=> Non-Secure
204 // </h>
205 // <h> ECAP
206 // <o.20> ECAP0 <0=> Secure <1=> Non-Secure
207 // <o.21> ECAP1 <0=> Secure <1=> Non-Secure
208 // </h>
209 // <o.25> TRNG <0=> Secure <1=> Non-Secure
210 */
211 #define SCU_INIT_PNSSET5_VAL 0x0
212 /*
213 PNSSET6
214 */
215 /*
216 // Module 0..31
217 // <o.0> USBD <0=> Secure <1=> Non-Secure
218 // <h> USCI
219 // <o.16> USCI0 <0=> Secure <1=> Non-Secure
220 // <o.17> USCI1 <0=> Secure <1=> Non-Secure
221 // </h>
222 */
223 #define SCU_INIT_PNSSET6_VAL 0x0
224 /*
225 // </h>
226 */
227
228
229
230 /*
231 // <h> GPIO Secure Attribution Configuration
232 */
233
234 /*
235 IONSSET
236 */
237 /*
238 // Bit 0..31
239 // <o.0> PA <0=> Secure <1=> Non-Secure
240 // <o.1> PB <0=> Secure <1=> Non-Secure
241 // <o.2> PC <0=> Secure <1=> Non-Secure
242 // <o.3> PD <0=> Secure <1=> Non-Secure
243 // <o.4> PE <0=> Secure <1=> Non-Secure
244 // <o.5> PF <0=> Secure <1=> Non-Secure
245 // <o.6> PG <0=> Secure <1=> Non-Secure
246 // <o.7> PH <0=> Secure <1=> Non-Secure
247 */
248 #define SCU_INIT_IONSSET_VAL 0x1
249 /*
250 // </h>
251 */
252
253
254
255 /**
256 \brief Setup SCU Configuration Unit
257 \details
258
259 */
SCU_Setup(void)260 __STATIC_INLINE void SCU_Setup(void)
261 {
262 int32_t i;
263
264 SCU->PNSSET[0] = SCU_INIT_PNSSET0_VAL;
265 SCU->PNSSET[1] = SCU_INIT_PNSSET1_VAL;
266 SCU->PNSSET[2] = SCU_INIT_PNSSET2_VAL;
267 SCU->PNSSET[3] = SCU_INIT_PNSSET3_VAL;
268 SCU->PNSSET[4] = SCU_INIT_PNSSET4_VAL;
269 SCU->PNSSET[5] = SCU_INIT_PNSSET5_VAL;
270 SCU->PNSSET[6] = SCU_INIT_PNSSET6_VAL;
271
272 SCU->IONSSET = SCU_INIT_IONSSET_VAL;
273
274 /* Set Non-secure SRAM */
275 for(i = 11; i >= S_DATA_SIZE / 8192; i--)
276 {
277 SCU->SRAMNSSET |= (1U << i);
278 }
279
280
281 }
282
283
284 /* ---------------------------------------------------------------------------------------------------- */
285
286 /*
287 // <e>Secure Attribute Unit (SAU) Control
288 */
289 #define SAU_INIT_CTRL 1
290
291 /*
292 // <q> Enable SAU
293 // <i> To enable Secure Attribute Unit (SAU).
294 */
295 #define SAU_INIT_CTRL_ENABLE 1
296
297 /*
298 // <o> All Memory Attribute When SAU is disabled
299 // <0=> All Memory is Secure
300 // <1=> All Memory is Non-Secure
301 // <i> To set the ALLNS bit in SAU CTRL.
302 // <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
303 */
304 #define SAU_INIT_CTRL_ALLNS 0
305
306 /*
307 // </e>
308 */
309
310
311 /*
312 // <h>Enable and Set Secure/Non-Secure region
313 */
314 #define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
315
316 /*
317 // <e>SAU Region 0
318 // <i> Setup SAU Region 0
319 */
320 #define SAU_INIT_REGION0 0
321 /*
322 // <o>Start Address <0-0xFFFFFFE0>
323 */
324 #define SAU_INIT_START0 0x0003F000 /* start address of SAU region 0 */
325 /*
326 // <o>End Address <0x1F-0xFFFFFFFF>
327 */
328 #define SAU_INIT_END0 0x0003FFFF /* end address of SAU region 0 */
329 /*
330 // <o>Region is
331 // <0=>Non-Secure
332 // <1=>Secure, Non-Secure Callable
333 */
334 #define SAU_INIT_NSC0 1
335 /*
336 // </e>
337 */
338
339 /*
340 // <e>SAU Region 1
341 // <i> Setup SAU Region 1
342 */
343 #define SAU_INIT_REGION1 0
344 /*
345 // <o>Start Address <0-0xFFFFFFE0>
346 */
347 #define SAU_INIT_START1 0x10060000
348 /*
349 // <o>End Address <0x1F-0xFFFFFFFF>
350 */
351 #define SAU_INIT_END1 0x1007FFFF
352 /*
353 // <o>Region is
354 // <0=>Non-Secure
355 // <1=>Secure, Non-Secure Callable
356 */
357 #define SAU_INIT_NSC1 0
358 /*
359 // </e>
360 */
361
362 /*
363 // <e>SAU Region 2
364 // <i> Setup SAU Region 2
365 */
366 #define SAU_INIT_REGION2 0
367 /*
368 // <o>Start Address <0-0xFFFFFFE0>
369 */
370 #define SAU_INIT_START2 0x2000F000
371 /*
372 // <o>End Address <0x1F-0xFFFFFFFF>
373 */
374 #define SAU_INIT_END2 0x2000FFFF
375 /*
376 // <o>Region is
377 // <0=>Non-Secure
378 // <1=>Secure, Non-Secure Callable
379 */
380 #define SAU_INIT_NSC2 1
381 /*
382 // </e>
383 */
384
385 /*
386 // <e>SAU Region 3
387 // <i> Setup SAU Region 3
388 */
389 #define SAU_INIT_REGION3 0
390 /*
391 // <o>Start Address <0-0xFFFFFFE0>
392 */
393 #define SAU_INIT_START3 0x0003F000
394 /*
395 // <o>End Address <0x1F-0xFFFFFFFF>
396 */
397 #define SAU_INIT_END3 0x0003F7FF
398 /*
399 // <o>Region is
400 // <0=>Non-Secure
401 // <1=>Secure, Non-Secure Callable
402 */
403 #define SAU_INIT_NSC3 1
404 /*
405 // </e>
406 */
407
408 /*
409 <e>SAU Region 4
410 <i> Setup SAU Region 4
411 */
412 #define SAU_INIT_REGION4 0
413 /*
414 <o>Start Address <0-0xFFFFFFE0>
415 */
416 #define SAU_INIT_START4 FMC_NON_SECURE_BASE /* start address of SAU region 4 */
417
418 /*
419 <o>End Address <0x1F-0xFFFFFFFF>
420 */
421 #define SAU_INIT_END4 0x1007FFFF /* end address of SAU region 4 */
422
423 /*
424 <o>Region is
425 <0=>Non-Secure
426 <1=>Secure, Non-Secure Callable
427 */
428 #define SAU_INIT_NSC4 0
429 /*
430 </e>
431 */
432
433 /*
434 <e>SAU Region 5
435 <i> Setup SAU Region 5
436 */
437 #define SAU_INIT_REGION5 1
438
439 /*
440 <o>Start Address <0-0xFFFFFFE0>
441 */
442 #define SAU_INIT_START5 0x00807E00
443
444 /*
445 <o>End Address <0x1F-0xFFFFFFFF>
446 */
447 #define SAU_INIT_END5 0x00807FFF
448
449 /*
450 <o>Region is
451 <0=>Non-Secure
452 <1=>Secure, Non-Secure Callable
453 */
454 #define SAU_INIT_NSC5 1
455 /*
456 </e>
457 */
458
459 /*
460 <e>SAU Region 6
461 <i> Setup SAU Region 6
462 */
463 #define SAU_INIT_REGION6 0
464
465 /*
466 <o>Start Address <0-0xFFFFFFE0>
467 */
468 #define SAU_INIT_START6 NON_SECURE_SRAM_BASE
469
470 /*
471 <o>End Address <0x1F-0xFFFFFFFF>
472 */
473 #define SAU_INIT_END6 0x30017FFF
474
475 /*
476 <o>Region is
477 <0=>Non-Secure
478 <1=>Secure, Non-Secure Callable
479 */
480 #define SAU_INIT_NSC6 0
481 /*
482 </e>
483 */
484
485 /*
486 <e>SAU Region 7
487 <i> Setup SAU Region 7
488 */
489 #define SAU_INIT_REGION7 0
490
491 /*
492 <o>Start Address <0-0xFFFFFFE0>
493 */
494 #define SAU_INIT_START7 0x50000000
495
496 /*
497 <o>End Address <0x1F-0xFFFFFFFF>
498 */
499 #define SAU_INIT_END7 0x5FFFFFFF
500
501 /*
502 <o>Region is
503 <0=>Non-Secure
504 <1=>Secure, Non-Secure Callable
505 */
506 #define SAU_INIT_NSC7 0
507 /*
508 </e>
509 */
510
511 /*
512 // </h>
513 */
514
515 /*
516 // <e>Setup behavior of Sleep and Exception Handling
517 */
518 #define SCB_CSR_AIRCR_INIT 1
519
520 /*
521 // <o> Deep Sleep can be enabled by
522 // <0=>Secure and Non-Secure state
523 // <1=>Secure state only
524 // <i> Value for SCB->CSR register bit DEEPSLEEPS
525 */
526 #define SCB_CSR_DEEPSLEEPS_VAL 0
527
528 /*
529 // <o>System reset request accessible from
530 // <0=> Secure and Non-Secure state
531 // <1=> Secure state only
532 // <i> Value for SCB->AIRCR register bit SYSRESETREQS
533 */
534 #define SCB_AIRCR_SYSRESETREQS_VAL 0
535
536 /*
537 // <o>Priority of Non-Secure exceptions is
538 // <0=> Not altered
539 // <1=> Lowered to 0x80-0xFF
540 // <i> Value for SCB->AIRCR register bit PRIS
541 */
542 #define SCB_AIRCR_PRIS_VAL 0
543
544 /* Assign HardFault to be always secure for safe */
545 #define SCB_AIRCR_BFHFNMINS_VAL 0
546
547 /*
548 // </e>
549 */
550
551
552 /*
553 // <h>Assign Interrupt to Secure or Non-secure Vector
554 */
555
556
557 /*
558 Initialize ITNS 0 (Interrupts 0..31)
559 */
560 #define NVIC_INIT_ITNS0 1
561 /*
562 // BODOUT Always secure
563 // IRC Always secure
564 // PWRWU_ Always secure
565 // SRAM_PERR Always secure
566 // CLKFAIL Always secure
567
568 // <o.6> RTC <0=> Secure <1=> Non-Secure
569 // <o.7> TAMPER <0=> Secure <1=> Non-Secure
570 // WDT Always secure
571 // WWDT Always secure
572 // <h> EINT
573 // <o.10> EINT0 <0=> Secure <1=> Non-Secure
574 // <o.11> EINT1 <0=> Secure <1=> Non-Secure
575 // <o.12> EINT2 <0=> Secure <1=> Non-Secure
576 // <o.13> EINT3 <0=> Secure <1=> Non-Secure
577 // <o.14> EINT4 <0=> Secure <1=> Non-Secure
578 // <o.15> EINT5 <0=> Secure <1=> Non-Secure
579 // </h>
580 // <h> GPIO
581 // <o.16> GPA <0=> Secure <1=> Non-Secure
582 // <o.17> GPB <0=> Secure <1=> Non-Secure
583 // <o.18> GPC <0=> Secure <1=> Non-Secure
584 // <o.19> GPD <0=> Secure <1=> Non-Secure
585 // <o.20> GPE <0=> Secure <1=> Non-Secure
586 // <o.21> GPF <0=> Secure <1=> Non-Secure
587 // </h>
588 // <o.22> QSPI0 <0=> Secure <1=> Non-Secure
589 // <o.23> SPI0 <0=> Secure <1=> Non-Secure
590 // <h> EPWM
591 // <o.24> BRAKE0 <0=> Secure <1=> Non-Secure
592 // <o.25> EPWM0_P0 <0=> Secure <1=> Non-Secure
593 // <o.26> EPWM0_P1 <0=> Secure <1=> Non-Secure
594 // <o.27> EPWM0_P2 <0=> Secure <1=> Non-Secure
595 // <o.28> BRAKE1 <0=> Secure <1=> Non-Secure
596 // <o.29> EPWM1_P0 <0=> Secure <1=> Non-Secure
597 // <o.30> EPWM1_P1 <0=> Secure <1=> Non-Secure
598 // <o.31> EPWM1_P2 <0=> Secure <1=> Non-Secure
599 // </h>
600 //
601 */
602 #define NVIC_INIT_ITNS0_VAL 0x40000
603
604 /*
605 Initialize ITNS 1 (Interrupts 0..31)
606 */
607 #define NVIC_INIT_ITNS1 1
608 /*
609 // <h> TIMER
610 // TMR0 Always secure
611 // TMR1 Always secure
612 // <o.2> TMR2 <0=> Secure <1=> Non-Secure
613 // <o.3> TMR3 <0=> Secure <1=> Non-Secure
614 // </h>
615 // <o.4> UART0 <0=> Secure <1=> Non-Secure
616 // <o.5> UART1 <0=> Secure <1=> Non-Secure
617 // <o.6> I2C0 <0=> Secure <1=> Non-Secure
618 // <o.7> I2C1 <0=> Secure <1=> Non-Secure
619 // PDMA0 is secure only
620 // <o.9> DAC <0=> Secure <1=> Non-Secure
621 // <o.10> EADC0 <0=> Secure <1=> Non-Secure
622 // <o.11> EADC1 <0=> Secure <1=> Non-Secure
623 // <o.12> ACMP01 <0=> Secure <1=> Non-Secure
624
625 // <o.14> EADC2 <0=> Secure <1=> Non-Secure
626 // <o.15> EADC3 <0=> Secure <1=> Non-Secure
627 // <o.16> UART2 <0=> Secure <1=> Non-Secure
628 // <o.17> UART3 <0=> Secure <1=> Non-Secure
629
630 // <o.19> SPI1 <0=> Secure <1=> Non-Secure
631 // <o.20> SPI2 <0=> Secure <1=> Non-Secure
632 // <o.21> USBD <0=> Secure <1=> Non-Secure
633 // <o.22> USBH <0=> Secure <1=> Non-Secure
634 // <o.23> USBOTG <0=> Secure <1=> Non-Secure
635 // <o.24> CAN0 <0=> Secure <1=> Non-Secure
636
637 // <h> Smart Card
638 // <o.26> SC0 <0=> Secure <1=> Non-Secure
639 // <o.27> SC1 <0=> Secure <1=> Non-Secure
640 // <o.28> SC2 <0=> Secure <1=> Non-Secure
641 // </h>
642
643 // <o.30> SPI3 <0=> Secure <1=> Non-Secure
644
645 //
646 */
647 #define NVIC_INIT_ITNS1_VAL 0x10
648
649 /*
650 Initialize ITNS 2 (Interrupts 0..31)
651 */
652 #define NVIC_INIT_ITNS2 1
653 /*
654 // <o.0> SDH0 <0=> Secure <1=> Non-Secure
655
656
657
658 // <o.4> I2S0 <0=> Secure <1=> Non-Secure
659
660 //
661 // <o.7> CRYPTO <0=> Secure <1=> Non-Secure
662 // <o.8> GPG <0=> Secure <1=> Non-Secure
663 // <o.9> EINT6 <0=> Secure <1=> Non-Secure
664 // <o.10> UART4 <0=> Secure <1=> Non-Secure
665 // <o.11> UART5 <0=> Secure <1=> Non-Secure
666 // <o.12> USCI0 <0=> Secure <1=> Non-Secure
667 // <o.13> USCI1 <0=> Secure <1=> Non-Secure
668 // <o.14> BPWM0 <0=> Secure <1=> Non-Secure
669 // <o.15> BPWM1 <0=> Secure <1=> Non-Secure
670
671
672 // <o.18> I2C2 <0=> Secure <1=> Non-Secure
673
674 // <o.20> QEI0 <0=> Secure <1=> Non-Secure
675 // <o.21> QEI1 <0=> Secure <1=> Non-Secure
676 // <o.22> ECAP0 <0=> Secure <1=> Non-Secure
677 // <o.23> ECAP1 <0=> Secure <1=> Non-Secure
678 // <o.24> GPH <0=> Secure <1=> Non-Secure
679 // <o.25> EINT7 <0=> Secure <1=> Non-Secure
680
681
682 // <o.28> USBH <0=> Secure <1=> Non-Secure
683
684
685
686 //
687 */
688 #define NVIC_INIT_ITNS2_VAL 0x0
689
690
691 /*
692 Initialize ITNS 3 (Interrupts 0..31)
693 */
694 #define NVIC_INIT_ITNS3 1
695 /*
696 // <o.2> PDMA1 <0=> Secure <1=> Non-Secure
697 // SCU Always secure
698 //
699 // <o.5> TRNG <0=> Secure <1=> Non-Secure
700 */
701 #define NVIC_INIT_ITNS3_VAL 0x0
702
703
704
705 /*
706 // </h>
707 */
708
709
710
711 /*
712 max 128 SAU regions.
713 SAU regions are defined in partition.h
714 */
715
716 #define SAU_INIT_REGION(n) \
717 SAU->RNR = (n & SAU_RNR_REGION_Msk); \
718 SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
719 SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
720 ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
721
722 /**
723 \brief Setup a SAU Region
724 \details Writes the region information contained in SAU_Region to the
725 registers SAU_RNR, SAU_RBAR, and SAU_RLAR
726 */
TZ_SAU_Setup(void)727 __STATIC_INLINE void TZ_SAU_Setup(void)
728 {
729
730 #if defined (__SAU_PRESENT) && (__SAU_PRESENT == 1U)
731
732 #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
733 SAU_INIT_REGION(0);
734 #endif
735
736 #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
737 SAU_INIT_REGION(1);
738 #endif
739
740 #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
741 SAU_INIT_REGION(2);
742 #endif
743
744 #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
745 SAU_INIT_REGION(3);
746 #endif
747
748 #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
749 SAU_INIT_REGION(4);
750 #endif
751
752 #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
753 SAU_INIT_REGION(5);
754 #endif
755
756 #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
757 SAU_INIT_REGION(6);
758 #endif
759
760 #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
761 SAU_INIT_REGION(7);
762 #endif
763
764 /* repeat this for all possible SAU regions */
765
766
767 #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
768 SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
769 ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
770 #endif
771
772 #endif /* defined (__SAU_PRESENT) && (__SAU_PRESENT == 1U) */
773
774 #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
775 SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk)) |
776 ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
777
778 // SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_SYSRESETREQS_Msk | SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk)) |
779 // ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
780 // ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk) |
781 // ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk);
782
783 SCB->AIRCR = (0x05FA << 16) |
784 ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
785 ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk) |
786 ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk);
787
788
789
790 #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
791
792 #if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U)
793 SCB->ICSR = (SCB->ICSR & ~(SCB_ICSR_STTNS_Msk)) |
794 ((SCB_ICSR_STTNS_VAL << SCB_ICSR_STTNS_Pos) & SCB_ICSR_STTNS_Msk);
795 #endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */
796
797 #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
798 NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
799 #endif
800
801 #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
802 NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
803 #endif
804
805 #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
806 NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
807 #endif
808
809 #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
810 NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
811 #endif
812
813
814 /* repeat this for all possible ITNS elements */
815
816 }
817
818
819 #endif /* PARTITION_M2351 */
820
821
