1 /**************************************************************************//** 2 * @file wwdt_reg.h 3 * @version V1.00 4 * @brief WWDT register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __WWDT_REG_H__ 10 #define __WWDT_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 19 /*---------------------- Window Watchdog Timer -------------------------*/ 20 /** 21 @addtogroup WWDT Window Watchdog Timer(WWDT) 22 Memory Mapped Structure for WWDT Controller 23 @{ 24 */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var WWDT_T::RLDCNT 32 * Offset: 0x00 WWDT Reload Counter Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[31:0] |RLDCNT |WWDT Reload Counter Register 37 * | | |Writing only 0x00005AA5 to this register will reload the WWDT counter value to 0x3F. 38 * | | |Note1: User can only write execute WWDT_RLDCNT register to the reload WWDT counter value command when current current WWDT counter value CNTDAT (WWDT_CNT[5:0]) is between 10 and CMPDAT (WWDT_CTL[21:16]) 39 * | | |If user writes 0x00005AA5 in WWDT_RLDCNT register when current current CNTDATWWDT counter value is larger than CMPDAT, WWDT reset signal system event will be generated immediately. 40 * | | |Note2: Execute WWDT counter reload always needs (WWDT_CLK *3) period to reload CNTDAT to 0x3F and internal prescale counter will be reset also. 41 * @var WWDT_T::CTL 42 * Offset: 0x04 WWDT Control Register 43 * --------------------------------------------------------------------------------------------------- 44 * |Bits |Field |Descriptions 45 * | :----: | :----: | :---- | 46 * |[0] |WWDTEN |WWDT Enable Control Bit 47 * | | |Set this bit to enable start WWDT counter counting. 48 * | | |0 = WWDT counter is stopped. 49 * | | |1 = WWDT counter is starting counting. 50 * |[1] |INTEN |WWDT Interrupt Enable Control Bit 51 * | | |If this bit is enabled, when WWDTIF (WWDT_STATUS[0]) is set to 1, the WWDT counter compare match interrupt signal is generated and inform to CPU. 52 * | | |0 = WWDT counter compare match interrupt Disabled. 53 * | | |1 = WWDT counter compare match interrupt Enabled. 54 * |[11:8] |PSCSEL |WWDT Counter Prescale Period Selection 55 * | | |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK. 56 * | | |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK. 57 * | | |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK. 58 * | | |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK. 59 * | | |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK. 60 * | | |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK. 61 * | | |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK. 62 * | | |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK. 63 * | | |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK. 64 * | | |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK. 65 * | | |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK. 66 * | | |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK. 67 * | | |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK. 68 * | | |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK. 69 * | | |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK. 70 * | | |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK. 71 * |[21:16] |CMPDAT |WWDT Window Compare Register Value 72 * | | |Set this register field to adjust the valid reload window interval when WWDTIF (WWDT_STATUS[0]) is generated.. 73 * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT CNTDAT (WWDT_CNT[5:]) is counter value between 10 and CMPDAT 74 * | | |If user writes 0x00005AA5 in WWDT_RLDCNT register when current WWDT counter value CNTDAT is larger than CMPDAT, WWDT reset system event signal will be generated immediately. 75 * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control 76 * | | |0 = ICE debug mode acknowledgment effects WWDT counter counting. 77 * | | |WWDT down counter will be held while CPU is held by ICE. 78 * | | |1 = ICE debug mode acknowledgment Disabled. 79 * | | |WWDT down counter will keep going counting no matter CPU is held by ICE or not. 80 * @var WWDT_T::STATUS 81 * Offset: 0x08 WWDT Status Register 82 * --------------------------------------------------------------------------------------------------- 83 * |Bits |Field |Descriptions 84 * | :----: | :----: | :---- | 85 * |[0] |WWDTIF |WWDT Compare Match Interrupt Flag 86 * | | |This bit indicates the that current CNTDAT (WWDT_CNT[5:0]) matches the CMPDAT (WWDT_CTL[21:16])interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]). 87 * | | |0 = No effect. 88 * | | |1 = WWDT WWDT CNTDAT counter value matches the CMPDAT. 89 * | | |Note: This bit is cleared by writing 1 to it. 90 * |[1] |WWDTRF |WWDT Timer-out Reset System Flag 91 * | | |If this bit is set to 1, it This bit indicates the that system has been reset by WWDT counter time-out reset system event.or not. 92 * | | |0 = WWDT time-out reset system event did not occur. 93 * | | |1 = WWDT time-out reset system event occurred. 94 * | | |Note: This bit is cleared by writing 1 to it. 95 * @var WWDT_T::CNT 96 * Offset: 0x0C WWDT Counter Value Register 97 * --------------------------------------------------------------------------------------------------- 98 * |Bits |Field |Descriptions 99 * | :----: | :----: | :---- | 100 * |[5:0] |CNTDAT |WWDT Counter Value 101 * | | |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value. 102 */ 103 __O uint32_t RLDCNT; /*!< [0x0000] WWDT Reload Counter Register */ 104 __IO uint32_t CTL; /*!< [0x0004] WWDT Control Register */ 105 __IO uint32_t STATUS; /*!< [0x0008] WWDT Status Register */ 106 __I uint32_t CNT; /*!< [0x000c] WWDT Counter Value Register */ 107 108 } WWDT_T; 109 110 111 /** 112 @addtogroup WWDT_CONST WWDT Bit Field Definition 113 Constant Definitions for WWDT Controller 114 @{ 115 */ 116 117 #define WWDT_RLDCNT_RLDCNT_Pos (0) /*!< WWDT_T::RLDCNT: RLDCNT Position */ 118 #define WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos) /*!< WWDT_T::RLDCNT: RLDCNT Mask */ 119 120 #define WWDT_CTL_WWDTEN_Pos (0) /*!< WWDT_T::CTL: WWDTEN Position */ 121 #define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) /*!< WWDT_T::CTL: WWDTEN Mask */ 122 123 #define WWDT_CTL_INTEN_Pos (1) /*!< WWDT_T::CTL: INTEN Position */ 124 #define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) /*!< WWDT_T::CTL: INTEN Mask */ 125 126 #define WWDT_CTL_PSCSEL_Pos (8) /*!< WWDT_T::CTL: PSCSEL Position */ 127 #define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) /*!< WWDT_T::CTL: PSCSEL Mask */ 128 129 #define WWDT_CTL_CMPDAT_Pos (16) /*!< WWDT_T::CTL: CMPDAT Position */ 130 #define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) /*!< WWDT_T::CTL: CMPDAT Mask */ 131 132 #define WWDT_CTL_ICEDEBUG_Pos (31) /*!< WWDT_T::CTL: ICEDEBUG Position */ 133 #define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) /*!< WWDT_T::CTL: ICEDEBUG Mask */ 134 135 #define WWDT_STATUS_WWDTIF_Pos (0) /*!< WWDT_T::STATUS: WWDTIF Position */ 136 #define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) /*!< WWDT_T::STATUS: WWDTIF Mask */ 137 138 #define WWDT_STATUS_WWDTRF_Pos (1) /*!< WWDT_T::STATUS: WWDTRF Position */ 139 #define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) /*!< WWDT_T::STATUS: WWDTRF Mask */ 140 141 #define WWDT_CNT_CNTDAT_Pos (0) /*!< WWDT_T::CNT: CNTDAT Position */ 142 #define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) /*!< WWDT_T::CNT: CNTDAT Mask */ 143 144 /**@}*/ /* WWDT_CONST */ 145 /**@}*/ /* end of WWDT register group */ 146 /**@}*/ /* end of REGISTER group */ 147 148 #endif /* __WWDT_REG_H__ */ 149
