1 /**************************************************************************//** 2 * @file uuart_reg.h 3 * @version V1.00 4 * @brief UUART register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __UUART_REG_H__ 10 #define __UUART_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 19 /*---------------------- UART Mode of USCI Controller -------------------------*/ 20 /** 21 @addtogroup UUART UART Mode of USCI Controller(UUART) 22 Memory Mapped Structure for UUART Controller 23 @{ 24 */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var UUART_T::CTL 32 * Offset: 0x00 USCI Control Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[2:0] |FUNMODE |Function Mode 37 * | | |This bit field selects the protocol for this USCI controller. 38 * | | |Selecting a protocol that is not available or a reserved combination disables the USCI. 39 * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol. 40 * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE. 41 * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state. 42 * | | |001 = The SPI protocol is selected. 43 * | | |010 = The UART protocol is selected. 44 * | | |100 = The I2C protocol is selected. 45 * | | |Others = Reserved. 46 * @var UUART_T::INTEN 47 * Offset: 0x04 USCI Interrupt Enable Register 48 * --------------------------------------------------------------------------------------------------- 49 * |Bits |Field |Descriptions 50 * | :----: | :----: | :---- | 51 * |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit 52 * | | |This bit enables the interrupt generation in case of a transmit start event. 53 * | | |0 = The transmit start interrupt is disabled. 54 * | | |1 = The transmit start interrupt is enabled. 55 * |[2] |TXENDIEN |Transmit End Interrupt Enable Bit 56 * | | |This bit enables the interrupt generation in case of a transmit finish event. 57 * | | |0 = The transmit finish interrupt is disabled. 58 * | | |1 = The transmit finish interrupt is enabled. 59 * |[3] |RXSTIEN |Receive Start Interrupt Enable Bit 60 * | | |This bit enables the interrupt generation in case of a receive start event. 61 * | | |0 = The receive start interrupt is disabled. 62 * | | |1 = The receive start interrupt is enabled. 63 * |[4] |RXENDIEN |Receive End Interrupt Enable Bit 64 * | | |This bit enables the interrupt generation in case of a receive finish event. 65 * | | |0 = The receive end interrupt is disabled. 66 * | | |1 = The receive end interrupt is enabled. 67 * @var UUART_T::BRGEN 68 * Offset: 0x08 USCI Baud Rate Generator Register 69 * --------------------------------------------------------------------------------------------------- 70 * |Bits |Field |Descriptions 71 * | :----: | :----: | :---- | 72 * |[0] |RCLKSEL |Reference Clock Source Selection 73 * | | |This bit selects the source signal of reference clock (fREF_CLK). 74 * | | |0 = Peripheral device clock fPCLK. 75 * | | |1 = Reserved. 76 * |[1] |PTCLKSEL |Protocol Clock Source Selection 77 * | | |This bit selects the source signal of protocol clock (fPROT_CLK). 78 * | | |0 = Reference clock fREF_CLK. 79 * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK). 80 * |[3:2] |SPCLKSEL |Sample Clock Source Selection 81 * | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. 82 * | | |00 = fSAMP_CLK frequency is fDIV_CLK. 83 * | | |01 = fSAMP_CLK frequency is from fPROT_CLK. 84 * | | |10 = fSAMP_CLK frequency is from fSCLK. 85 * | | |11 = fSAMP_CLK frequency is from fREF_CLK. 86 * |[4] |TMCNTEN |Timing Measurement Counter Enable Bit 87 * | | |This bit enables the 10-bit timing measurement counter. 88 * | | |0 = Timing measurement counter is Disabled. 89 * | | |1 = Timing measurement counter is Enabled. 90 * |[5] |TMCNTSRC |Timing Measurement Counter Clock Source Selection 91 * | | |0 = Timing measurement counter with fPROT_CLK. 92 * | | |1 = Timing measurement counter with fDIV_CLK. 93 * |[9:8] |PDSCNT |Pre-divider for Sample Counter 94 * | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK. 95 * | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1). 96 * |[14:10] |DSCNT |Denominator for Sample Counter 97 * | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK. 98 * | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1). 99 * | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value. 100 * |[25:16] |CLKDIV |Clock Divider 101 * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ). 102 * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. 103 * | | |The revised value is the average bit time between bit 5 and bit 6. 104 * | | |The user can use revised CLKDIV and new BRDETITV (UUART_PROTCTL[24:16]) to calculate the precise baud rate. 105 * @var UUART_T::DATIN0 106 * Offset: 0x10 USCI Input Data Signal Configuration Register 0 107 * --------------------------------------------------------------------------------------------------- 108 * |Bits |Field |Descriptions 109 * | :----: | :----: | :---- | 110 * |[0] |SYNCSEL |Input Signal Synchronization Selection 111 * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 112 * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. 113 * | | |1 = The synchronized signal can be taken as input for the data shift unit. 114 * |[2] |ININV |Input Signal Inverse Selection 115 * | | |This bit defines the inverter enable of the input asynchronous signal. 116 * | | |0 = The un-synchronized input signal will not be inverted. 117 * | | |1 = The un-synchronized input signal will be inverted. 118 * |[4:3] |EDGEDET |Input Signal Edge Detection Mode 119 * | | |This bit field selects which edge actives the trigger event of input data signal. 120 * | | |00 = The trigger event activation is disabled. 121 * | | |01 = A rising edge activates the trigger event of input data signal. 122 * | | |10 = A falling edge activates the trigger event of input data signal. 123 * | | |11 = Both edges activate the trigger event of input data signal. 124 * | | |Note: In UART function mode, it is suggested to set this bit field as 10. 125 * @var UUART_T::CTLIN0 126 * Offset: 0x20 USCI Input Control Signal Configuration Register 0 127 * --------------------------------------------------------------------------------------------------- 128 * |Bits |Field |Descriptions 129 * | :----: | :----: | :---- | 130 * |[0] |SYNCSEL |Input Synchronization Signal Selection 131 * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 132 * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. 133 * | | |1 = The synchronized signal can be taken as input for the data shift unit. 134 * |[2] |ININV |Input Signal Inverse Selection 135 * | | |This bit defines the inverter enable of the input asynchronous signal. 136 * | | |0 = The un-synchronized input signal will not be inverted. 137 * | | |1 = The un-synchronized input signal will be inverted. 138 * @var UUART_T::CLKIN 139 * Offset: 0x28 USCI Input Clock Signal Configuration Register 140 * --------------------------------------------------------------------------------------------------- 141 * |Bits |Field |Descriptions 142 * | :----: | :----: | :---- | 143 * |[0] |SYNCSEL |Input Synchronization Signal Selection 144 * | | |This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 145 * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. 146 * | | |1 = The synchronized signal can be taken as input for the data shift unit. 147 * @var UUART_T::LINECTL 148 * Offset: 0x2C USCI Line Control Register 149 * --------------------------------------------------------------------------------------------------- 150 * |Bits |Field |Descriptions 151 * | :----: | :----: | :---- | 152 * |[0] |LSB |LSB First Transmission Selection 153 * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first. 154 * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first. 155 * |[5] |DATOINV |Data Output Inverse Selection 156 * | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin. 157 * | | |0 = The value of USCIx_DAT1 is equal to the data shift register. 158 * | | |1 = The value of USCIx_DAT1 is the inversion of data shift register. 159 * |[7] |CTLOINV |Control Signal Output Inverse Selection 160 * | | |This bit defines the relation between the internal control signal and the output control signal. 161 * | | |0 = No effect. 162 * | | |1 = The control signal will be inverted before its output. 163 * | | |Note: In UART protocol, the control signal means nRTS signal. 164 * |[11:8] |DWIDTH |Word Length of Transmission 165 * | | |This bit field defines the data word length (amount of bits) for reception and transmission 166 * | | |The data word is always right-aligned in the data buffer 167 * | | |USCI support word length from 4 to 16 bits. 168 * | | |0x0 = The data word contains 16 bits located at bit positions [15:0]. 169 * | | |0x1 = Reserved. 170 * | | |0x2 = Reserved. 171 * | | |0x3 = Reserved. 172 * | | |0x4 = The data word contains 4 bits located at bit positions [3:0]. 173 * | | |0x5 = The data word contains 5 bits located at bit positions [4:0]. 174 * | | |... 175 * | | |0xF = The data word contains 15 bits located at bit positions [14:0]. 176 * | | |Note: In UART protocol, the length can be configured as 6~13 bits. 177 * @var UUART_T::TXDAT 178 * Offset: 0x30 USCI Transmit Data Register 179 * --------------------------------------------------------------------------------------------------- 180 * |Bits |Field |Descriptions 181 * | :----: | :----: | :---- | 182 * |[15:0] |TXDAT |Transmit Data 183 * | | |Software can use this bit field to write 16-bit transmit data for transmission. 184 * @var UUART_T::RXDAT 185 * Offset: 0x34 USCI Receive Data Register 186 * --------------------------------------------------------------------------------------------------- 187 * |Bits |Field |Descriptions 188 * | :----: | :----: | :---- | 189 * |[15:0] |RXDAT |Received Data 190 * | | |This bit field monitors the received data which stored in receive data buffer. 191 * | | |Note: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UUART_PROTSTS[7:5]). 192 * @var UUART_T::BUFCTL 193 * Offset: 0x38 USCI Transmit/Receive Buffer Control Register 194 * --------------------------------------------------------------------------------------------------- 195 * |Bits |Field |Descriptions 196 * | :----: | :----: | :---- | 197 * |[7] |TXCLR |Clear Transmit Buffer 198 * | | |0 = No effect. 199 * | | |1 = The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value). 200 * | | |Should only be used while the buffer is not taking part in data traffic. 201 * | | |Note: It is cleared automatically after one PCLK cycle. 202 * |[14] |RXOVIEN |Receive Buffer Overrun Error Interrupt Enable Control 203 * | | |0 = Receive overrun interrupt Disabled. 204 * | | |1 = Receive overrun interrupt Enabled. 205 * |[15] |RXCLR |Clear Receive Buffer 206 * | | |0 = No effect. 207 * | | |1 = The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value). 208 * | | |Should only be used while the buffer is not taking part in data traffic. 209 * | | |Note: It is cleared automatically after one PCLK cycle. 210 * |[16] |TXRST |Transmit Reset 211 * | | |0 = No effect. 212 * | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer. 213 * | | |Note: It is cleared automatically after one PCLK cycle. 214 * |[17] |RXRST |Receive Reset 215 * | | |0 = No effect. 216 * | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer. 217 * | | |Note1: It is cleared automatically after one PCLK cycle. 218 * | | |Note2: It is suggest to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1. 219 * @var UUART_T::BUFSTS 220 * Offset: 0x3C USCI Transmit/Receive Buffer Status Register 221 * --------------------------------------------------------------------------------------------------- 222 * |Bits |Field |Descriptions 223 * | :----: | :----: | :---- | 224 * |[0] |RXEMPTY |Receive Buffer Empty Indicator 225 * | | |0 = Receive buffer is not empty. 226 * | | |1 = Receive buffer is empty. 227 * |[1] |RXFULL |Receive Buffer Full Indicator 228 * | | |0 = Receive buffer is not full. 229 * | | |1 = Receive buffer is full. 230 * |[3] |RXOVIF |Receive Buffer Over-run Error Interrupt Status 231 * | | |This bit indicates that a receive buffer overrun error event has been detected. 232 * | | |If RXOVIEN (UUART_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. 233 * | | |It is cleared by software writes 1 to this bit. 234 * | | |0 = A receive buffer overrun error event has not been detected. 235 * | | |1 = A receive buffer overrun error event has been detected. 236 * |[8] |TXEMPTY |Transmit Buffer Empty Indicator 237 * | | |0 = Transmit buffer is not empty. 238 * | | |1 = Transmit buffer is empty. 239 * |[9] |TXFULL |Transmit Buffer Full Indicator 240 * | | |0 = Transmit buffer is not full. 241 * | | |1 = Transmit buffer is full. 242 * @var UUART_T::PDMACTL 243 * Offset: 0x40 USCI PDMA Control Register 244 * --------------------------------------------------------------------------------------------------- 245 * |Bits |Field |Descriptions 246 * | :----: | :----: | :---- | 247 * |[0] |PDMARST |PDMA Reset 248 * | | |0 = No effect. 249 * | | |1 = Reset the USCI PDMA control logic. This bit will be cleared to 0 automatically. 250 * |[1] |TXPDMAEN |PDMA Transmit Channel Available 251 * | | |0 = Transmit PDMA function Disabled. 252 * | | |1 = Transmit PDMA function Enabled. 253 * |[2] |RXPDMAEN |PDMA Receive Channel Available 254 * | | |0 = Receive PDMA function Disabled. 255 * | | |1 = Receive PDMA function Enabled. 256 * |[3] |PDMAEN |PDMA Mode Enable Bit 257 * | | |0 = PDMA function Disabled. 258 * | | |1 = PDMA function Enabled. 259 * @var UUART_T::WKCTL 260 * Offset: 0x54 USCI Wake-up Control Register 261 * --------------------------------------------------------------------------------------------------- 262 * |Bits |Field |Descriptions 263 * | :----: | :----: | :---- | 264 * |[0] |WKEN |Wake-up Enable Bit 265 * | | |0 = Wake-up function Disabled. 266 * | | |1 = Wake-up function Enabled. 267 * |[2] |PDBOPT |Power Down Blocking Option 268 * | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately. 269 * | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately. 270 * @var UUART_T::WKSTS 271 * Offset: 0x58 USCI Wake-up Status Register 272 * --------------------------------------------------------------------------------------------------- 273 * |Bits |Field |Descriptions 274 * | :----: | :----: | :---- | 275 * |[0] |WKF |Wake-up Flag 276 * | | |When chip is woken up from Power-down mode, this bit is set to 1 277 * | | |Software can write 1 to clear this bit. 278 * @var UUART_T::PROTCTL 279 * Offset: 0x5C USCI Protocol Control Register 280 * --------------------------------------------------------------------------------------------------- 281 * |Bits |Field |Descriptions 282 * | :----: | :----: | :---- | 283 * |[0] |STOPB |Stop Bits 284 * | | |This bit defines the number of stop bits in an UART frame. 285 * | | |0 = The number of stop bits is 1. 286 * | | |1 = The number of stop bits is 2. 287 * |[1] |PARITYEN |Parity Enable Bit 288 * | | |This bit defines the parity bit is enabled in an UART frame. 289 * | | |0 = The parity bit Disabled. 290 * | | |1 = The parity bit Enabled. 291 * |[2] |EVENPARITY|Even Parity Enable Bit 292 * | | |0 = Odd number of logic 1's is transmitted and checked in each word. 293 * | | |1 = Even number of logic 1's is transmitted and checked in each word. 294 * | | |Note: This bit has effect only when PARITYEN is set. 295 * |[3] |RTSAUTOEN |nRTS Auto-flow Control Enable Bit 296 * | | |When nRTS auto-flow is enabled, if the receiver buffer is full (RXFULL (UUART_BUFSTS[1] = 1)), the UART will de-assert nRTS signal. 297 * | | |0 = nRTS auto-flow control Disabled. 298 * | | |1 = nRTS auto-flow control Enabled. 299 * | | |Note: This bit has effect only when the RTSAUDIREN is not set. 300 * |[4] |CTSAUTOEN |nCTS Auto-flow Control Enable Bit 301 * | | |When nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted). 302 * | | |0 = nCTS auto-flow control Disabled. 303 * | | |1 = nCTS auto-flow control Enabled. 304 * |[5] |RTSAUDIREN|nRTS Auto Direction Enable Bit 305 * | | |When nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the nRTS signal is inactive. 306 * | | |0 = nRTS auto direction control Disabled. 307 * | | |1 = nRTS auto direction control Enabled. 308 * | | |Note1: This bit is used for nRTS auto direction control for RS485. 309 * | | |Note2: This bit has effect only when the RTSAUTOEN is not set. 310 * |[6] |ABREN |Auto-baud Rate Detect Enable Bit 311 * | | |0 = Auto-baud rate detect function Disabled. 312 * | | |1 = Auto-baud rate detect function Enabled. 313 * | | |Note: When the auto - baud rate detect operation finishes, hardware will clear this bit. 314 * | | |The associated interrupt ABRDETIF (UUART_PROTSTS[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled). 315 * |[9] |DATWKEN |Data Wake-up Mode Enable Bit 316 * | | |0 = Data wake-up mode Disabled. 317 * | | |1 = Data wake-up mode Enabled. 318 * |[10] |CTSWKEN |nCTS Wake-up Mode Enable Bit 319 * | | |0 = nCTS wake-up mode Disabled. 320 * | | |1 = nCTS wake-up mode Enabled. 321 * |[14:11] |WAKECNT |Wake-up Counter 322 * | | |These bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode. 323 * |[24:16] |BRDETITV |Baud Rate Detection Interval 324 * | | |This bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits. 325 * | | |The order of the bus shall be 1 and 0 step by step (e.g 326 * | | |the input data pattern shall be 0x55) 327 * | | |The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTCTL[9]) is set. 328 * | | |Note: This bit can be cleared to 0 by software writing 1 to the BRDETITV. 329 * |[26] |STICKEN |Stick Parity Enable Bit 330 * | | |0 = Stick parity Disabled. 331 * | | |1 = Stick parity Enabled. 332 * | | |Note: Refer to RS-485 Support section for detail information. 333 * |[29] |BCEN |Transmit Break Control Enable Bit 334 * | | |0 = Transmit Break Control Disabled. 335 * | | |1 = Transmit Break Control Enabled. 336 * | | |Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). 337 * | | |This bit acts only on TX line and has no effect on the transmitter logic. 338 * |[30] |DGE |Deglitch Enable Bit 339 * | | |0 = Deglitch Disabled. 340 * | | |1 = Deglitch Enabled. 341 * | | |Note: When this bit is set to logic 1, any pulse width less than about 300 ns will be considered a glitch and will be removed in the serial data input (RX). 342 * | | |This bit acts only on RX line and has no effect on the transmitter logic. 343 * |[31] |PROTEN |UART Protocol Enable Bit 344 * | | |0 = UART Protocol Disabled. 345 * | | |1 = UART Protocol Enabled. 346 * @var UUART_T::PROTIEN 347 * Offset: 0x60 USCI Protocol Interrupt Enable Register 348 * --------------------------------------------------------------------------------------------------- 349 * |Bits |Field |Descriptions 350 * | :----: | :----: | :---- | 351 * |[1] |ABRIEN |Auto-baud Rate Interrupt Enable Bit 352 * | | |0 = Auto-baud rate interrupt Disabled. 353 * | | |1 = Auto-baud rate interrupt Enabled. 354 * |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit 355 * | | |0 = Receive line status interrupt Disabled. 356 * | | |1 = Receive line status interrupt Enabled. 357 * | | |Note: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt. 358 * @var UUART_T::PROTSTS 359 * Offset: 0x64 USCI Protocol Status Register 360 * --------------------------------------------------------------------------------------------------- 361 * |Bits |Field |Descriptions 362 * | :----: | :----: | :---- | 363 * |[1] |TXSTIF |Transmit Start Interrupt Flag 364 * | | |0 = A transmit start interrupt status has not occurred. 365 * | | |1 = A transmit start interrupt status has occurred. 366 * | | |Note1: It is cleared by software writing one into this bit. 367 * | | |Note2: Used for user to load next transmit data when there is no data in transmit buffer. 368 * |[2] |TXENDIF |Transmit End Interrupt Flag 369 * | | |0 = A transmit end interrupt status has not occurred. 370 * | | |1 = A transmit end interrupt status has occurred. 371 * | | |Note: It is cleared by software writing one into this bit. 372 * |[3] |RXSTIF |Receive Start Interrupt Flag 373 * | | |0 = A receive start interrupt status has not occurred. 374 * | | |1 = A receive start interrupt status has occurred. 375 * | | |Note: It is cleared by software writing one into this bit. 376 * |[4] |RXENDIF |Receive End Interrupt Flag 377 * | | |0 = A receive finish interrupt status has not occurred. 378 * | | |1 = A receive finish interrupt status has occurred. 379 * | | |Note: It is cleared by software writing one into this bit. 380 * |[5] |PARITYERR |Parity Error Flag 381 * | | |This bit is set to logic 1 whenever the received character does not have a valid parity bit. 382 * | | |0 = No parity error is generated. 383 * | | |1 = Parity error is generated. 384 * | | |Note: This bit can be cleared by write 1 among the BREAK, FRMERR and PARITYERR bits. 385 * |[6] |FRMERR |Framing Error Flag 386 * | | |This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). 387 * | | |0 = No framing error is generated. 388 * | | |1 = Framing error is generated. 389 * | | |Note: This bit can be cleared by write 1 among the BREAK, FRMERR and PARITYERR bits. 390 * |[7] |BREAK |Break Flag 391 * | | |This bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). 392 * | | |0 = No Break is generated. 393 * | | |1 = Break is generated in the receiver bus. 394 * | | |Note: This bit can be cleared by write 1 among the BREAK, FRMERR and PARITYERR bits. 395 * |[9] |ABRDETIF |Auto-baud Rate Interrupt Flag 396 * | | |This bit is set when auto-baud rate detection is done among the falling edge of the input data. 397 * | | |If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated. 398 * | | |This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus. 399 * | | |0 = Auto-baud rate detect function is not done. 400 * | | |1 = One Bit auto-baud rate detect function is done. 401 * | | |Note: This bit can be cleared by writing 1 to it. 402 * |[10] |RXBUSY |RX Bus Status Flag (Read Only) 403 * | | |This bit indicates the busy status of the receiver. 404 * | | |0 = The receiver is Idle. 405 * | | |1 = The receiver is BUSY. 406 * |[11] |ABERRSTS |Auto-baud Rate Error Status 407 * | | |This bit is set when auto-baud rate detection counter overrun. 408 * | | |When the auto-baud rate counter overrun, the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the correct baud rate again. 409 * | | |0 = Auto-baud rate detect counter is not overrun. 410 * | | |1 = Auto-baud rate detect counter is overrun. 411 * | | |Note1: This bit is set at the same time of ABRDETIF. 412 * | | |Note2: This bit can be cleared by writing 1 to ABRDETIF or ABERRSTS. 413 * |[16] |CTSSYNCLV |nCTS Synchronized Level Status (Read Only) 414 * | | |This bit used to indicate the current status of the internal synchronized nCTS signal. 415 * | | |0 = The internal synchronized nCTS is low. 416 * | | |1 = The internal synchronized nCTS is high. 417 * |[17] |CTSLV |nCTS Pin Status (Read Only) 418 * | | |This bit used to monitor the current status of nCTS pin input. 419 * | | |0 = nCTS pin input is low level voltage logic state. 420 * | | |1 = nCTS pin input is high level voltage logic state. 421 */ 422 423 __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */ 424 __IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */ 425 __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */ 426 __I uint32_t RESERVE0[1]; 427 __IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */ 428 __I uint32_t RESERVE1[3]; 429 __IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */ 430 __I uint32_t RESERVE2[1]; 431 __IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */ 432 __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */ 433 __O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */ 434 __I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */ 435 __IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */ 436 __IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */ 437 __IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */ 438 __I uint32_t RESERVE3[4]; 439 __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */ 440 __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */ 441 __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */ 442 __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */ 443 __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */ 444 445 } UUART_T; 446 447 /** 448 @addtogroup UUART_CONST UUART Bit Field Definition 449 Constant Definitions for UUART Controller 450 @{ 451 */ 452 453 #define UUART_CTL_FUNMODE_Pos (0) /*!< UUART_T::CTL: FUNMODE Position */ 454 #define UUART_CTL_FUNMODE_Msk (0x7ul << UUART_CTL_FUNMODE_Pos) /*!< UUART_T::CTL: FUNMODE Mask */ 455 456 #define UUART_INTEN_TXSTIEN_Pos (1) /*!< UUART_T::INTEN: TXSTIEN Position */ 457 #define UUART_INTEN_TXSTIEN_Msk (0x1ul << UUART_INTEN_TXSTIEN_Pos) /*!< UUART_T::INTEN: TXSTIEN Mask */ 458 459 #define UUART_INTEN_TXENDIEN_Pos (2) /*!< UUART_T::INTEN: TXENDIEN Position */ 460 #define UUART_INTEN_TXENDIEN_Msk (0x1ul << UUART_INTEN_TXENDIEN_Pos) /*!< UUART_T::INTEN: TXENDIEN Mask */ 461 462 #define UUART_INTEN_RXSTIEN_Pos (3) /*!< UUART_T::INTEN: RXSTIEN Position */ 463 #define UUART_INTEN_RXSTIEN_Msk (0x1ul << UUART_INTEN_RXSTIEN_Pos) /*!< UUART_T::INTEN: RXSTIEN Mask */ 464 465 #define UUART_INTEN_RXENDIEN_Pos (4) /*!< UUART_T::INTEN: RXENDIEN Position */ 466 #define UUART_INTEN_RXENDIEN_Msk (0x1ul << UUART_INTEN_RXENDIEN_Pos) /*!< UUART_T::INTEN: RXENDIEN Mask */ 467 468 #define UUART_BRGEN_RCLKSEL_Pos (0) /*!< UUART_T::BRGEN: RCLKSEL Position */ 469 #define UUART_BRGEN_RCLKSEL_Msk (0x1ul << UUART_BRGEN_RCLKSEL_Pos) /*!< UUART_T::BRGEN: RCLKSEL Mask */ 470 471 #define UUART_BRGEN_PTCLKSEL_Pos (1) /*!< UUART_T::BRGEN: PTCLKSEL Position */ 472 #define UUART_BRGEN_PTCLKSEL_Msk (0x1ul << UUART_BRGEN_PTCLKSEL_Pos) /*!< UUART_T::BRGEN: PTCLKSEL Mask */ 473 474 #define UUART_BRGEN_SPCLKSEL_Pos (2) /*!< UUART_T::BRGEN: SPCLKSEL Position */ 475 #define UUART_BRGEN_SPCLKSEL_Msk (0x3ul << UUART_BRGEN_SPCLKSEL_Pos) /*!< UUART_T::BRGEN: SPCLKSEL Mask */ 476 477 #define UUART_BRGEN_TMCNTEN_Pos (4) /*!< UUART_T::BRGEN: TMCNTEN Position */ 478 #define UUART_BRGEN_TMCNTEN_Msk (0x1ul << UUART_BRGEN_TMCNTEN_Pos) /*!< UUART_T::BRGEN: TMCNTEN Mask */ 479 480 #define UUART_BRGEN_TMCNTSRC_Pos (5) /*!< UUART_T::BRGEN: TMCNTSRC Position */ 481 #define UUART_BRGEN_TMCNTSRC_Msk (0x1ul << UUART_BRGEN_TMCNTSRC_Pos) /*!< UUART_T::BRGEN: TMCNTSRC Mask */ 482 483 #define UUART_BRGEN_PDSCNT_Pos (8) /*!< UUART_T::BRGEN: PDSCNT Position */ 484 #define UUART_BRGEN_PDSCNT_Msk (0x3ul << UUART_BRGEN_PDSCNT_Pos) /*!< UUART_T::BRGEN: PDSCNT Mask */ 485 486 #define UUART_BRGEN_DSCNT_Pos (10) /*!< UUART_T::BRGEN: DSCNT Position */ 487 #define UUART_BRGEN_DSCNT_Msk (0x1ful << UUART_BRGEN_DSCNT_Pos) /*!< UUART_T::BRGEN: DSCNT Mask */ 488 489 #define UUART_BRGEN_CLKDIV_Pos (16) /*!< UUART_T::BRGEN: CLKDIV Position */ 490 #define UUART_BRGEN_CLKDIV_Msk (0x3fful << UUART_BRGEN_CLKDIV_Pos) /*!< UUART_T::BRGEN: CLKDIV Mask */ 491 492 #define UUART_DATIN0_SYNCSEL_Pos (0) /*!< UUART_T::DATIN0: SYNCSEL Position */ 493 #define UUART_DATIN0_SYNCSEL_Msk (0x1ul << UUART_DATIN0_SYNCSEL_Pos) /*!< UUART_T::DATIN0: SYNCSEL Mask */ 494 495 #define UUART_DATIN0_ININV_Pos (2) /*!< UUART_T::DATIN0: ININV Position */ 496 #define UUART_DATIN0_ININV_Msk (0x1ul << UUART_DATIN0_ININV_Pos) /*!< UUART_T::DATIN0: ININV Mask */ 497 498 #define UUART_DATIN0_EDGEDET_Pos (3) /*!< UUART_T::DATIN0: EDGEDET Position */ 499 #define UUART_DATIN0_EDGEDET_Msk (0x3ul << UUART_DATIN0_EDGEDET_Pos) /*!< UUART_T::DATIN0: EDGEDET Mask */ 500 501 #define UUART_CTLIN0_SYNCSEL_Pos (0) /*!< UUART_T::CTLIN0: SYNCSEL Position */ 502 #define UUART_CTLIN0_SYNCSEL_Msk (0x1ul << UUART_CTLIN0_SYNCSEL_Pos) /*!< UUART_T::CTLIN0: SYNCSEL Mask */ 503 504 #define UUART_CTLIN0_ININV_Pos (2) /*!< UUART_T::CTLIN0: ININV Position */ 505 #define UUART_CTLIN0_ININV_Msk (0x1ul << UUART_CTLIN0_ININV_Pos) /*!< UUART_T::CTLIN0: ININV Mask */ 506 507 #define UUART_CLKIN_SYNCSEL_Pos (0) /*!< UUART_T::CLKIN: SYNCSEL Position */ 508 #define UUART_CLKIN_SYNCSEL_Msk (0x1ul << UUART_CLKIN_SYNCSEL_Pos) /*!< UUART_T::CLKIN: SYNCSEL Mask */ 509 510 #define UUART_LINECTL_LSB_Pos (0) /*!< UUART_T::LINECTL: LSB Position */ 511 #define UUART_LINECTL_LSB_Msk (0x1ul << UUART_LINECTL_LSB_Pos) /*!< UUART_T::LINECTL: LSB Mask */ 512 513 #define UUART_LINECTL_DATOINV_Pos (5) /*!< UUART_T::LINECTL: DATOINV Position */ 514 #define UUART_LINECTL_DATOINV_Msk (0x1ul << UUART_LINECTL_DATOINV_Pos) /*!< UUART_T::LINECTL: DATOINV Mask */ 515 516 #define UUART_LINECTL_CTLOINV_Pos (7) /*!< UUART_T::LINECTL: CTLOINV Position */ 517 #define UUART_LINECTL_CTLOINV_Msk (0x1ul << UUART_LINECTL_CTLOINV_Pos) /*!< UUART_T::LINECTL: CTLOINV Mask */ 518 519 #define UUART_LINECTL_DWIDTH_Pos (8) /*!< UUART_T::LINECTL: DWIDTH Position */ 520 #define UUART_LINECTL_DWIDTH_Msk (0xful << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_T::LINECTL: DWIDTH Mask */ 521 522 #define UUART_TXDAT_TXDAT_Pos (0) /*!< UUART_T::TXDAT: TXDAT Position */ 523 #define UUART_TXDAT_TXDAT_Msk (0xfffful << UUART_TXDAT_TXDAT_Pos) /*!< UUART_T::TXDAT: TXDAT Mask */ 524 525 #define UUART_RXDAT_RXDAT_Pos (0) /*!< UUART_T::RXDAT: RXDAT Position */ 526 #define UUART_RXDAT_RXDAT_Msk (0xfffful << UUART_RXDAT_RXDAT_Pos) /*!< UUART_T::RXDAT: RXDAT Mask */ 527 528 #define UUART_BUFCTL_TXCLR_Pos (7) /*!< UUART_T::BUFCTL: TXCLR Position */ 529 #define UUART_BUFCTL_TXCLR_Msk (0x1ul << UUART_BUFCTL_TXCLR_Pos) /*!< UUART_T::BUFCTL: TXCLR Mask */ 530 531 #define UUART_BUFCTL_RXOVIEN_Pos (14) /*!< UUART_T::BUFCTL: RXOVIEN Position */ 532 #define UUART_BUFCTL_RXOVIEN_Msk (0x1ul << UUART_BUFCTL_RXOVIEN_Pos) /*!< UUART_T::BUFCTL: RXOVIEN Mask */ 533 534 #define UUART_BUFCTL_RXCLR_Pos (15) /*!< UUART_T::BUFCTL: RXCLR Position */ 535 #define UUART_BUFCTL_RXCLR_Msk (0x1ul << UUART_BUFCTL_RXCLR_Pos) /*!< UUART_T::BUFCTL: RXCLR Mask */ 536 537 #define UUART_BUFCTL_TXRST_Pos (16) /*!< UUART_T::BUFCTL: TXRST Position */ 538 #define UUART_BUFCTL_TXRST_Msk (0x1ul << UUART_BUFCTL_TXRST_Pos) /*!< UUART_T::BUFCTL: TXRST Mask */ 539 540 #define UUART_BUFCTL_RXRST_Pos (17) /*!< UUART_T::BUFCTL: RXRST Position */ 541 #define UUART_BUFCTL_RXRST_Msk (0x1ul << UUART_BUFCTL_RXRST_Pos) /*!< UUART_T::BUFCTL: RXRST Mask */ 542 543 #define UUART_BUFSTS_RXEMPTY_Pos (0) /*!< UUART_T::BUFSTS: RXEMPTY Position */ 544 #define UUART_BUFSTS_RXEMPTY_Msk (0x1ul << UUART_BUFSTS_RXEMPTY_Pos) /*!< UUART_T::BUFSTS: RXEMPTY Mask */ 545 546 #define UUART_BUFSTS_RXFULL_Pos (1) /*!< UUART_T::BUFSTS: RXFULL Position */ 547 #define UUART_BUFSTS_RXFULL_Msk (0x1ul << UUART_BUFSTS_RXFULL_Pos) /*!< UUART_T::BUFSTS: RXFULL Mask */ 548 549 #define UUART_BUFSTS_RXOVIF_Pos (3) /*!< UUART_T::BUFSTS: RXOVIF Position */ 550 #define UUART_BUFSTS_RXOVIF_Msk (0x1ul << UUART_BUFSTS_RXOVIF_Pos) /*!< UUART_T::BUFSTS: RXOVIF Mask */ 551 552 #define UUART_BUFSTS_TXEMPTY_Pos (8) /*!< UUART_T::BUFSTS: TXEMPTY Position */ 553 #define UUART_BUFSTS_TXEMPTY_Msk (0x1ul << UUART_BUFSTS_TXEMPTY_Pos) /*!< UUART_T::BUFSTS: TXEMPTY Mask */ 554 555 #define UUART_BUFSTS_TXFULL_Pos (9) /*!< UUART_T::BUFSTS: TXFULL Position */ 556 #define UUART_BUFSTS_TXFULL_Msk (0x1ul << UUART_BUFSTS_TXFULL_Pos) /*!< UUART_T::BUFSTS: TXFULL Mask */ 557 558 #define UUART_PDMACTL_PDMARST_Pos (0) /*!< UUART_T::PDMACTL: PDMARST Position */ 559 #define UUART_PDMACTL_PDMARST_Msk (0x1ul << UUART_PDMACTL_PDMARST_Pos) /*!< UUART_T::PDMACTL: PDMARST Mask */ 560 561 #define UUART_PDMACTL_TXPDMAEN_Pos (1) /*!< UUART_T::PDMACTL: TXPDMAEN Position */ 562 #define UUART_PDMACTL_TXPDMAEN_Msk (0x1ul << UUART_PDMACTL_TXPDMAEN_Pos) /*!< UUART_T::PDMACTL: TXPDMAEN Mask */ 563 564 #define UUART_PDMACTL_RXPDMAEN_Pos (2) /*!< UUART_T::PDMACTL: RXPDMAEN Position */ 565 #define UUART_PDMACTL_RXPDMAEN_Msk (0x1ul << UUART_PDMACTL_RXPDMAEN_Pos) /*!< UUART_T::PDMACTL: RXPDMAEN Mask */ 566 567 #define UUART_PDMACTL_PDMAEN_Pos (3) /*!< UUART_T::PDMACTL: PDMAEN Position */ 568 #define UUART_PDMACTL_PDMAEN_Msk (0x1ul << UUART_PDMACTL_PDMAEN_Pos) /*!< UUART_T::PDMACTL: PDMAEN Mask */ 569 570 #define UUART_WKCTL_WKEN_Pos (0) /*!< UUART_T::WKCTL: WKEN Position */ 571 #define UUART_WKCTL_WKEN_Msk (0x1ul << UUART_WKCTL_WKEN_Pos) /*!< UUART_T::WKCTL: WKEN Mask */ 572 573 #define UUART_WKCTL_PDBOPT_Pos (2) /*!< UUART_T::WKCTL: PDBOPT Position */ 574 #define UUART_WKCTL_PDBOPT_Msk (0x1ul << UUART_WKCTL_PDBOPT_Pos) /*!< UUART_T::WKCTL: PDBOPT Mask */ 575 576 #define UUART_WKSTS_WKF_Pos (0) /*!< UUART_T::WKSTS: WKF Position */ 577 #define UUART_WKSTS_WKF_Msk (0x1ul << UUART_WKSTS_WKF_Pos) /*!< UUART_T::WKSTS: WKF Mask */ 578 579 #define UUART_PROTCTL_STOPB_Pos (0) /*!< UUART_T::PROTCTL: STOPB Position */ 580 #define UUART_PROTCTL_STOPB_Msk (0x1ul << UUART_PROTCTL_STOPB_Pos) /*!< UUART_T::PROTCTL: STOPB Mask */ 581 582 #define UUART_PROTCTL_PARITYEN_Pos (1) /*!< UUART_T::PROTCTL: PARITYEN Position */ 583 #define UUART_PROTCTL_PARITYEN_Msk (0x1ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_T::PROTCTL: PARITYEN Mask */ 584 585 #define UUART_PROTCTL_EVENPARITY_Pos (2) /*!< UUART_T::PROTCTL: EVENPARITY Position */ 586 #define UUART_PROTCTL_EVENPARITY_Msk (0x1ul << UUART_PROTCTL_EVENPARITY_Pos) /*!< UUART_T::PROTCTL: EVENPARITY Mask */ 587 588 #define UUART_PROTCTL_RTSAUTOEN_Pos (3) /*!< UUART_T::PROTCTL: RTSAUTOEN Position */ 589 #define UUART_PROTCTL_RTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_RTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: RTSAUTOEN Mask */ 590 591 #define UUART_PROTCTL_CTSAUTOEN_Pos (4) /*!< UUART_T::PROTCTL: CTSAUTOEN Position */ 592 #define UUART_PROTCTL_CTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_CTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: CTSAUTOEN Mask */ 593 594 #define UUART_PROTCTL_RTSAUDIREN_Pos (5) /*!< UUART_T::PROTCTL: RTSAUDIREN Position */ 595 #define UUART_PROTCTL_RTSAUDIREN_Msk (0x1ul << UUART_PROTCTL_RTSAUDIREN_Pos) /*!< UUART_T::PROTCTL: RTSAUDIREN Mask */ 596 597 #define UUART_PROTCTL_ABREN_Pos (6) /*!< UUART_T::PROTCTL: ABREN Position */ 598 #define UUART_PROTCTL_ABREN_Msk (0x1ul << UUART_PROTCTL_ABREN_Pos) /*!< UUART_T::PROTCTL: ABREN Mask */ 599 600 #define UUART_PROTCTL_DATWKEN_Pos (9) /*!< UUART_T::PROTCTL: DATWKEN Position */ 601 #define UUART_PROTCTL_DATWKEN_Msk (0x1ul << UUART_PROTCTL_DATWKEN_Pos) /*!< UUART_T::PROTCTL: DATWKEN Mask */ 602 603 #define UUART_PROTCTL_CTSWKEN_Pos (10) /*!< UUART_T::PROTCTL: CTSWKEN Position */ 604 #define UUART_PROTCTL_CTSWKEN_Msk (0x1ul << UUART_PROTCTL_CTSWKEN_Pos) /*!< UUART_T::PROTCTL: CTSWKEN Mask */ 605 606 #define UUART_PROTCTL_WAKECNT_Pos (11) /*!< UUART_T::PROTCTL: WAKECNT Position */ 607 #define UUART_PROTCTL_WAKECNT_Msk (0xful << UUART_PROTCTL_WAKECNT_Pos) /*!< UUART_T::PROTCTL: WAKECNT Mask */ 608 609 #define UUART_PROTCTL_BRDETITV_Pos (16) /*!< UUART_T::PROTCTL: BRDETITV Position */ 610 #define UUART_PROTCTL_BRDETITV_Msk (0x1fful << UUART_PROTCTL_BRDETITV_Pos) /*!< UUART_T::PROTCTL: BRDETITV Mask */ 611 612 #define UUART_PROTCTL_STICKEN_Pos (26) /*!< UUART_T::PROTCTL: STICKEN Position */ 613 #define UUART_PROTCTL_STICKEN_Msk (0x1ul << UUART_PROTCTL_STICKEN_Pos) /*!< UUART_T::PROTCTL: STICKEN Mask */ 614 615 #define UUART_PROTCTL_BCEN_Pos (29) /*!< UUART_T::PROTCTL: BCEN Position */ 616 #define UUART_PROTCTL_BCEN_Msk (0x1ul << UUART_PROTCTL_BCEN_Pos) /*!< UUART_T::PROTCTL: BCEN Mask */ 617 618 #define UUART_PROTCTL_DGE_Pos (30) /*!< UUART_T::PROTCTL: DGE Position */ 619 #define UUART_PROTCTL_DGE_Msk (0x1ul << UUART_PROTCTL_DGE_Pos) /*!< UUART_T::PROTCTL: DGE Mask */ 620 621 #define UUART_PROTCTL_PROTEN_Pos (31) /*!< UUART_T::PROTCTL: PROTEN Position */ 622 #define UUART_PROTCTL_PROTEN_Msk (0x1ul << UUART_PROTCTL_PROTEN_Pos) /*!< UUART_T::PROTCTL: PROTEN Mask */ 623 624 #define UUART_PROTIEN_ABRIEN_Pos (1) /*!< UUART_T::PROTIEN: ABRIEN Position */ 625 #define UUART_PROTIEN_ABRIEN_Msk (0x1ul << UUART_PROTIEN_ABRIEN_Pos) /*!< UUART_T::PROTIEN: ABRIEN Mask */ 626 627 #define UUART_PROTIEN_RLSIEN_Pos (2) /*!< UUART_T::PROTIEN: RLSIEN Position */ 628 #define UUART_PROTIEN_RLSIEN_Msk (0x1ul << UUART_PROTIEN_RLSIEN_Pos) /*!< UUART_T::PROTIEN: RLSIEN Mask */ 629 630 #define UUART_PROTSTS_TXSTIF_Pos (1) /*!< UUART_T::PROTSTS: TXSTIF Position */ 631 #define UUART_PROTSTS_TXSTIF_Msk (0x1ul << UUART_PROTSTS_TXSTIF_Pos) /*!< UUART_T::PROTSTS: TXSTIF Mask */ 632 633 #define UUART_PROTSTS_TXENDIF_Pos (2) /*!< UUART_T::PROTSTS: TXENDIF Position */ 634 #define UUART_PROTSTS_TXENDIF_Msk (0x1ul << UUART_PROTSTS_TXENDIF_Pos) /*!< UUART_T::PROTSTS: TXENDIF Mask */ 635 636 #define UUART_PROTSTS_RXSTIF_Pos (3) /*!< UUART_T::PROTSTS: RXSTIF Position */ 637 #define UUART_PROTSTS_RXSTIF_Msk (0x1ul << UUART_PROTSTS_RXSTIF_Pos) /*!< UUART_T::PROTSTS: RXSTIF Mask */ 638 639 #define UUART_PROTSTS_RXENDIF_Pos (4) /*!< UUART_T::PROTSTS: RXENDIF Position */ 640 #define UUART_PROTSTS_RXENDIF_Msk (0x1ul << UUART_PROTSTS_RXENDIF_Pos) /*!< UUART_T::PROTSTS: RXENDIF Mask */ 641 642 #define UUART_PROTSTS_PARITYERR_Pos (5) /*!< UUART_T::PROTSTS: PARITYERR Position */ 643 #define UUART_PROTSTS_PARITYERR_Msk (0x1ul << UUART_PROTSTS_PARITYERR_Pos) /*!< UUART_T::PROTSTS: PARITYERR Mask */ 644 645 #define UUART_PROTSTS_FRMERR_Pos (6) /*!< UUART_T::PROTSTS: FRMERR Position */ 646 #define UUART_PROTSTS_FRMERR_Msk (0x1ul << UUART_PROTSTS_FRMERR_Pos) /*!< UUART_T::PROTSTS: FRMERR Mask */ 647 648 #define UUART_PROTSTS_BREAK_Pos (7) /*!< UUART_T::PROTSTS: BREAK Position */ 649 #define UUART_PROTSTS_BREAK_Msk (0x1ul << UUART_PROTSTS_BREAK_Pos) /*!< UUART_T::PROTSTS: BREAK Mask */ 650 651 #define UUART_PROTSTS_ABRDETIF_Pos (9) /*!< UUART_T::PROTSTS: ABRDETIF Position */ 652 #define UUART_PROTSTS_ABRDETIF_Msk (0x1ul << UUART_PROTSTS_ABRDETIF_Pos) /*!< UUART_T::PROTSTS: ABRDETIF Mask */ 653 654 #define UUART_PROTSTS_RXBUSY_Pos (10) /*!< UUART_T::PROTSTS: RXBUSY Position */ 655 #define UUART_PROTSTS_RXBUSY_Msk (0x1ul << UUART_PROTSTS_RXBUSY_Pos) /*!< UUART_T::PROTSTS: RXBUSY Mask */ 656 657 #define UUART_PROTSTS_ABERRSTS_Pos (11) /*!< UUART_T::PROTSTS: ABERRSTS Position */ 658 #define UUART_PROTSTS_ABERRSTS_Msk (0x1ul << UUART_PROTSTS_ABERRSTS_Pos) /*!< UUART_T::PROTSTS: ABERRSTS Mask */ 659 660 #define UUART_PROTSTS_CTSSYNCLV_Pos (16) /*!< UUART_T::PROTSTS: CTSSYNCLV Position */ 661 #define UUART_PROTSTS_CTSSYNCLV_Msk (0x1ul << UUART_PROTSTS_CTSSYNCLV_Pos) /*!< UUART_T::PROTSTS: CTSSYNCLV Mask */ 662 663 #define UUART_PROTSTS_CTSLV_Pos (17) /*!< UUART_T::PROTSTS: CTSLV Position */ 664 #define UUART_PROTSTS_CTSLV_Msk (0x1ul << UUART_PROTSTS_CTSLV_Pos) /*!< UUART_T::PROTSTS: CTSLV Mask */ 665 666 /**@}*/ /* UUART_CONST */ 667 /**@}*/ /* end of UUART register group */ 668 /**@}*/ /* end of REGISTER group */ 669 670 #endif /* __UUART_REG_H__ */ 671
