1 /**************************************************************************//** 2 * @file sdh_reg.h 3 * @version V1.00 4 * @brief SDH register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __SDH_REG_H__ 10 #define __SDH_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 /*---------------------- SD Card Host Interface -------------------------*/ 19 /** 20 @addtogroup SDH SD Card Host Interface(SDH) 21 Memory Mapped Structure for SDH Controller 22 @{ 23 */ 24 25 typedef struct 26 { 27 28 /** 29 * @var SDH_T::FB 30 * Offset: 0x00~0x7C Shared Buffer (FIFO) 31 * --------------------------------------------------------------------------------------------------- 32 * |Bits |Field |Descriptions 33 * | :----: | :----: | :---- | 34 * |[31:0] |BUFFER |Shared Buffer 35 * | | |Buffer for DMA transfer 36 * @var SDH_T::DMACTL 37 * Offset: 0x400 DMA Control and Status Register 38 * --------------------------------------------------------------------------------------------------- 39 * |Bits |Field |Descriptions 40 * | :----: | :----: | :---- | 41 * |[0] |DMAEN |DMA Engine Enable Bit 42 * | | |If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state. 43 * | | |0 = DMA Disabled. 44 * | | |1 = DMA Enabled. 45 * | | |Note: If target abort is occurred, DMAEN will be cleared. 46 * |[1] |DMARST |Software Engine Reset 47 * | | |0 = No effect. 48 * | | |1 = Reset internal state machine and pointers 49 * | | |The contents of control register will not be cleared 50 * | | |This bit will auto be cleared after few clock cycles. 51 * | | |Note: The software reset DMA related registers. 52 * |[3] |SGEN |Scatter-gather Function Enable Bit 53 * | | |0 = Scatter-gather function Disabled (DMA will treat the starting address in DMASAR as starting pointer of a single block memory). 54 * | | |1 = Scatter-gather function Enabled (DMA will treat the starting address in DMASAR as a starting address of Physical Address Descriptor (PAD) table 55 * | | |The format of these Pads' will be described later). 56 * |[9] |DMABUSY |DMA Transfer Is in Progress 57 * | | |This bit indicates if SD Host is granted and doing DMA transfer or not. 58 * | | |0 = DMA transfer is not in progress. 59 * | | |1 = DMA transfer is in progress. 60 * @var SDH_T::DMASA 61 * Offset: 0x408 DMA Transfer Starting Address Register 62 * --------------------------------------------------------------------------------------------------- 63 * |Bits |Field |Descriptions 64 * | :----: | :----: | :---- | 65 * |[0] |ORDER |Determined to the PAD Table Fetching Is in Order or Out of Order 66 * | | |0 = PAD table is fetched in order. 67 * | | |1 = PAD table is fetched out of order. 68 * | | |Note: the bit0 is valid in scatter-gather mode when SGEN = 1. 69 * |[31:1] |DMASA |DMA Transfer Starting Address 70 * | | |This field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMA to retrieve or fill in data. 71 * | | |If DMA is not in normal mode, this field will be interpreted as a starting address of Physical Address Descriptor (PAD) table. 72 * | | |Note: Starting address of the SRAM must be word aligned, for example, 0x0000_0000, 0x0000_0004. 73 * @var SDH_T::DMABCNT 74 * Offset: 0x40C DMA Transfer Byte Count Register 75 * --------------------------------------------------------------------------------------------------- 76 * |Bits |Field |Descriptions 77 * | :----: | :----: | :---- | 78 * |[25:0] |BCNT |DMA Transfer Byte Count (Read Only) 79 * | | |This field indicates the remained byte count of DMA transfer 80 * | | |The value of this field is valid only when DMA is busy; otherwise, it is 0. 81 * @var SDH_T::DMAINTEN 82 * Offset: 0x410 DMA Interrupt Enable Control Register 83 * --------------------------------------------------------------------------------------------------- 84 * |Bits |Field |Descriptions 85 * | :----: | :----: | :---- | 86 * |[0] |ABORTIEN |DMA Read/Write Target Abort Interrupt Enable Bit 87 * | | |0 = Target abort interrupt generation Disabled during DMA transfer. 88 * | | |1 = Target abort interrupt generation Enabled during DMA transfer. 89 * |[1] |WEOTIEN |Wrong EOT Encountered Interrupt Enable Bit 90 * | | |0 = Interrupt generation Disabled when wrong EOT is encountered. 91 * | | |1 = Interrupt generation Enabled when wrong EOT is encountered. 92 * @var SDH_T::DMAINTSTS 93 * Offset: 0x414 DMA Interrupt Status Register 94 * --------------------------------------------------------------------------------------------------- 95 * |Bits |Field |Descriptions 96 * | :----: | :----: | :---- | 97 * |[0] |ABORTIF |DMA Read/Write Target Abort Interrupt Flag 98 * | | |0 = No bus ERROR response received. 99 * | | |1 = Bus ERROR response received. 100 * | | |Note1: This bit is read only, but can be cleared by writing '1' to it. 101 * | | |Note2: When DMA's bus master received ERROR response, it means that target abort is happened 102 * | | |DMA will stop transfer and respond this event and then go to IDLE state 103 * | | |When target abort occurred or WEOTIF is set, software must reset DMA and SD host, and then transfer those data again. 104 * |[1] |WEOTIF |Wrong EOT Encountered Interrupt Flag 105 * | | |When DMA Scatter-Gather function is enabled, and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of SD host), this bit will be set. 106 * | | |0 = No EOT encountered before DMA transfer finished. 107 * | | |1 = EOT encountered before DMA transfer finished. 108 * | | |Note: This bit is read only, but can be cleared by writing '1' to it. 109 * @var SDH_T::GCTL 110 * Offset: 0x800 Global Control and Status Register 111 * --------------------------------------------------------------------------------------------------- 112 * |Bits |Field |Descriptions 113 * | :----: | :----: | :---- | 114 * |[0] |GCTLRST |Software Engine Reset 115 * | | |0 = No effect. 116 * | | |1 = Reset SD host 117 * | | |The contents of control register will not be cleared 118 * | | |This bit will auto cleared after reset complete. 119 * |[1] |SDEN |Secure Digital Functionality Enable Bit 120 * | | |0 = SD functionality disabled. 121 * | | |1 = SD functionality enabled. 122 * @var SDH_T::GINTEN 123 * Offset: 0x804 Global Interrupt Control Register 124 * --------------------------------------------------------------------------------------------------- 125 * |Bits |Field |Descriptions 126 * | :----: | :----: | :---- | 127 * |[0] |DTAIEN |DMA READ/WRITE Target Abort Interrupt Enable Bit 128 * | | |0 = DMA READ/WRITE target abort interrupt generation disabled. 129 * | | |1 = DMA READ/WRITE target abort interrupt generation enabled. 130 * @var SDH_T::GINTSTS 131 * Offset: 0x808 Global Interrupt Status Register 132 * --------------------------------------------------------------------------------------------------- 133 * |Bits |Field |Descriptions 134 * | :----: | :----: | :---- | 135 * |[0] |DTAIF |DMA READ/WRITE Target Abort Interrupt Flag (Read Only) 136 * | | |This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation 137 * | | |When Target Abort is occurred, please reset all engine. 138 * | | |0 = No bus ERROR response received. 139 * | | |1 = Bus ERROR response received. 140 * | | |Note: This bit is read only, but can be cleared by writing '1' to it. 141 * @var SDH_T::CTL 142 * Offset: 0x820 SD Control and Status Register 143 * --------------------------------------------------------------------------------------------------- 144 * |Bits |Field |Descriptions 145 * | :----: | :----: | :---- | 146 * |[0] |COEN |Command Output Enable Bit 147 * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) 148 * | | |1 = Enabled, SD host will output a command to SD card. 149 * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). 150 * |[1] |RIEN |Response Input Enable Bit 151 * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) 152 * | | |1 = Enabled, SD host will wait to receive a response from SD card. 153 * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). 154 * |[2] |DIEN |Data Input Enable Bit 155 * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) 156 * | | |1 = Enabled, SD host will wait to receive block data and the CRC16 value from SD card. 157 * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). 158 * |[3] |DOEN |Data Output Enable Bit 159 * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) 160 * | | |1 = Enabled, SD host will transfer block data and the CRC16 value to SD card. 161 * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). 162 * |[4] |R2EN |Response R2 Input Enable Bit 163 * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) 164 * | | |1 = Enabled, SD host will wait to receive a response R2 from SD card and store the response data into DMC's flash buffer (exclude CRC7). 165 * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). 166 * |[5] |CLK74OEN |Initial 74 Clock Cycles Output Enable Bit 167 * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) 168 * | | |1 = Enabled, SD host will output 74 clock cycles to SD card. 169 * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). 170 * |[6] |CLK8OEN |Generating 8 Clock Cycles Output Enable Bit 171 * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) 172 * | | |1 = Enabled, SD host will output 8 clock cycles. 173 * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). 174 * |[7] |CLKKEEP0 |SD Clock Enable Control for Port 0 175 * | | |0 = SD host decided when to output clock and when to disable clock output automatically. 176 * | | |1 = SD clock always keeps free running. 177 * |[13:8] |CMDCODE |SD Command Code 178 * | | |This register contains the SD command code (0x00 ~ 0x3F). 179 * |[14] |CTLRST |Software Engine Reset 180 * | | |0 = No effect. 181 * | | |1 = Reset the internal state machine and counters 182 * | | |The contents of control register will not be cleared (but RIEN, DIEN, DOEN and R2EN will be cleared) 183 * | | |This bit will be auto cleared after few clock cycles. 184 * |[15] |DBW |SD Data Bus Width (for 1-bit / 4-bit Selection) 185 * | | |0 = Data bus width is 1-bit. 186 * | | |1 = Data bus width is 4-bit. 187 * |[23:16] |BLKCNT |Block Counts to Be Transferred or Received 188 * | | |This field contains the block counts for data-in and data-out transfer 189 * | | |For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, software can use this function to accelerate data transfer and improve performance 190 * | | |Don't fill 0x0 to this field. 191 * | | |Note: For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, the actual total length is BLKCNT * (BLKLEN +1). 192 * |[27:24] |SDNWR |NWR Parameter for Block Write Operation 193 * | | |This value indicates the NWR parameter for data block write operation in SD clock counts 194 * | | |The actual clock cycle will be SDNWR+1. 195 * @var SDH_T::CMDARG 196 * Offset: 0x824 SD Command Argument Register 197 * --------------------------------------------------------------------------------------------------- 198 * |Bits |Field |Descriptions 199 * | :----: | :----: | :---- | 200 * |[31:0] |ARGUMENT |SD Command Argument 201 * | | |This register contains a 32-bit value specifies the argument of SD command from host controller to SD card 202 * | | |Before trigger COEN (SDH_CTL [0]), software should fill argument in this field. 203 * @var SDH_T::INTEN 204 * Offset: 0x828 SD Interrupt Control Register 205 * --------------------------------------------------------------------------------------------------- 206 * |Bits |Field |Descriptions 207 * | :----: | :----: | :---- | 208 * |[0] |BLKDIEN |Block Transfer Done Interrupt Enable Bit 209 * | | |0 = SD host will not generate interrupt when data-in (out) transfer done. 210 * | | |1 = SD host will generate interrupt when data-in (out) transfer done. 211 * |[1] |CRCIEN |CRC7, CRC16 and CRC Status Error Interrupt Enable Bit 212 * | | |0 = SD host will not generate interrupt when CRC7, CRC16 and CRC status is error. 213 * | | |1 = SD host will generate interrupt when CRC7, CRC16 and CRC status is error. 214 * |[8] |CDIEN0 |SD0 Card Detection Interrupt Enable Bit 215 * | | |Enable/Disable interrupts generation of SD controller when card 0 is inserted or removed. 216 * | | |0 = SD card detection interrupt Disabled. 217 * | | |1 = SD card detection interrupt Enabled. 218 * |[12] |RTOIEN |Response Time-out Interrupt Enable Bit 219 * | | |Enable/Disable interrupts generation of SD controller when receiving response or R2 time-out 220 * | | |Time-out value is specified at TOUT register. 221 * | | |0 = Response time-out interrupt Disabled. 222 * | | |1 = Response time-out interrupt Enabled. 223 * |[13] |DITOIEN |Data Input Time-out Interrupt Enable Bit 224 * | | |Enable/Disable interrupts generation of SD controller when data input time-out 225 * | | |Time-out value is specified at TOUT register. 226 * | | |0 = Data input time-out interrupt Disabled. 227 * | | |1 = Data input time-out interrupt Enabled. 228 * |[14] |WKIEN |Wake-up Signal Generating Enable Bit 229 * | | |Enable/Disable wake-up signal generating of SD host when current using SD card issues an interrupt (wake-up) via DAT [1] to host. 230 * | | |0 = Wake-up signal generating Disabled. 231 * | | |1 = Wake-up signal generating Enabled. 232 * |[30] |CDSRC0 |SD0 Card Detect Source Selection 233 * | | |0 = From SD0 card's DAT3 pin. 234 * | | |Host need clock to got data on pin DAT3 235 * | | |Please make sure CLKKEEP0 (SDH_CTL[7]) is 1 in order to generate free running clock for DAT3 pin. 236 * | | |1 = From GPIO pin. 237 * @var SDH_T::INTSTS 238 * Offset: 0x82C SD Interrupt Status Register 239 * --------------------------------------------------------------------------------------------------- 240 * |Bits |Field |Descriptions 241 * | :----: | :----: | :---- | 242 * |[0] |BLKDIF |Block Transfer Done Interrupt Flag (Read Only) 243 * | | |This bit indicates that SD host has finished all data-in or data-out block transfer 244 * | | |If there is a CRC16 error or incorrect CRC status during multiple block data transfer, the transfer will be broken and this bit will also be set. 245 * | | |0 = Not finished yet. 246 * | | |1 = Done. 247 * | | |Note: This bit is read only, but can be cleared by writing '1' to it. 248 * |[1] |CRCIF |CRC7, CRC16 and CRC Status Error Interrupt Flag (Read Only) 249 * | | |This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer 250 * | | |When CRC error is occurred, software should reset SD engine 251 * | | |Some response (ex 252 * | | |R3) doesn't have CRC7 information with it; SD host will still calculate CRC7, get CRC error and set this flag 253 * | | |In this condition, software should ignore CRC error and clears this bit manually. 254 * | | |0 = No CRC error is occurred. 255 * | | |1 = CRC error is occurred. 256 * | | |Note: This bit is read only, but can be cleared by writing '1' to it. 257 * |[2] |CRC7 |CRC7 Check Status (Read Only) 258 * | | |SD host will check CRC7 correctness during each response in 259 * | | |If that response does not contain CRC7 information (ex 260 * | | |R3), then software should turn off CRCIEN (SDH_INTEN[1]) and ignore this bit. 261 * | | |0 = Fault. 262 * | | |1 = OK. 263 * |[3] |CRC16 |CRC16 Check Status of Data-in Transfer (Read Only) 264 * | | |SD host will check CRC16 correctness after data-in transfer. 265 * | | |0 = Fault. 266 * | | |1 = OK. 267 * |[6:4] |CRCSTS |CRC Status Value of Data-out Transfer (Read Only) 268 * | | |SD host will record CRC status of data-out transfer 269 * | | |Software could use this value to identify what type of error is during data-out transfer. 270 * | | |010 = Positive CRC status. 271 * | | |101 = Negative CRC status. 272 * | | |111 = SD card programming error occurs. 273 * |[7] |DAT0STS |DAT0 Pin Status of Current Selected SD Port (Read Only) 274 * | | |This bit is the DAT0 pin status of current selected SD port. 275 * |[8] |CDIF0 |SD0 Card Detection Interrupt Flag (Read Only) 276 * | | |This bit indicates that SD card 0 is inserted or removed 277 * | | |Only when CDIEN0 (SDH_INTEN[8]) is set to 1, this bit is active. 278 * | | |0 = No card is inserted or removed. 279 * | | |1 = There is a card inserted in or removed from SD0. 280 * | | |Note: This bit is read only, but can be cleared by writing '1' to it. 281 * |[12] |RTOIF |Response Time-out Interrupt Flag (Read Only) 282 * | | |This bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit). 283 * | | |0 = Not time-out. 284 * | | |1 = Response time-out. 285 * | | |Note: This bit is read only, but can be cleared by writing '1' to it. 286 * |[13] |DITOIF |Data Input Time-out Interrupt Flag (Read Only) 287 * | | |This bit indicates that SD host counts to time-out value when receiving data (waiting start bit). 288 * | | |0 = Not time-out. 289 * | | |1 = Data input time-out. 290 * | | |Note: This bit is read only, but can be cleared by writing '1' to it. 291 * |[16] |CDSTS0 |Card Detect Status of SD0 (Read Only) 292 * | | |This bit indicates the card detect pin status of SD0, and is used for card detection 293 * | | |When there is a card inserted in or removed from SD0, software should check this bit to confirm if there is really a card insertion or removal. 294 * | | |If CDSRC0 (SDH_INTEN[30]) = 0, to select DAT3 for card detection:. 295 * | | |0 = Card removed. 296 * | | |1 = Card inserted. 297 * | | |If CDSRC0 (SDH_INTEN[30]) = 1, to select GPIO for card detection:. 298 * | | |0 = Card inserted. 299 * | | |1 = Card removed. 300 * |[18] |DAT1STS |DAT1 Pin Status of SD Port (Read Only) 301 * | | |This bit indicates the DAT1 pin status of SD port. 302 * @var SDH_T::RESP0 303 * Offset: 0x830 SD Receiving Response Token Register 0 304 * --------------------------------------------------------------------------------------------------- 305 * |Bits |Field |Descriptions 306 * | :----: | :----: | :---- | 307 * |[31:0] |RESPTK0 |SD Receiving Response Token 0 308 * | | |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set 309 * | | |This field contains response bit 47-16 of the response token. 310 * @var SDH_T::RESP1 311 * Offset: 0x834 SD Receiving Response Token Register 1 312 * --------------------------------------------------------------------------------------------------- 313 * |Bits |Field |Descriptions 314 * | :----: | :----: | :---- | 315 * |[7:0] |RESPTK1 |SD Receiving Response Token 1 316 * | | |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set 317 * | | |This register contains the bit 15-8 of the response token. 318 * @var SDH_T::BLEN 319 * Offset: 0x838 SD Block Length Register 320 * --------------------------------------------------------------------------------------------------- 321 * |Bits |Field |Descriptions 322 * | :----: | :----: | :---- | 323 * |[10:0] |BLKLEN |SD BLOCK LENGTH in Byte Unit 324 * | | |An 11-bit value specifies the SD transfer byte count of a block 325 * | | |The actual byte count is equal to BLKLEN+1. 326 * | | |Note: The default SD block length is 512 bytes 327 * @var SDH_T::TOUT 328 * Offset: 0x83C SD Response/Data-in Time-out Register 329 * --------------------------------------------------------------------------------------------------- 330 * |Bits |Field |Descriptions 331 * | :----: | :----: | :---- | 332 * |[23:0] |TOUT |SD Response/Data-in Time-out Value 333 * | | |A 24-bit value specifies the time-out counts of response and data input 334 * | | |SD host controller will wait start bit of response or data-in until this value reached 335 * | | |The time period depends on SD engine clock frequency 336 * | | |Do not write a small number into this field, or you may never get response or data due to time-out. 337 * | | |Note: Filling 0x0 into this field will disable hardware time-out function. 338 */ 339 340 __IO uint32_t FB[32]; /*!< Shared Buffer (FIFO) */ 341 __I uint32_t RESERVE0[224]; 342 __IO uint32_t DMACTL; /*!< [0x0400] DMA Control and Status Register */ 343 __I uint32_t RESERVE1[1]; 344 __IO uint32_t DMASA; /*!< [0x0408] DMA Transfer Starting Address Register */ 345 __I uint32_t DMABCNT; /*!< [0x040c] DMA Transfer Byte Count Register */ 346 __IO uint32_t DMAINTEN; /*!< [0x0410] DMA Interrupt Enable Control Register */ 347 __IO uint32_t DMAINTSTS; /*!< [0x0414] DMA Interrupt Status Register */ 348 __I uint32_t RESERVE2[250]; 349 __IO uint32_t GCTL; /*!< [0x0800] Global Control and Status Register */ 350 __IO uint32_t GINTEN; /*!< [0x0804] Global Interrupt Control Register */ 351 __IO uint32_t GINTSTS; /*!< [0x0808] Global Interrupt Status Register */ 352 __I uint32_t RESERVE3[5]; 353 __IO uint32_t CTL; /*!< [0x0820] SD Control and Status Register */ 354 __IO uint32_t CMDARG; /*!< [0x0824] SD Command Argument Register */ 355 __IO uint32_t INTEN; /*!< [0x0828] SD Interrupt Control Register */ 356 __IO uint32_t INTSTS; /*!< [0x082c] SD Interrupt Status Register */ 357 __I uint32_t RESP0; /*!< [0x0830] SD Receiving Response Token Register 0 */ 358 __I uint32_t RESP1; /*!< [0x0834] SD Receiving Response Token Register 1 */ 359 __IO uint32_t BLEN; /*!< [0x0838] SD Block Length Register */ 360 __IO uint32_t TOUT; /*!< [0x083c] SD Response/Data-in Time-out Register */ 361 362 } SDH_T; 363 364 /** 365 @addtogroup SDH_CONST SDH Bit Field Definition 366 Constant Definitions for SDH Controller 367 @{ 368 */ 369 370 #define SDH_DMACTL_DMAEN_Pos (0) /*!< SDH_T::DMACTL: DMAEN Position */ 371 #define SDH_DMACTL_DMAEN_Msk (0x1ul << SDH_DMACTL_DMAEN_Pos) /*!< SDH_T::DMACTL: DMAEN Mask */ 372 373 #define SDH_DMACTL_DMARST_Pos (1) /*!< SDH_T::DMACTL: DMARST Position */ 374 #define SDH_DMACTL_DMARST_Msk (0x1ul << SDH_DMACTL_DMARST_Pos) /*!< SDH_T::DMACTL: DMARST Mask */ 375 376 #define SDH_DMACTL_SGEN_Pos (3) /*!< SDH_T::DMACTL: SGEN Position */ 377 #define SDH_DMACTL_SGEN_Msk (0x1ul << SDH_DMACTL_SGEN_Pos) /*!< SDH_T::DMACTL: SGEN Mask */ 378 379 #define SDH_DMACTL_DMABUSY_Pos (9) /*!< SDH_T::DMACTL: DMABUSY Position */ 380 #define SDH_DMACTL_DMABUSY_Msk (0x1ul << SDH_DMACTL_DMABUSY_Pos) /*!< SDH_T::DMACTL: DMABUSY Mask */ 381 382 #define SDH_DMASA_ORDER_Pos (0) /*!< SDH_T::DMASA: ORDER Position */ 383 #define SDH_DMASA_ORDER_Msk (0x1ul << SDH_DMASA_ORDER_Pos) /*!< SDH_T::DMASA: ORDER Mask */ 384 385 #define SDH_DMASA_DMASA_Pos (1) /*!< SDH_T::DMASA: DMASA Position */ 386 #define SDH_DMASA_DMASA_Msk (0x7ffffffful << SDH_DMASA_DMASA_Pos) /*!< SDH_T::DMASA: DMASA Mask */ 387 388 #define SDH_DMABCNT_BCNT_Pos (0) /*!< SDH_T::DMABCNT: BCNT Position */ 389 #define SDH_DMABCNT_BCNT_Msk (0x3fffffful << SDH_DMABCNT_BCNT_Pos) /*!< SDH_T::DMABCNT: BCNT Mask */ 390 391 #define SDH_DMAINTEN_ABORTIEN_Pos (0) /*!< SDH_T::DMAINTEN: ABORTIEN Position */ 392 #define SDH_DMAINTEN_ABORTIEN_Msk (0x1ul << SDH_DMAINTEN_ABORTIEN_Pos) /*!< SDH_T::DMAINTEN: ABORTIEN Mask */ 393 394 #define SDH_DMAINTEN_WEOTIEN_Pos (1) /*!< SDH_T::DMAINTEN: WEOTIEN Position */ 395 #define SDH_DMAINTEN_WEOTIEN_Msk (0x1ul << SDH_DMAINTEN_WEOTIEN_Pos) /*!< SDH_T::DMAINTEN: WEOTIEN Mask */ 396 397 #define SDH_DMAINTSTS_ABORTIF_Pos (0) /*!< SDH_T::DMAINTSTS: ABORTIF Position */ 398 #define SDH_DMAINTSTS_ABORTIF_Msk (0x1ul << SDH_DMAINTSTS_ABORTIF_Pos) /*!< SDH_T::DMAINTSTS: ABORTIF Mask */ 399 400 #define SDH_DMAINTSTS_WEOTIF_Pos (1) /*!< SDH_T::DMAINTSTS: WEOTIF Position */ 401 #define SDH_DMAINTSTS_WEOTIF_Msk (0x1ul << SDH_DMAINTSTS_WEOTIF_Pos) /*!< SDH_T::DMAINTSTS: WEOTIF Mask */ 402 403 #define SDH_GCTL_GCTLRST_Pos (0) /*!< SDH_T::GCTL: GCTLRST Position */ 404 #define SDH_GCTL_GCTLRST_Msk (0x1ul << SDH_GCTL_GCTLRST_Pos) /*!< SDH_T::GCTL: GCTLRST Mask */ 405 406 #define SDH_GCTL_SDEN_Pos (1) /*!< SDH_T::GCTL: SDEN Position */ 407 #define SDH_GCTL_SDEN_Msk (0x1ul << SDH_GCTL_SDEN_Pos) /*!< SDH_T::GCTL: SDEN Mask */ 408 409 #define SDH_GINTEN_DTAIEN_Pos (0) /*!< SDH_T::GINTEN: DTAIEN Position */ 410 #define SDH_GINTEN_DTAIEN_Msk (0x1ul << SDH_GINTEN_DTAIEN_Pos) /*!< SDH_T::GINTEN: DTAIEN Mask */ 411 412 #define SDH_GINTSTS_DTAIF_Pos (0) /*!< SDH_T::GINTSTS: DTAIF Position */ 413 #define SDH_GINTSTS_DTAIF_Msk (0x1ul << SDH_GINTSTS_DTAIF_Pos) /*!< SDH_T::GINTSTS: DTAIF Mask */ 414 415 #define SDH_CTL_COEN_Pos (0) /*!< SDH_T::CTL: COEN Position */ 416 #define SDH_CTL_COEN_Msk (0x1ul << SDH_CTL_COEN_Pos) /*!< SDH_T::CTL: COEN Mask */ 417 418 #define SDH_CTL_RIEN_Pos (1) /*!< SDH_T::CTL: RIEN Position */ 419 #define SDH_CTL_RIEN_Msk (0x1ul << SDH_CTL_RIEN_Pos) /*!< SDH_T::CTL: RIEN Mask */ 420 421 #define SDH_CTL_DIEN_Pos (2) /*!< SDH_T::CTL: DIEN Position */ 422 #define SDH_CTL_DIEN_Msk (0x1ul << SDH_CTL_DIEN_Pos) /*!< SDH_T::CTL: DIEN Mask */ 423 424 #define SDH_CTL_DOEN_Pos (3) /*!< SDH_T::CTL: DOEN Position */ 425 #define SDH_CTL_DOEN_Msk (0x1ul << SDH_CTL_DOEN_Pos) /*!< SDH_T::CTL: DOEN Mask */ 426 427 #define SDH_CTL_R2EN_Pos (4) /*!< SDH_T::CTL: R2EN Position */ 428 #define SDH_CTL_R2EN_Msk (0x1ul << SDH_CTL_R2EN_Pos) /*!< SDH_T::CTL: R2EN Mask */ 429 430 #define SDH_CTL_CLK74OEN_Pos (5) /*!< SDH_T::CTL: CLK74OEN Position */ 431 #define SDH_CTL_CLK74OEN_Msk (0x1ul << SDH_CTL_CLK74OEN_Pos) /*!< SDH_T::CTL: CLK74OEN Mask */ 432 433 #define SDH_CTL_CLK8OEN_Pos (6) /*!< SDH_T::CTL: CLK8OEN Position */ 434 #define SDH_CTL_CLK8OEN_Msk (0x1ul << SDH_CTL_CLK8OEN_Pos) /*!< SDH_T::CTL: CLK8OEN Mask */ 435 436 #define SDH_CTL_CLKKEEP_Pos (7) /*!< SDH_T::CTL: CLKKEEP Position */ 437 #define SDH_CTL_CLKKEEP_Msk (0x1ul << SDH_CTL_CLKKEEP_Pos) /*!< SDH_T::CTL: CLKKEEP Mask */ 438 439 #define SDH_CTL_CMDCODE_Pos (8) /*!< SDH_T::CTL: CMDCODE Position */ 440 #define SDH_CTL_CMDCODE_Msk (0x3ful << SDH_CTL_CMDCODE_Pos) /*!< SDH_T::CTL: CMDCODE Mask */ 441 442 #define SDH_CTL_CTLRST_Pos (14) /*!< SDH_T::CTL: CTLRST Position */ 443 #define SDH_CTL_CTLRST_Msk (0x1ul << SDH_CTL_CTLRST_Pos) /*!< SDH_T::CTL: CTLRST Mask */ 444 445 #define SDH_CTL_DBW_Pos (15) /*!< SDH_T::CTL: DBW Position */ 446 #define SDH_CTL_DBW_Msk (0x1ul << SDH_CTL_DBW_Pos) /*!< SDH_T::CTL: DBW Mask */ 447 448 #define SDH_CTL_BLKCNT_Pos (16) /*!< SDH_T::CTL: BLKCNT Position */ 449 #define SDH_CTL_BLKCNT_Msk (0xfful << SDH_CTL_BLKCNT_Pos) /*!< SDH_T::CTL: BLKCNT Mask */ 450 451 #define SDH_CTL_SDNWR_Pos (24) /*!< SDH_T::CTL: SDNWR Position */ 452 #define SDH_CTL_SDNWR_Msk (0xful << SDH_CTL_SDNWR_Pos) /*!< SDH_T::CTL: SDNWR Mask */ 453 454 #define SDH_CMDARG_ARGUMENT_Pos (0) /*!< SDH_T::CMDARG: ARGUMENT Position */ 455 #define SDH_CMDARG_ARGUMENT_Msk (0xfffffffful << SDH_CMDARG_ARGUMENT_Pos) /*!< SDH_T::CMDARG: ARGUMENT Mask */ 456 457 #define SDH_INTEN_BLKDIEN_Pos (0) /*!< SDH_T::INTEN: BLKDIEN Position */ 458 #define SDH_INTEN_BLKDIEN_Msk (0x1ul << SDH_INTEN_BLKDIEN_Pos) /*!< SDH_T::INTEN: BLKDIEN Mask */ 459 460 #define SDH_INTEN_CRCIEN_Pos (1) /*!< SDH_T::INTEN: CRCIEN Position */ 461 #define SDH_INTEN_CRCIEN_Msk (0x1ul << SDH_INTEN_CRCIEN_Pos) /*!< SDH_T::INTEN: CRCIEN Mask */ 462 463 #define SDH_INTEN_CDIEN_Pos (8) /*!< SDH_T::INTEN: CDIEN Position */ 464 #define SDH_INTEN_CDIEN_Msk (0x1ul << SDH_INTEN_CDIEN_Pos) /*!< SDH_T::INTEN: CDIEN Mask */ 465 466 #define SDH_INTEN_RTOIEN_Pos (12) /*!< SDH_T::INTEN: RTOIEN Position */ 467 #define SDH_INTEN_RTOIEN_Msk (0x1ul << SDH_INTEN_RTOIEN_Pos) /*!< SDH_T::INTEN: RTOIEN Mask */ 468 469 #define SDH_INTEN_DITOIEN_Pos (13) /*!< SDH_T::INTEN: DITOIEN Position */ 470 #define SDH_INTEN_DITOIEN_Msk (0x1ul << SDH_INTEN_DITOIEN_Pos) /*!< SDH_T::INTEN: DITOIEN Mask */ 471 472 #define SDH_INTEN_WKIEN_Pos (14) /*!< SDH_T::INTEN: WKIEN Position */ 473 #define SDH_INTEN_WKIEN_Msk (0x1ul << SDH_INTEN_WKIEN_Pos) /*!< SDH_T::INTEN: WKIEN Mask */ 474 475 #define SDH_INTEN_CDSRC_Pos (30) /*!< SDH_T::INTEN: CDSRC Position */ 476 #define SDH_INTEN_CDSRC_Msk (0x1ul << SDH_INTEN_CDSRC_Pos) /*!< SDH_T::INTEN: CDSRC Mask */ 477 478 #define SDH_INTSTS_BLKDIF_Pos (0) /*!< SDH_T::INTSTS: BLKDIF Position */ 479 #define SDH_INTSTS_BLKDIF_Msk (0x1ul << SDH_INTSTS_BLKDIF_Pos) /*!< SDH_T::INTSTS: BLKDIF Mask */ 480 481 #define SDH_INTSTS_CRCIF_Pos (1) /*!< SDH_T::INTSTS: CRCIF Position */ 482 #define SDH_INTSTS_CRCIF_Msk (0x1ul << SDH_INTSTS_CRCIF_Pos) /*!< SDH_T::INTSTS: CRCIF Mask */ 483 484 #define SDH_INTSTS_CRC7_Pos (2) /*!< SDH_T::INTSTS: CRC7 Position */ 485 #define SDH_INTSTS_CRC7_Msk (0x1ul << SDH_INTSTS_CRC7_Pos) /*!< SDH_T::INTSTS: CRC7 Mask */ 486 487 #define SDH_INTSTS_CRC16_Pos (3) /*!< SDH_T::INTSTS: CRC16 Position */ 488 #define SDH_INTSTS_CRC16_Msk (0x1ul << SDH_INTSTS_CRC16_Pos) /*!< SDH_T::INTSTS: CRC16 Mask */ 489 490 #define SDH_INTSTS_CRCSTS_Pos (4) /*!< SDH_T::INTSTS: CRCSTS Position */ 491 #define SDH_INTSTS_CRCSTS_Msk (0x7ul << SDH_INTSTS_CRCSTS_Pos) /*!< SDH_T::INTSTS: CRCSTS Mask */ 492 493 #define SDH_INTSTS_DAT0STS_Pos (7) /*!< SDH_T::INTSTS: DAT0STS Position */ 494 #define SDH_INTSTS_DAT0STS_Msk (0x1ul << SDH_INTSTS_DAT0STS_Pos) /*!< SDH_T::INTSTS: DAT0STS Mask */ 495 496 #define SDH_INTSTS_CDIF_Pos (8) /*!< SDH_T::INTSTS: CDIF Position */ 497 #define SDH_INTSTS_CDIF_Msk (0x1ul << SDH_INTSTS_CDIF_Pos) /*!< SDH_T::INTSTS: CDIF Mask */ 498 499 #define SDH_INTSTS_RTOIF_Pos (12) /*!< SDH_T::INTSTS: RTOIF Position */ 500 #define SDH_INTSTS_RTOIF_Msk (0x1ul << SDH_INTSTS_RTOIF_Pos) /*!< SDH_T::INTSTS: RTOIF Mask */ 501 502 #define SDH_INTSTS_DITOIF_Pos (13) /*!< SDH_T::INTSTS: DITOIF Position */ 503 #define SDH_INTSTS_DITOIF_Msk (0x1ul << SDH_INTSTS_DITOIF_Pos) /*!< SDH_T::INTSTS: DITOIF Mask */ 504 505 #define SDH_INTSTS_CDSTS_Pos (16) /*!< SDH_T::INTSTS: CDSTS Position */ 506 #define SDH_INTSTS_CDSTS_Msk (0x1ul << SDH_INTSTS_CDSTS_Pos) /*!< SDH_T::INTSTS: CDSTS Mask */ 507 508 #define SDH_INTSTS_DAT1STS_Pos (18) /*!< SDH_T::INTSTS: DAT1STS Position */ 509 #define SDH_INTSTS_DAT1STS_Msk (0x1ul << SDH_INTSTS_DAT1STS_Pos) /*!< SDH_T::INTSTS: DAT1STS Mask */ 510 511 #define SDH_RESP0_RESPTK0_Pos (0) /*!< SDH_T::RESP0: RESPTK0 Position */ 512 #define SDH_RESP0_RESPTK0_Msk (0xfffffffful << SDH_RESP0_RESPTK0_Pos) /*!< SDH_T::RESP0: RESPTK0 Mask */ 513 514 #define SDH_RESP1_RESPTK1_Pos (0) /*!< SDH_T::RESP1: RESPTK1 Position */ 515 #define SDH_RESP1_RESPTK1_Msk (0xfful << SDH_RESP1_RESPTK1_Pos) /*!< SDH_T::RESP1: RESPTK1 Mask */ 516 517 #define SDH_BLEN_BLKLEN_Pos (0) /*!< SDH_T::BLEN: BLKLEN Position */ 518 #define SDH_BLEN_BLKLEN_Msk (0x7fful << SDH_BLEN_BLKLEN_Pos) /*!< SDH_T::BLEN: BLKLEN Mask */ 519 520 #define SDH_TOUT_TOUT_Pos (0) /*!< SDH_T::TOUT: TOUT Position */ 521 #define SDH_TOUT_TOUT_Msk (0xfffffful << SDH_TOUT_TOUT_Pos) /*!< SDH_T::TOUT: TOUT Mask */ 522 523 /**@}*/ /* SDH_CONST */ 524 /**@}*/ /* end of SDH register group */ 525 /**@}*/ /* end of REGISTER group */ 526 527 528 #endif /* __SDH_REG_H__ */ 529
