1 /**************************************************************************//** 2 * @file hdiv_reg.h 3 * @version V1.00 4 * @brief HDIV register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __HDIV_REG_H__ 10 #define __HDIV_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 /*---------------------- Hardware Divider --------------------------------*/ 19 /** 20 @addtogroup HDIV Hardware Divider(HDIV) 21 Memory Mapped Structure for HDIV Controller 22 @{ 23 */ 24 25 typedef struct 26 { 27 28 29 /** 30 * @var HDIV_T::DIVIDEND 31 * Offset: 0x00 Dividend Source Register 32 * --------------------------------------------------------------------------------------------------- 33 * |Bits |Field |Descriptions 34 * | :----: | :----: | :---- | 35 * |[31:0] |DIVIDEND |Dividend Source 36 * | | |This register is given the dividend of divider before calculation starting. 37 * @var HDIV_T::DIVISOR 38 * Offset: 0x04 Divisor Source Resister 39 * --------------------------------------------------------------------------------------------------- 40 * |Bits |Field |Descriptions 41 * | :----: | :----: | :---- | 42 * |[15:0] |DIVISOR |Divisor Source 43 * | | |This register is given the divisor of divider before calculation starts. 44 * | | |Note: When this register is written, hardware divider will start calculate. 45 * @var HDIV_T::DIVQUO 46 * Offset: 0x08 Quotient Result Resister 47 * --------------------------------------------------------------------------------------------------- 48 * |Bits |Field |Descriptions 49 * | :----: | :----: | :---- | 50 * |[31:0] |QUOTIENT |Quotient Result 51 * | | |This register holds the quotient result of divider after calculation complete. 52 * @var HDIV_T::DIVREM 53 * Offset: 0x0C Remainder Result Register 54 * --------------------------------------------------------------------------------------------------- 55 * |Bits |Field |Descriptions 56 * | :----: | :----: | :---- | 57 * |[31:0] |REMAINDER |Remainder Result 58 * | | |The remainder of hardware divider is 16-bit sign integer (REMAINDER[15:0]), which holds the remainder result of divider after calculation complete. 59 * | | |The remainder of hardware divider with sign extension (REMAINDER[31:16]) to 32-bit integer. 60 * | | |This register holds the remainder result of divider after calculation complete. 61 * @var HDIV_T::DIVSTS 62 * Offset: 0x10 Divider Status Register 63 * --------------------------------------------------------------------------------------------------- 64 * |Bits |Field |Descriptions 65 * | :----: | :----: | :---- | 66 * |[0] |FINISH |Division Finish Flag 67 * | | |0 = Under Calculation. 68 * | | |1 = Calculation finished. 69 * | | |The flag will become low when the divider is in calculation. 70 * | | |The flag will go back to high once the calculation finished. 71 * |[1] |DIV0 |Divisor Zero Warning 72 * | | |0 = The divisor is not 0. 73 * | | |1 = The divisor is 0. 74 * | | |Note: The DIV0 flag is used to indicate divide-by-zero situation and updated whenever DIVISOR is written 75 * | | |This register is read only. 76 */ 77 __IO uint32_t DIVIDEND; /*!< [0x0000] Dividend Source Register */ 78 __IO uint32_t DIVISOR; /*!< [0x0004] Divisor Source Resister */ 79 __IO uint32_t DIVQUO; /*!< [0x0008] Quotient Result Resister */ 80 __IO uint32_t DIVREM; /*!< [0x000c] Remainder Result Register */ 81 __I uint32_t DIVSTS; /*!< [0x0010] Divider Status Register */ 82 83 } HDIV_T; 84 85 /** 86 @addtogroup HDIV_CONST HDIV Bit Field Definition 87 Constant Definitions for HDIV Controller 88 @{ 89 */ 90 91 #define HDIV_DIVIDEND_DIVIDEND_Pos (0) /*!< HDIV_T::DIVIDEND: DIVIDEND Position */ 92 #define HDIV_DIVIDEND_DIVIDEND_Msk (0xfffffffful << HDIV_DIVIDEND_DIVIDEND_Pos) /*!< HDIV_T::DIVIDEND: DIVIDEND Mask */ 93 94 #define HDIV_DIVISOR_DIVISOR_Pos (0) /*!< HDIV_T::DIVISOR: DIVISOR Position */ 95 #define HDIV_DIVISOR_DIVISOR_Msk (0xfffful << HDIV_DIVISOR_DIVISOR_Pos) /*!< HDIV_T::DIVISOR: DIVISOR Mask */ 96 97 #define HDIV_DIVQUO_QUOTIENT_Pos (0) /*!< HDIV_T::DIVQUO: QUOTIENT Position */ 98 #define HDIV_DIVQUO_QUOTIENT_Msk (0xfffffffful << HDIV_DIVQUO_QUOTIENT_Pos) /*!< HDIV_T::DIVQUO: QUOTIENT Mask */ 99 100 #define HDIV_DIVREM_REMAINDER_Pos (0) /*!< HDIV_T::DIVREM: REMAINDER Position */ 101 #define HDIV_DIVREM_REMAINDER_Msk (0xfffffffful << HDIV_DIVREM_REMAINDER_Pos) /*!< HDIV_T::DIVREM: REMAINDER Mask */ 102 103 #define HDIV_DIVSTS_FINISH_Pos (0) /*!< HDIV_T::DIVSTS: FINISH Position */ 104 #define HDIV_DIVSTS_FINISH_Msk (0x1ul << HDIV_DIVSTS_FINISH_Pos) /*!< HDIV_T::DIVSTS: FINISH Mask */ 105 106 #define HDIV_DIVSTS_DIV0_Pos (1) /*!< HDIV_T::DIVSTS: DIV0 Position */ 107 #define HDIV_DIVSTS_DIV0_Msk (0x1ul << HDIV_DIVSTS_DIV0_Pos) /*!< HDIV_T::DIVSTS: DIV0 Mask */ 108 109 /**@}*/ /* HDIV_CONST */ 110 /**@}*/ /* end of HDIV register group */ 111 /**@}*/ /* end of REGISTER group */ 112 113 114 #endif /* __HDIV_REG_H__ */ 115
