1 /**************************************************************************//** 2 * @file eadc_reg.h 3 * @version V1.00 4 * @brief EADC register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __EADC_REG_H__ 10 #define __EADC_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 /*---------------------- Enhanced Analog to Digital Converter -------------------------*/ 19 /** 20 @addtogroup EADC Enhanced Analog to Digital Converter(EADC) 21 Memory Mapped Structure for EADC Controller 22 @{ 23 */ 24 25 26 typedef struct 27 { 28 29 30 /** 31 * @var EADC_T::DAT[19] 32 * Offset: 0x00 ADC Data Register 0~18 for Sample Module 0~18 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[15:0] |RESULT |ADC Conversion Result 37 * | | |This field contains 12 bits conversion result. 38 * | | |When DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]. 39 * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12]. 40 * |[16] |OV |Overrun Flag 41 * | | |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1. 42 * | | |0 = Data in RESULT[11:0] is recent conversion result. 43 * | | |1 = Data in RESULT[11:0] is overwrite. 44 * | | |Note: It is cleared by hardware after EADC_DAT register is read. 45 * |[17] |VALID |Valid Flag 46 * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read. 47 * | | |0 = Data in RESULT[11:0] bits is not valid. 48 * | | |1 = Data in RESULT[11:0] bits is valid. 49 * @var EADC_T::CURDAT 50 * Offset: 0x4C ADC PDMA Current Transfer Data Register 51 * --------------------------------------------------------------------------------------------------- 52 * |Bits |Field |Descriptions 53 * | :----: | :----: | :---- | 54 * |[17:0] |CURDAT |ADC PDMA Current Transfer Data Register 55 * | | |This register is a shadow register of EADC_DATn (n=0~18) for PDMA support. 56 * | | |This is a read only register. 57 * @var EADC_T::CTL 58 * Offset: 0x50 ADC Control Register 59 * --------------------------------------------------------------------------------------------------- 60 * |Bits |Field |Descriptions 61 * | :----: | :----: | :---- | 62 * |[0] |ADCEN |ADC Converter Enable Bit 63 * | | |0 = Disabled EADC. 64 * | | |1 = Enabled EADC. 65 * | | |Note: Before starting ADC conversion function, this bit should be set to 1 66 * | | |Clear it to 0 to disable ADC converter analog circuit power consumption. 67 * |[1] |ADCRST |ADC Converter Control Circuits Reset 68 * | | |0 = No effect. 69 * | | |1 = Cause ADC control circuits reset to initial state, but not change the ADC registers value. 70 * | | |Note: ADCRST bit remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0. 71 * |[2] |ADCIEN0 |Specific Sample Module ADC ADINT0 Interrupt Enable Bit 72 * | | |The ADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module ADC conversion 73 * | | |If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated. 74 * | | |0 = Specific sample module ADC ADINT0 interrupt function Disabled. 75 * | | |1 = Specific sample module ADC ADINT0 interrupt function Enabled. 76 * |[3] |ADCIEN1 |Specific Sample Module ADC ADINT1 Interrupt Enable Bit 77 * | | |The ADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module ADC conversion 78 * | | |If ADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated. 79 * | | |0 = Specific sample module ADC ADINT1 interrupt function Disabled. 80 * | | |1 = Specific sample module ADC ADINT1 interrupt function Enabled. 81 * |[4] |ADCIEN2 |Specific Sample Module ADC ADINT2 Interrupt Enable Bit 82 * | | |The ADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module ADC conversion 83 * | | |If ADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated. 84 * | | |0 = Specific sample module ADC ADINT2 interrupt function Disabled. 85 * | | |1 = Specific sample module ADC ADINT2 interrupt function Enabled. 86 * |[5] |ADCIEN3 |Specific Sample Module ADC ADINT3 Interrupt Enable Bit 87 * | | |The ADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module ADC conversion 88 * | | |If ADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated. 89 * | | |0 = Specific sample module ADC ADINT3 interrupt function Disabled. 90 * | | |1 = Specific sample module ADC ADINT3 interrupt function Enabled. 91 * |[7:6] |RESSEL |Resolution Selection 92 * | | |00 = 6-bit ADC result will be put at RESULT (EADC_DATn[5:0]). 93 * | | |01 = 8-bit ADC result will be put at RESULT (EADC_DATn[7:0]). 94 * | | |10 = 10-bit ADC result will be put at RESULT (EADC_DATn[9:0]). 95 * | | |11 = 12-bit ADC result will be put at RESULT (EADC_DATn[11:0]). 96 * |[8] |DIFFEN |Differential Analog Input Mode Enable Bit 97 * | | |0 = Single-end analog input mode. 98 * | | |1 = Differential analog input mode. 99 * |[9] |DMOF |ADC Differential Input Mode Output Format 100 * | | |0 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with unsigned format. 101 * | | |1 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with 2'complement format. 102 * @var EADC_T::SWTRG 103 * Offset: 0x54 ADC Sample Module Software Start Register 104 * --------------------------------------------------------------------------------------------------- 105 * |Bits |Field |Descriptions 106 * | :----: | :----: | :---- | 107 * |[18:0] |SWTRG |ADC Sample Module 0~18 Software Force to Start ADC Conversion 108 * | | |0 = No effect. 109 * | | |1 = Cause an ADC conversion when the priority is given to sample module. 110 * | | |Note: After write this register to start ADC conversion, the EADC_PENDSTS register will show which sample module will conversion 111 * | | |If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it. 112 * @var EADC_T::PENDSTS 113 * Offset: 0x58 ADC Start of Conversion Pending Flag Register 114 * --------------------------------------------------------------------------------------------------- 115 * |Bits |Field |Descriptions 116 * | :----: | :----: | :---- | 117 * |[18:0] |STPF |ADC Sample Module 0~18 Start of Conversion Pending Flag 118 * | | |Read: 119 * | | |0 = There is no pending conversion for sample module. 120 * | | |1 = Sample module ADC start of conversion is pending. 121 * | | |Write: 122 * | | |1 = clear pending flag and cancel the conversion for sample module. 123 * | | |Note: This bit remains 1 during pending state, when the respective ADC conversion is end, the STPFn (n=0~18) bit is automatically cleared to 0 124 * @var EADC_T::OVSTS 125 * Offset: 0x5C ADC Sample Module Start of Conversion Overrun Flag Register 126 * --------------------------------------------------------------------------------------------------- 127 * |Bits |Field |Descriptions 128 * | :----: | :----: | :---- | 129 * |[18:0] |SPOVF |ADC SAMPLE0~18 Overrun Flag 130 * | | |0 = No sample module event overrun. 131 * | | |1 = Indicates a new sample module event is generated while an old one event is pending. 132 * | | |Note: This bit is cleared by writing 1 to it. 133 * @var EADC_T::SCTL[19] 134 * Offset: 0x80 ADC Sample Module 0~18 Control Register 135 * --------------------------------------------------------------------------------------------------- 136 * |Bits |Field |Descriptions 137 * | :----: | :----: | :---- | 138 * |[3:0] |CHSEL |ADC Sample Module Channel Selection 139 * | | |00H = EADC_CH0 (slow channel). 140 * | | |01H = EADC_CH1 (slow channel). 141 * | | |02H = EADC_CH2 (slow channel). 142 * | | |03H = EADC_CH3 (slow channel). 143 * | | |04H = EADC_CH4 (slow channel). 144 * | | |05H = EADC_CH5 (slow channel). 145 * | | |06H = EADC_CH6 (slow channel). 146 * | | |07H = EADC_CH7 (slow channel). 147 * | | |08H = EADC_CH8 (slow channel). 148 * | | |09H = EADC_CH9 (slow channel). 149 * | | |0AH = EADC_CH10 (fast channel). 150 * | | |0BH = EADC_CH11 (fast channel). 151 * | | |0CH = EADC_CH12 (fast channel). 152 * | | |0DH = EADC_CH13 (fast channel). 153 * | | |0EH = EADC_CH14 (fast channel). 154 * | | |0FH = EADC_CH15 (fast channel). 155 * |[4] |EXTREN |ADC External Trigger Rising Edge Enable Bit 156 * | | |0 = Rising edge Disabled when ADC selects EADC0_ST as trigger source. 157 * | | |1 = Rising edge Enabled when ADC selects EADC0_ST as trigger source. 158 * |[5] |EXTFEN |ADC External Trigger Falling Edge Enable Bit 159 * | | |0 = Falling edge Disabled when ADC selects EADC0_ST as trigger source. 160 * | | |1 = Falling edge Enabled when ADC selects EADC0_ST as trigger source. 161 * |[7:6] |TRGDLYDIV |ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection 162 * | | |Trigger delay clock frequency: 163 * | | |00 = ADC_CLK/1. 164 * | | |01 = ADC_CLK/2. 165 * | | |10 = ADC_CLK/4. 166 * | | |11 = ADC_CLK/16. 167 * |[15:8] |TRGDLYCNT |ADC Sample Module Start of Conversion Trigger Delay Time 168 * | | |Trigger delay time = TRGDLYCNT x ADC_CLK x n (n=1,2,4,16 from TRGDLYDIV setting). 169 * |[20:16] |TRGSEL |ADC Sample Module Start of Conversion Trigger Source Selection 170 * | | |0H = Disable trigger. 171 * | | |1H = External trigger from EADC0_ST pin input. 172 * | | |2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger. 173 * | | |3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger. 174 * | | |4H = Timer0 overflow pulse trigger. 175 * | | |5H = Timer1 overflow pulse trigger. 176 * | | |6H = Timer2 overflow pulse trigger. 177 * | | |7H = Timer3 overflow pulse trigger. 178 * | | |8H = Timer4 overflow pulse trigger. 179 * | | |9H = Timer5 overflow pulse trigger. 180 * | | |AH = EPWM0TG0. 181 * | | |BH = EPWM0TG1. 182 * | | |CH = EPWM0TG2. 183 * | | |DH = EPWM0TG3. 184 * | | |EH = EPWM0TG4. 185 * | | |FH = EPWM0TG5. 186 * | | |10H = EPWM1TG0. 187 * | | |11H = EPWM1TG1. 188 * | | |12H = EPWM1TG2. 189 * | | |13H = EPWM1TG3. 190 * | | |14H = EPWM1TG4. 191 * | | |15H = EPWM1TG5. 192 * | | |16H = BPWM0TG. 193 * | | |17H = BPWM1TG. 194 * | | |other = Reserved. 195 * |[22] |INTPOS |Interrupt Flag Position Select 196 * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC end of conversion. 197 * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC start of conversion. 198 * |[23] |DBMEN |Double Buffer Mode Enable Bit 199 * | | |0 = Sample has one sample result register. (default). 200 * | | |1 = Sample has two sample result registers. 201 * |[31:24] |EXTSMPT |ADC Sampling Time Extend 202 * | | |When ADC converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend ADC sampling time after trigger source is coming to get enough sampling time. 203 * | | |The range of start delay time is from 0~255 ADC clock. 204 * @var EADC_T::INTSRC[4] 205 * Offset: 0xD0 ADC interrupt 0~3 Source Enable Control Register. 206 * --------------------------------------------------------------------------------------------------- 207 * |Bits |Field |Descriptions 208 * | :----: | :----: | :---- | 209 * |[0] |SPLIE0 |Sample Module 0 Interrupt Enable Bit 210 * | | |0 = Sample Module 0 interrupt Disabled. 211 * | | |1 = Sample Module 0 interrupt Enabled. 212 * |[1] |SPLIE1 |Sample Module 1 Interrupt Enable Bit 213 * | | |0 = Sample Module 1 interrupt Disabled. 214 * | | |1 = Sample Module 1 interrupt Enabled. 215 * |[2] |SPLIE2 |Sample Module 2 Interrupt Enable Bit 216 * | | |0 = Sample Module 2 interrupt Disabled. 217 * | | |1 = Sample Module 2 interrupt Enabled. 218 * |[3] |SPLIE3 |Sample Module 3 Interrupt Enable Bit 219 * | | |0 = Sample Module 3 interrupt Disabled. 220 * | | |1 = Sample Module 3 interrupt Enabled. 221 * |[4] |SPLIE4 |Sample Module 4 Interrupt Enable Bit 222 * | | |0 = Sample Module 4 interrupt Disabled. 223 * | | |1 = Sample Module 4 interrupt Enabled. 224 * |[5] |SPLIE5 |Sample Module 5 Interrupt Enable Bit 225 * | | |0 = Sample Module 5 interrupt Disabled. 226 * | | |1 = Sample Module 5 interrupt Enabled. 227 * |[6] |SPLIE6 |Sample Module 6 Interrupt Enable Bit 228 * | | |0 = Sample Module 6 interrupt Disabled. 229 * | | |1 = Sample Module 6 interrupt Enabled. 230 * |[7] |SPLIE7 |Sample Module 7 Interrupt Enable Bit 231 * | | |0 = Sample Module 7 interrupt Disabled. 232 * | | |1 = Sample Module 7 interrupt Enabled. 233 * |[8] |SPLIE8 |Sample Module 8 Interrupt Enable Bit 234 * | | |0 = Sample Module 8 interrupt Disabled. 235 * | | |1 = Sample Module 8 interrupt Enabled. 236 * |[9] |SPLIE9 |Sample Module 9 Interrupt Enable Bit 237 * | | |0 = Sample Module 9 interrupt Disabled. 238 * | | |1 = Sample Module 9 interrupt Enabled. 239 * |[10] |SPLIE10 |Sample Module 10 Interrupt Enable Bit 240 * | | |0 = Sample Module 10 interrupt Disabled. 241 * | | |1 = Sample Module 10 interrupt Enabled. 242 * |[11] |SPLIE11 |Sample Module 11 Interrupt Enable Bit 243 * | | |0 = Sample Module 11 interrupt Disabled. 244 * | | |1 = Sample Module 11 interrupt Enabled. 245 * |[12] |SPLIE12 |Sample Module 12 Interrupt Enable Bit 246 * | | |0 = Sample Module 12 interrupt Disabled. 247 * | | |1 = Sample Module 12 interrupt Enabled. 248 * |[13] |SPLIE13 |Sample Module 13 Interrupt Enable Bit 249 * | | |0 = Sample Module 13 interrupt Disabled. 250 * | | |1 = Sample Module 13 interrupt Enabled. 251 * |[14] |SPLIE14 |Sample Module 14 Interrupt Enable Bit 252 * | | |0 = Sample Module 14 interrupt Disabled. 253 * | | |1 = Sample Module 14 interrupt Enabled. 254 * |[15] |SPLIE15 |Sample Module 15 Interrupt Enable Bit 255 * | | |0 = Sample Module 15 interrupt Disabled. 256 * | | |1 = Sample Module 15 interrupt Enabled. 257 * |[16] |SPLIE16 |Sample Module 16 Interrupt Enable Bit 258 * | | |0 = Sample Module 16 interrupt Disabled. 259 * | | |1 = Sample Module 16 interrupt Enabled. 260 * |[17] |SPLIE17 |Sample Module 17 Interrupt Enable Bit 261 * | | |0 = Sample Module 17 interrupt Disabled. 262 * | | |1 = Sample Module 17 interrupt Enabled. 263 * |[18] |SPLIE18 |Sample Module 18 Interrupt Enable Bit 264 * | | |0 = Sample Module 18 interrupt Disabled. 265 * | | |1 = Sample Module 18 interrupt Enabled. 266 * @var EADC_T::CMP[4] 267 * Offset: 0xE0 ADC Result Compare Register 0~3 268 * --------------------------------------------------------------------------------------------------- 269 * |Bits |Field |Descriptions 270 * | :----: | :----: | :---- | 271 * |[0] |ADCMPEN |ADC Result Compare Enable Bit 272 * | | |0 = Compare Disabled. 273 * | | |1 = Compare Enabled. 274 * | | |Set this bit to 1 to enable compare CMPDAT (EADC_CMPn[27:16], n=0~3) with specified sample module conversion result when converted data is loaded into EADC_DAT register. 275 * |[1] |ADCMPIE |ADC Result Compare Interrupt Enable Bit 276 * | | |0 = Compare function interrupt Disabled. 277 * | | |1 = Compare function interrupt Enabled. 278 * | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated. 279 * |[2] |CMPCOND |Compare Condition 280 * | | |0= Set the compare condition as that when a 12-bit ADC conversion result is less than the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one. 281 * | | |1= Set the compare condition as that when a 12-bit ADC conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one. 282 * | | |Note: When the internal counter reaches the value to (CMPMCNT (EADC_CMPn[11:8], n=0~3) +1), the CMPF bit will be set. 283 * |[7:3] |CMPSPL |Compare Sample Module Selection 284 * | | |00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared. 285 * | | |00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared. 286 * | | |00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared. 287 * | | |00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared. 288 * | | |00100 = Sample Module 4 conversion result EADC_DAT4 is selected to be compared. 289 * | | |00101 = Sample Module 5 conversion result EADC_DAT5 is selected to be compared. 290 * | | |00110 = Sample Module 6 conversion result EADC_DAT6 is selected to be compared. 291 * | | |00111 = Sample Module 7 conversion result EADC_DAT7 is selected to be compared. 292 * | | |01000 = Sample Module 8 conversion result EADC_DAT8 is selected to be compared. 293 * | | |01001 = Sample Module 9 conversion result EADC_DAT9 is selected to be compared. 294 * | | |01010 = Sample Module 10 conversion result EADC_DAT10 is selected to be compared. 295 * | | |01011 = Sample Module 11 conversion result EADC_DAT11 is selected to be compared. 296 * | | |01100 = Sample Module 12 conversion result EADC_DAT12 is selected to be compared. 297 * | | |01101 = Sample Module 13 conversion result EADC_DAT13 is selected to be compared. 298 * | | |01110 = Sample Module 14 conversion result EADC_DAT14 is selected to be compared. 299 * | | |01111 = Sample Module 15 conversion result EADC_DAT15 is selected to be compared. 300 * | | |10000 = Sample Module 16 conversion result EADC_DAT16 is selected to be compared. 301 * | | |10001 = Sample Module 17 conversion result EADC_DAT17 is selected to be compared. 302 * | | |10010 = Sample Module 18 conversion result EADC_DAT18 is selected to be compared. 303 * |[11:8] |CMPMCNT |Compare Match Count 304 * | | |When the specified ADC sample module analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPn[2], n=0~3), the internal match counter will increase 1 305 * | | |If the compare result does not meet the compare condition, the internal compare match counter will reset to 0 306 * | | |When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be set. 307 * |[15] |CMPWEN |Compare Window Mode Enable Bit 308 * | | |0 = ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched 309 * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched 310 * | | |1 = ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched 311 * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched. 312 * | | |Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register. 313 * |[27:16] |CMPDAT |Comparison Data 314 * | | |The 12 bits data is used to compare with conversion result of specified sample module 315 * | | |User can use it to monitor the external analog input pin voltage transition without imposing a load on software. 316 * @var EADC_T::STATUS0 317 * Offset: 0xF0 ADC Status Register 0 318 * --------------------------------------------------------------------------------------------------- 319 * |Bits |Field |Descriptions 320 * | :----: | :----: | :---- | 321 * |[15:0] |VALID |EADC_DAT0~15 Data Valid Flag 322 * | | |It is a mirror of VALID bit in sample module ADC result data register EADC_DATn. (n=0~18). 323 * |[31:16] |OV |EADC_DAT0~15 Overrun Flag 324 * | | |It is a mirror to OV bit in sample module ADC result data register EADC_DATn. (n=0~18). 325 * @var EADC_T::STATUS1 326 * Offset: 0xF4 ADC Status Register 1 327 * --------------------------------------------------------------------------------------------------- 328 * |Bits |Field |Descriptions 329 * | :----: | :----: | :---- | 330 * |[2:0] |VALID |EADC_DAT16~18 Data Valid Flag 331 * | | |It is a mirror of VALID bit in sample module ADC result data register EADC_DATn. (n=0~18). 332 * |[18:16] |OV |EADC_DAT16~18 Overrun Flag 333 * | | |It is a mirror to OV bit in sample module ADC result data register EADC_DATn. (n=0~18). 334 * @var EADC_T::STATUS2 335 * Offset: 0xF8 ADC Status Register 2 336 * --------------------------------------------------------------------------------------------------- 337 * |Bits |Field |Descriptions 338 * | :----: | :----: | :---- | 339 * |[0] |ADIF0 |ADC ADINT0 Interrupt Flag 340 * | | |0 = No ADINT0 interrupt pulse received. 341 * | | |1 = ADINT0 interrupt pulse has been received. 342 * | | |Note1: This bit is cleared by writing 1 to it. 343 * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed 344 * |[1] |ADIF1 |ADC ADINT1 Interrupt Flag 345 * | | |0 = No ADINT1 interrupt pulse received. 346 * | | |1 = ADINT1 interrupt pulse has been received. 347 * | | |Note1: This bit is cleared by writing 1 to it. 348 * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed 349 * |[2] |ADIF2 |ADC ADINT2 Interrupt Flag 350 * | | |0 = No ADINT2 interrupt pulse received. 351 * | | |1 = ADINT2 interrupt pulse has been received. 352 * | | |Note1: This bit is cleared by writing 1 to it. 353 * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed 354 * |[3] |ADIF3 |ADC ADINT3 Interrupt Flag 355 * | | |0 = No ADINT3 interrupt pulse received. 356 * | | |1 = ADINT3 interrupt pulse has been received. 357 * | | |Note1: This bit is cleared by writing 1 to it. 358 * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed 359 * |[4] |ADCMPF0 |ADC Compare 0 Flag 360 * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1. 361 * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP0 register setting. 362 * | | |1 = Conversion result in EADC_DAT meets EADC_CMP0 register setting. 363 * | | |Note: This bit is cleared by writing 1 to it. 364 * |[5] |ADCMPF1 |ADC Compare 1 Flag 365 * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1. 366 * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP1 register setting. 367 * | | |1 = Conversion result in EADC_DAT meets EADC_CMP1 register setting. 368 * | | |Note: This bit is cleared by writing 1 to it. 369 * |[6] |ADCMPF2 |ADC Compare 2 Flag 370 * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1. 371 * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP2 register setting. 372 * | | |1 = Conversion result in EADC_DAT meets EADC_CMP2 register setting. 373 * | | |Note: This bit is cleared by writing 1 to it. 374 * |[7] |ADCMPF3 |ADC Compare 3 Flag 375 * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1. 376 * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP3 register setting. 377 * | | |1 = Conversion result in EADC_DAT meets EADC_CMP3 register setting. 378 * | | |Note: This bit is cleared by writing 1 to it. 379 * |[8] |ADOVIF0 |ADC ADINT0 Interrupt Flag Overrun 380 * | | |0 = ADINT0 interrupt flag is not overwritten to 1. 381 * | | |1 = ADINT0 interrupt flag is overwritten to 1. 382 * | | |Note: This bit is cleared by writing 1 to it. 383 * |[9] |ADOVIF1 |ADC ADINT1 Interrupt Flag Overrun 384 * | | |0 = ADINT1 interrupt flag is not overwritten to 1. 385 * | | |1 = ADINT1 interrupt flag is overwritten to 1. 386 * | | |Note: This bit is cleared by writing 1 to it. 387 * |[10] |ADOVIF2 |ADC ADINT2 Interrupt Flag Overrun 388 * | | |0 = ADINT2 interrupt flag is not overwritten to 1. 389 * | | |1 = ADINT2 interrupt flag is s overwritten to 1. 390 * | | |Note: This bit is cleared by writing 1 to it. 391 * |[11] |ADOVIF3 |ADC ADINT3 Interrupt Flag Overrun 392 * | | |0 = ADINT3 interrupt flag is not overwritten to 1. 393 * | | |1 = ADINT3 interrupt flag is overwritten to 1. 394 * | | |Note: This bit is cleared by writing 1 to it. 395 * |[12] |ADCMPO0 |ADC Compare 0 Output Status (Read Only) 396 * | | |The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module. 397 * | | |User can use it to monitor the external analog input pin voltage status. 398 * | | |0 = Conversion result in EADC_DAT less than CMPDAT0 setting. 399 * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT0 setting. 400 * |[13] |ADCMPO1 |ADC Compare 1 Output Status (Read Only) 401 * | | |The 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module. 402 * | | |User can use it to monitor the external analog input pin voltage status. 403 * | | |0 = Conversion result in EADC_DAT less than CMPDAT1 setting. 404 * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT1 setting. 405 * |[14] |ADCMPO2 |ADC Compare 2 Output Status (Read Only) 406 * | | |The 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module. 407 * | | |User can use it to monitor the external analog input pin voltage status. 408 * | | |0 = Conversion result in EADC_DAT less than CMPDAT2 setting. 409 * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT2 setting. 410 * |[15] |ADCMPO3 |ADC Compare 3 Output Status (Read Only) 411 * | | |The 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module. 412 * | | |User can use it to monitor the external analog input pin voltage status. 413 * | | |0 = Conversion result in EADC_DAT less than CMPDAT3 setting. 414 * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT3 setting. 415 * |[20:16] |CHANNEL |Current Conversion Channel (Read Only) 416 * | | |This filed reflects ADC current conversion channel when BUSY=1. 417 * | | |It is read only. 418 * | | |00H = EADC_CH0. 419 * | | |01H = EADC_CH1. 420 * | | |02H = EADC_CH2. 421 * | | |03H = EADC_CH3. 422 * | | |04H = EADC_CH4. 423 * | | |05H = EADC_CH5. 424 * | | |06H = EADC_CH6. 425 * | | |07H = EADC_CH7. 426 * | | |08H = EADC_CH8. 427 * | | |09H = EADC_CH9. 428 * | | |0AH = EADC_CH10. 429 * | | |0BH = EADC_CH11. 430 * | | |0CH = EADC_CH12. 431 * | | |0DH = EADC_CH13. 432 * | | |0EH = EADC_CH14. 433 * | | |0FH = EADC_CH15. 434 * | | |10H = VBG. 435 * | | |11H = VTEMP. 436 * | | |12H = VBAT/4. 437 * |[23] |BUSY |Busy/Idle (Read Only) 438 * | | |0 = EADC is in idle state. 439 * | | |1 = EADC is busy at conversion. 440 * |[24] |ADOVIF |All ADC Interrupt Flag Overrun Bits Check (Read Only) 441 * | | |n=0~3. 442 * | | |0 = None of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1. 443 * | | |1 = Any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1. 444 * | | |Note: This bit will keep 1 when any ADOVIFn Flag is equal to 1. 445 * |[25] |STOVF |for All ADC Sample Module Start of Conversion Overrun Flags Check (Read Only) 446 * | | |n=0~18. 447 * | | |0 = None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. 448 * | | |1 = Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. 449 * | | |Note: This bit will keep 1 when any SPOVFn Flag is equal to 1. 450 * |[26] |AVALID |for All Sample Module ADC Result Data Register EADC_DAT Data Valid Flag Check (Read Only) 451 * | | |n=0~18. 452 * | | |0 = None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. 453 * | | |1 = Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. 454 * | | |Note: This bit will keep 1 when any VALIDn Flag is equal to 1. 455 * |[27] |AOV |for All Sample Module ADC Result Data Register Overrun Flags Check (Read Only) 456 * | | |n=0~18. 457 * | | |0 = None of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. 458 * | | |1 = Any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. 459 * | | |Note: This bit will keep 1 when any OVn Flag is equal to 1. 460 * @var EADC_T::STATUS3 461 * Offset: 0xFC ADC Status Register 3 462 * --------------------------------------------------------------------------------------------------- 463 * |Bits |Field |Descriptions 464 * | :----: | :----: | :---- | 465 * |[4:0] |CURSPL |ADC Current Sample Module 466 * | | |This register show the current ADC is controlled by which sample module control logic modules. 467 * | | |If the ADC is Idle, this bit filed will set to 0x1F. 468 * | | |This is a read only register. 469 * @var EADC_T::DDAT 470 * Offset: 0x100-0x10C ADC Double Data Register n for Sample Module n, n=0~3 471 * --------------------------------------------------------------------------------------------------- 472 * |Bits |Field |Descriptions 473 * | :----: | :----: | :---- | 474 * |[15:0] |RESULT |ADC Conversion Results 475 * | | |This field contains 12 bits conversion results. 476 * | | |When the DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]. 477 * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT [11:0] and signed bits to will be filled in RESULT [15:12]. 478 * |[16] |OV |Overrun Flag 479 * | | |0 = Data in RESULT (EADC_DATn[15:0], n=0~3) is recent conversion result. 480 * | | |1 = Data in RESULT (EADC_DATn[15:0], n=0~3) is overwrite. 481 * | | |If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1. 482 * | | |It is cleared by hardware after EADC_DDAT register is read. 483 * |[17] |VALID |Valid Flag 484 * | | |0 = Double data in RESULT (EADC_DDATn[15:0]) is not valid. 485 * | | |1 = Double data in RESULT (EADC_DDATn[15:0]) is valid. 486 * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DDATn register is read. 487 * | | |(n=0~3). 488 * @var EADC_T::PWRM 489 * Offset: 0x110 ADC Power Management Register 490 * --------------------------------------------------------------------------------------------------- 491 * |Bits |Field |Descriptions 492 * | :----: | :----: | :---- | 493 * |[0] |PWUPRDY |ADC Power-up Sequence Completed and Ready for Conversion (Read Only) 494 * | | |0 = ADC is not ready for conversion may be in power down state or in the progress of power up. 495 * | | |1 = ADC is ready for conversion. 496 * |[1] |PWUCALEN |Power Up Calibration Function Enable Control 497 * | | |0 = Disable the function of calibration at power up. 498 * | | |1 = Enable the function of calibration at power up. 499 * | | |Note: This bit work together with CALSEL (EADC_CALCTL [3]), see the following 500 * | | |{PWUCALEN, CALSEL } Description: 501 * | | |PWUCALEN is 0 and CALSEL is 0: No need to calibrate. 502 * | | |PWUCALEN is 0 and CALSEL is 1: No need to calibrate. 503 * | | |PWUCALEN is 1 and CALSEL is 0: Load calibration word when power up. 504 * | | |PWUCALEN is 1 and CALSEL is 1: Calibrate when power up. 505 * |[3:2] |PWDMOD |ADC Power-down Mode 506 * | | |Set this bit fields to select ADC power down mode when system power-down. 507 * | | |00 = ADC Deep power down mode. 508 * | | |01 = ADC Power down. 509 * | | |10 = ADC Standby mode. 510 * | | |11 = ADC Deep power down mode. 511 * | | |Note: Different PWDMOD has different power down/up sequence, in order to avoid ADC powering up with wrong sequence; user must keep PWMOD consistent each time in power down and start up 512 * |[19:8] |LDOSUT |ADC Internal LDO Start-up Time 513 * | | |Set this bit fields to control LDO start-up time 514 * | | |The minimum required LDO start-up time is 20us 515 * | | |LDO start-up time = (1/ADC_CLK) x LDOSUT. 516 * @var EADC_T::CALCTL 517 * Offset: 0x114 ADC Calibration Control Register 518 * --------------------------------------------------------------------------------------------------- 519 * |Bits |Field |Descriptions 520 * | :----: | :----: | :---- | 521 * |[1] |CALSTART |Calibration Functional Block Start 522 * | | |0 = Stops calibration functional block. 523 * | | |1 = Starts calibration functional block. 524 * | | |Note: This bit is set by SW and clear by HW after re-calibration finish 525 * |[2] |CALDONE |Calibration Functional Block Complete (Read Only) 526 * | | |0 = During a calibration. 527 * | | |1 = Calibration is completed. 528 * |[3] |CALSEL |Select Calibration Functional Block 529 * | | |0 = Load calibration word when calibration functional block is active. 530 * | | |1 = Execute calibration when calibration functional block is active. 531 * @var EADC_T::CALDWRD 532 * Offset: 0x118 ADC Calibration Load Word Register 533 * --------------------------------------------------------------------------------------------------- 534 * |Bits |Field |Descriptions 535 * | :----: | :----: | :---- | 536 * |[6:0] |CALWORD |Calibration Word Bits 537 * | | |Write to this register with the previous calibration word before load calibration action. 538 * | | |Read this register after calibration done. 539 * | | |Note: The calibration block contains two parts CALIBRATION and LOAD CALIBRATION; if the calibration block configure as CALIBRATION; then this register represent the result of calibration when calibration is completed; if configure as LOAD CALIBRATION ; configure this register before loading calibration action, after loading calibration complete, the laoded calibration word will apply to the ADC; while in loading calibration function the loaded value will not be equal to the original CALWORD until calibration is done. 540 */ 541 542 __I uint32_t DAT[19]; /*!< [0x0000~0x0048] ADC Data Register n for Sample Module n, n=0~18 */ 543 __I uint32_t CURDAT; /*!< [0x004c] ADC PDMA Current Transfer Data Register */ 544 __IO uint32_t CTL; /*!< [0x0050] ADC Control Register */ 545 __O uint32_t SWTRG; /*!< [0x0054] ADC Sample Module Software Start Register */ 546 __IO uint32_t PENDSTS; /*!< [0x0058] ADC Start of Conversion Pending Flag Register */ 547 __IO uint32_t OVSTS; /*!< [0x005c] ADC Sample Module Start of Conversion Overrun Flag Register */ 548 __I uint32_t RESERVE0[8]; 549 __IO uint32_t SCTL[19]; /*!< [0x0080~0x00c8] ADC Sample Module n Control Register, n=0~18 */ 550 __I uint32_t RESERVE1[1]; 551 __IO uint32_t INTSRC[4]; /*!< [0x00d0~0x00dc] ADC interrupt n Source Enable Control Register, n=0~3 */ 552 __IO uint32_t CMP[4]; /*!< [0x00e0~0x00ec] ADC Result Compare Register n, n=0~3 */ 553 __I uint32_t STATUS0; /*!< [0x00f0] ADC Status Register 0 */ 554 __I uint32_t STATUS1; /*!< [0x00f4] ADC Status Register 1 */ 555 __IO uint32_t STATUS2; /*!< [0x00f8] ADC Status Register 2 */ 556 __I uint32_t STATUS3; /*!< [0x00fc] ADC Status Register 3 */ 557 __I uint32_t DDAT[4]; /*!< [0x0100~0x010c] ADC Double Data Register n for Sample Module n, n=0~3 */ 558 __IO uint32_t PWRM; /*!< [0x0110] ADC Power Management Register */ 559 __IO uint32_t CALCTL; /*!< [0x0114] ADC Calibration Control Register */ 560 __IO uint32_t CALDWRD; /*!< [0x0118] ADC Calibration Load Word Register */ 561 __I uint32_t RESERVE2[5]; 562 __IO uint32_t PDMACTL; /*!< [0x0130] ADC PDMA Control Register */ 563 564 } EADC_T; 565 566 /** 567 @addtogroup EADC_CONST EADC Bit Field Definition 568 Constant Definitions for EADC Controller 569 @{ 570 */ 571 572 #define EADC_DAT_RESULT_Pos (0) /*!< EADC_T::DAT: RESULT Position */ 573 #define EADC_DAT_RESULT_Msk (0xfffful << EADC_DAT_RESULT_Pos) /*!< EADC_T::DAT: RESULT Mask */ 574 575 #define EADC_DAT_OV_Pos (16) /*!< EADC_T::DAT: OV Position */ 576 #define EADC_DAT_OV_Msk (0x1ul << EADC_DAT_OV_Pos) /*!< EADC_T::DAT: OV Mask */ 577 578 #define EADC_DAT_VALID_Pos (17) /*!< EADC_T::DAT: VALID Position */ 579 #define EADC_DAT_VALID_Msk (0x1ul << EADC_DAT_VALID_Pos) /*!< EADC_T::DAT: VALID Mask */ 580 581 #define EADC_DAT0_RESULT_Pos (0) /*!< EADC_T::DAT0: RESULT Position */ 582 #define EADC_DAT0_RESULT_Msk (0xfffful << EADC_DAT0_RESULT_Pos) /*!< EADC_T::DAT0: RESULT Mask */ 583 584 #define EADC_DAT0_OV_Pos (16) /*!< EADC_T::DAT0: OV Position */ 585 #define EADC_DAT0_OV_Msk (0x1ul << EADC_DAT0_OV_Pos) /*!< EADC_T::DAT0: OV Mask */ 586 587 #define EADC_DAT0_VALID_Pos (17) /*!< EADC_T::DAT0: VALID Position */ 588 #define EADC_DAT0_VALID_Msk (0x1ul << EADC_DAT0_VALID_Pos) /*!< EADC_T::DAT0: VALID Mask */ 589 590 #define EADC_DAT1_RESULT_Pos (0) /*!< EADC_T::DAT1: RESULT Position */ 591 #define EADC_DAT1_RESULT_Msk (0xfffful << EADC_DAT1_RESULT_Pos) /*!< EADC_T::DAT1: RESULT Mask */ 592 593 #define EADC_DAT1_OV_Pos (16) /*!< EADC_T::DAT1: OV Position */ 594 #define EADC_DAT1_OV_Msk (0x1ul << EADC_DAT1_OV_Pos) /*!< EADC_T::DAT1: OV Mask */ 595 596 #define EADC_DAT1_VALID_Pos (17) /*!< EADC_T::DAT1: VALID Position */ 597 #define EADC_DAT1_VALID_Msk (0x1ul << EADC_DAT1_VALID_Pos) /*!< EADC_T::DAT1: VALID Mask */ 598 599 #define EADC_DAT2_RESULT_Pos (0) /*!< EADC_T::DAT2: RESULT Position */ 600 #define EADC_DAT2_RESULT_Msk (0xfffful << EADC_DAT2_RESULT_Pos) /*!< EADC_T::DAT2: RESULT Mask */ 601 602 #define EADC_DAT2_OV_Pos (16) /*!< EADC_T::DAT2: OV Position */ 603 #define EADC_DAT2_OV_Msk (0x1ul << EADC_DAT2_OV_Pos) /*!< EADC_T::DAT2: OV Mask */ 604 605 #define EADC_DAT2_VALID_Pos (17) /*!< EADC_T::DAT2: VALID Position */ 606 #define EADC_DAT2_VALID_Msk (0x1ul << EADC_DAT2_VALID_Pos) /*!< EADC_T::DAT2: VALID Mask */ 607 608 #define EADC_DAT3_RESULT_Pos (0) /*!< EADC_T::DAT3: RESULT Position */ 609 #define EADC_DAT3_RESULT_Msk (0xfffful << EADC_DAT3_RESULT_Pos) /*!< EADC_T::DAT3: RESULT Mask */ 610 611 #define EADC_DAT3_OV_Pos (16) /*!< EADC_T::DAT3: OV Position */ 612 #define EADC_DAT3_OV_Msk (0x1ul << EADC_DAT3_OV_Pos) /*!< EADC_T::DAT3: OV Mask */ 613 614 #define EADC_DAT3_VALID_Pos (17) /*!< EADC_T::DAT3: VALID Position */ 615 #define EADC_DAT3_VALID_Msk (0x1ul << EADC_DAT3_VALID_Pos) /*!< EADC_T::DAT3: VALID Mask */ 616 617 #define EADC_DAT4_RESULT_Pos (0) /*!< EADC_T::DAT4: RESULT Position */ 618 #define EADC_DAT4_RESULT_Msk (0xfffful << EADC_DAT4_RESULT_Pos) /*!< EADC_T::DAT4: RESULT Mask */ 619 620 #define EADC_DAT4_OV_Pos (16) /*!< EADC_T::DAT4: OV Position */ 621 #define EADC_DAT4_OV_Msk (0x1ul << EADC_DAT4_OV_Pos) /*!< EADC_T::DAT4: OV Mask */ 622 623 #define EADC_DAT4_VALID_Pos (17) /*!< EADC_T::DAT4: VALID Position */ 624 #define EADC_DAT4_VALID_Msk (0x1ul << EADC_DAT4_VALID_Pos) /*!< EADC_T::DAT4: VALID Mask */ 625 626 #define EADC_DAT5_RESULT_Pos (0) /*!< EADC_T::DAT5: RESULT Position */ 627 #define EADC_DAT5_RESULT_Msk (0xfffful << EADC_DAT5_RESULT_Pos) /*!< EADC_T::DAT5: RESULT Mask */ 628 629 #define EADC_DAT5_OV_Pos (16) /*!< EADC_T::DAT5: OV Position */ 630 #define EADC_DAT5_OV_Msk (0x1ul << EADC_DAT5_OV_Pos) /*!< EADC_T::DAT5: OV Mask */ 631 632 #define EADC_DAT5_VALID_Pos (17) /*!< EADC_T::DAT5: VALID Position */ 633 #define EADC_DAT5_VALID_Msk (0x1ul << EADC_DAT5_VALID_Pos) /*!< EADC_T::DAT5: VALID Mask */ 634 635 #define EADC_DAT6_RESULT_Pos (0) /*!< EADC_T::DAT6: RESULT Position */ 636 #define EADC_DAT6_RESULT_Msk (0xfffful << EADC_DAT6_RESULT_Pos) /*!< EADC_T::DAT6: RESULT Mask */ 637 638 #define EADC_DAT6_OV_Pos (16) /*!< EADC_T::DAT6: OV Position */ 639 #define EADC_DAT6_OV_Msk (0x1ul << EADC_DAT6_OV_Pos) /*!< EADC_T::DAT6: OV Mask */ 640 641 #define EADC_DAT6_VALID_Pos (17) /*!< EADC_T::DAT6: VALID Position */ 642 #define EADC_DAT6_VALID_Msk (0x1ul << EADC_DAT6_VALID_Pos) /*!< EADC_T::DAT6: VALID Mask */ 643 644 #define EADC_DAT7_RESULT_Pos (0) /*!< EADC_T::DAT7: RESULT Position */ 645 #define EADC_DAT7_RESULT_Msk (0xfffful << EADC_DAT7_RESULT_Pos) /*!< EADC_T::DAT7: RESULT Mask */ 646 647 #define EADC_DAT7_OV_Pos (16) /*!< EADC_T::DAT7: OV Position */ 648 #define EADC_DAT7_OV_Msk (0x1ul << EADC_DAT7_OV_Pos) /*!< EADC_T::DAT7: OV Mask */ 649 650 #define EADC_DAT7_VALID_Pos (17) /*!< EADC_T::DAT7: VALID Position */ 651 #define EADC_DAT7_VALID_Msk (0x1ul << EADC_DAT7_VALID_Pos) /*!< EADC_T::DAT7: VALID Mask */ 652 653 #define EADC_DAT8_RESULT_Pos (0) /*!< EADC_T::DAT8: RESULT Position */ 654 #define EADC_DAT8_RESULT_Msk (0xfffful << EADC_DAT8_RESULT_Pos) /*!< EADC_T::DAT8: RESULT Mask */ 655 656 #define EADC_DAT8_OV_Pos (16) /*!< EADC_T::DAT8: OV Position */ 657 #define EADC_DAT8_OV_Msk (0x1ul << EADC_DAT8_OV_Pos) /*!< EADC_T::DAT8: OV Mask */ 658 659 #define EADC_DAT8_VALID_Pos (17) /*!< EADC_T::DAT8: VALID Position */ 660 #define EADC_DAT8_VALID_Msk (0x1ul << EADC_DAT8_VALID_Pos) /*!< EADC_T::DAT8: VALID Mask */ 661 662 #define EADC_DAT9_RESULT_Pos (0) /*!< EADC_T::DAT9: RESULT Position */ 663 #define EADC_DAT9_RESULT_Msk (0xfffful << EADC_DAT9_RESULT_Pos) /*!< EADC_T::DAT9: RESULT Mask */ 664 665 #define EADC_DAT9_OV_Pos (16) /*!< EADC_T::DAT9: OV Position */ 666 #define EADC_DAT9_OV_Msk (0x1ul << EADC_DAT9_OV_Pos) /*!< EADC_T::DAT9: OV Mask */ 667 668 #define EADC_DAT9_VALID_Pos (17) /*!< EADC_T::DAT9: VALID Position */ 669 #define EADC_DAT9_VALID_Msk (0x1ul << EADC_DAT9_VALID_Pos) /*!< EADC_T::DAT9: VALID Mask */ 670 671 #define EADC_DAT10_RESULT_Pos (0) /*!< EADC_T::DAT10: RESULT Position */ 672 #define EADC_DAT10_RESULT_Msk (0xfffful << EADC_DAT10_RESULT_Pos) /*!< EADC_T::DAT10: RESULT Mask */ 673 674 #define EADC_DAT10_OV_Pos (16) /*!< EADC_T::DAT10: OV Position */ 675 #define EADC_DAT10_OV_Msk (0x1ul << EADC_DAT10_OV_Pos) /*!< EADC_T::DAT10: OV Mask */ 676 677 #define EADC_DAT10_VALID_Pos (17) /*!< EADC_T::DAT10: VALID Position */ 678 #define EADC_DAT10_VALID_Msk (0x1ul << EADC_DAT10_VALID_Pos) /*!< EADC_T::DAT10: VALID Mask */ 679 680 #define EADC_DAT11_RESULT_Pos (0) /*!< EADC_T::DAT11: RESULT Position */ 681 #define EADC_DAT11_RESULT_Msk (0xfffful << EADC_DAT11_RESULT_Pos) /*!< EADC_T::DAT11: RESULT Mask */ 682 683 #define EADC_DAT11_OV_Pos (16) /*!< EADC_T::DAT11: OV Position */ 684 #define EADC_DAT11_OV_Msk (0x1ul << EADC_DAT11_OV_Pos) /*!< EADC_T::DAT11: OV Mask */ 685 686 #define EADC_DAT11_VALID_Pos (17) /*!< EADC_T::DAT11: VALID Position */ 687 #define EADC_DAT11_VALID_Msk (0x1ul << EADC_DAT11_VALID_Pos) /*!< EADC_T::DAT11: VALID Mask */ 688 689 #define EADC_DAT12_RESULT_Pos (0) /*!< EADC_T::DAT12: RESULT Position */ 690 #define EADC_DAT12_RESULT_Msk (0xfffful << EADC_DAT12_RESULT_Pos) /*!< EADC_T::DAT12: RESULT Mask */ 691 692 #define EADC_DAT12_OV_Pos (16) /*!< EADC_T::DAT12: OV Position */ 693 #define EADC_DAT12_OV_Msk (0x1ul << EADC_DAT12_OV_Pos) /*!< EADC_T::DAT12: OV Mask */ 694 695 #define EADC_DAT12_VALID_Pos (17) /*!< EADC_T::DAT12: VALID Position */ 696 #define EADC_DAT12_VALID_Msk (0x1ul << EADC_DAT12_VALID_Pos) /*!< EADC_T::DAT12: VALID Mask */ 697 698 #define EADC_DAT13_RESULT_Pos (0) /*!< EADC_T::DAT13: RESULT Position */ 699 #define EADC_DAT13_RESULT_Msk (0xfffful << EADC_DAT13_RESULT_Pos) /*!< EADC_T::DAT13: RESULT Mask */ 700 701 #define EADC_DAT13_OV_Pos (16) /*!< EADC_T::DAT13: OV Position */ 702 #define EADC_DAT13_OV_Msk (0x1ul << EADC_DAT13_OV_Pos) /*!< EADC_T::DAT13: OV Mask */ 703 704 #define EADC_DAT13_VALID_Pos (17) /*!< EADC_T::DAT13: VALID Position */ 705 #define EADC_DAT13_VALID_Msk (0x1ul << EADC_DAT13_VALID_Pos) /*!< EADC_T::DAT13: VALID Mask */ 706 707 #define EADC_DAT14_RESULT_Pos (0) /*!< EADC_T::DAT14: RESULT Position */ 708 #define EADC_DAT14_RESULT_Msk (0xfffful << EADC_DAT14_RESULT_Pos) /*!< EADC_T::DAT14: RESULT Mask */ 709 710 #define EADC_DAT14_OV_Pos (16) /*!< EADC_T::DAT14: OV Position */ 711 #define EADC_DAT14_OV_Msk (0x1ul << EADC_DAT14_OV_Pos) /*!< EADC_T::DAT14: OV Mask */ 712 713 #define EADC_DAT14_VALID_Pos (17) /*!< EADC_T::DAT14: VALID Position */ 714 #define EADC_DAT14_VALID_Msk (0x1ul << EADC_DAT14_VALID_Pos) /*!< EADC_T::DAT14: VALID Mask */ 715 716 #define EADC_DAT15_RESULT_Pos (0) /*!< EADC_T::DAT15: RESULT Position */ 717 #define EADC_DAT15_RESULT_Msk (0xfffful << EADC_DAT15_RESULT_Pos) /*!< EADC_T::DAT15: RESULT Mask */ 718 719 #define EADC_DAT15_OV_Pos (16) /*!< EADC_T::DAT15: OV Position */ 720 #define EADC_DAT15_OV_Msk (0x1ul << EADC_DAT15_OV_Pos) /*!< EADC_T::DAT15: OV Mask */ 721 722 #define EADC_DAT15_VALID_Pos (17) /*!< EADC_T::DAT15: VALID Position */ 723 #define EADC_DAT15_VALID_Msk (0x1ul << EADC_DAT15_VALID_Pos) /*!< EADC_T::DAT15: VALID Mask */ 724 725 #define EADC_DAT16_RESULT_Pos (0) /*!< EADC_T::DAT16: RESULT Position */ 726 #define EADC_DAT16_RESULT_Msk (0xfffful << EADC_DAT16_RESULT_Pos) /*!< EADC_T::DAT16: RESULT Mask */ 727 728 #define EADC_DAT16_OV_Pos (16) /*!< EADC_T::DAT16: OV Position */ 729 #define EADC_DAT16_OV_Msk (0x1ul << EADC_DAT16_OV_Pos) /*!< EADC_T::DAT16: OV Mask */ 730 731 #define EADC_DAT16_VALID_Pos (17) /*!< EADC_T::DAT16: VALID Position */ 732 #define EADC_DAT16_VALID_Msk (0x1ul << EADC_DAT16_VALID_Pos) /*!< EADC_T::DAT16: VALID Mask */ 733 734 #define EADC_DAT17_RESULT_Pos (0) /*!< EADC_T::DAT17: RESULT Position */ 735 #define EADC_DAT17_RESULT_Msk (0xfffful << EADC_DAT17_RESULT_Pos) /*!< EADC_T::DAT17: RESULT Mask */ 736 737 #define EADC_DAT17_OV_Pos (16) /*!< EADC_T::DAT17: OV Position */ 738 #define EADC_DAT17_OV_Msk (0x1ul << EADC_DAT17_OV_Pos) /*!< EADC_T::DAT17: OV Mask */ 739 740 #define EADC_DAT17_VALID_Pos (17) /*!< EADC_T::DAT17: VALID Position */ 741 #define EADC_DAT17_VALID_Msk (0x1ul << EADC_DAT17_VALID_Pos) /*!< EADC_T::DAT17: VALID Mask */ 742 743 #define EADC_DAT18_RESULT_Pos (0) /*!< EADC_T::DAT18: RESULT Position */ 744 #define EADC_DAT18_RESULT_Msk (0xfffful << EADC_DAT18_RESULT_Pos) /*!< EADC_T::DAT18: RESULT Mask */ 745 746 #define EADC_DAT18_OV_Pos (16) /*!< EADC_T::DAT18: OV Position */ 747 #define EADC_DAT18_OV_Msk (0x1ul << EADC_DAT18_OV_Pos) /*!< EADC_T::DAT18: OV Mask */ 748 749 #define EADC_DAT18_VALID_Pos (17) /*!< EADC_T::DAT18: VALID Position */ 750 #define EADC_DAT18_VALID_Msk (0x1ul << EADC_DAT18_VALID_Pos) /*!< EADC_T::DAT18: VALID Mask */ 751 752 #define EADC_CURDAT_CURDAT_Pos (0) /*!< EADC_T::CURDAT: CURDAT Position */ 753 #define EADC_CURDAT_CURDAT_Msk (0x3fffful << EADC_CURDAT_CURDAT_Pos) /*!< EADC_T::CURDAT: CURDAT Mask */ 754 755 #define EADC_CTL_ADCEN_Pos (0) /*!< EADC_T::CTL: ADCEN Position */ 756 #define EADC_CTL_ADCEN_Msk (0x1ul << EADC_CTL_ADCEN_Pos) /*!< EADC_T::CTL: ADCEN Mask */ 757 758 #define EADC_CTL_ADCRST_Pos (1) /*!< EADC_T::CTL: ADCRST Position */ 759 #define EADC_CTL_ADCRST_Msk (0x1ul << EADC_CTL_ADCRST_Pos) /*!< EADC_T::CTL: ADCRST Mask */ 760 761 #define EADC_CTL_ADCIEN0_Pos (2) /*!< EADC_T::CTL: ADCIEN0 Position */ 762 #define EADC_CTL_ADCIEN0_Msk (0x1ul << EADC_CTL_ADCIEN0_Pos) /*!< EADC_T::CTL: ADCIEN0 Mask */ 763 764 #define EADC_CTL_ADCIEN1_Pos (3) /*!< EADC_T::CTL: ADCIEN1 Position */ 765 #define EADC_CTL_ADCIEN1_Msk (0x1ul << EADC_CTL_ADCIEN1_Pos) /*!< EADC_T::CTL: ADCIEN1 Mask */ 766 767 #define EADC_CTL_ADCIEN2_Pos (4) /*!< EADC_T::CTL: ADCIEN2 Position */ 768 #define EADC_CTL_ADCIEN2_Msk (0x1ul << EADC_CTL_ADCIEN2_Pos) /*!< EADC_T::CTL: ADCIEN2 Mask */ 769 770 #define EADC_CTL_ADCIEN3_Pos (5) /*!< EADC_T::CTL: ADCIEN3 Position */ 771 #define EADC_CTL_ADCIEN3_Msk (0x1ul << EADC_CTL_ADCIEN3_Pos) /*!< EADC_T::CTL: ADCIEN3 Mask */ 772 773 #define EADC_CTL_RESSEL_Pos (6) /*!< EADC_T::CTL: RESSEL Position */ 774 #define EADC_CTL_RESSEL_Msk (0x3ul << EADC_CTL_RESSEL_Pos) /*!< EADC_T::CTL: RESSEL Mask */ 775 776 #define EADC_CTL_DIFFEN_Pos (8) /*!< EADC_T::CTL: DIFFEN Position */ 777 #define EADC_CTL_DIFFEN_Msk (0x1ul << EADC_CTL_DIFFEN_Pos) /*!< EADC_T::CTL: DIFFEN Mask */ 778 779 #define EADC_CTL_DMOF_Pos (9) /*!< EADC_T::CTL: DMOF Position */ 780 #define EADC_CTL_DMOF_Msk (0x1ul << EADC_CTL_DMOF_Pos) /*!< EADC_T::CTL: DMOF Mask */ 781 782 #define EADC_SWTRG_SWTRG_Pos (0) /*!< EADC_T::SWTRG: SWTRG Position */ 783 #define EADC_SWTRG_SWTRG_Msk (0x7fffful << EADC_SWTRG_SWTRG_Pos) /*!< EADC_T::SWTRG: SWTRG Mask */ 784 785 #define EADC_PENDSTS_STPF_Pos (0) /*!< EADC_T::PENDSTS: STPF Position */ 786 #define EADC_PENDSTS_STPF_Msk (0x7fffful << EADC_PENDSTS_STPF_Pos) /*!< EADC_T::PENDSTS: STPF Mask */ 787 788 #define EADC_OVSTS_SPOVF_Pos (0) /*!< EADC_T::OVSTS: SPOVF Position */ 789 #define EADC_OVSTS_SPOVF_Msk (0x7fffful << EADC_OVSTS_SPOVF_Pos) /*!< EADC_T::OVSTS: SPOVF Mask */ 790 791 #define EADC_SCTL_CHSEL_Pos (0) /*!< EADC_T::SCTL: CHSEL Position */ 792 #define EADC_SCTL_CHSEL_Msk (0xful << EADC_SCTL_CHSEL_Pos) /*!< EADC_T::SCTL: CHSEL Mask */ 793 794 #define EADC_SCTL_EXTREN_Pos (4) /*!< EADC_T::SCTL: EXTREN Position */ 795 #define EADC_SCTL_EXTREN_Msk (0x1ul << EADC_SCTL_EXTREN_Pos) /*!< EADC_T::SCTL: EXTREN Mask */ 796 797 #define EADC_SCTL_EXTFEN_Pos (5) /*!< EADC_T::SCTL: EXTFEN Position */ 798 #define EADC_SCTL_EXTFEN_Msk (0x1ul << EADC_SCTL_EXTFEN_Pos) /*!< EADC_T::SCTL: EXTFEN Mask */ 799 800 #define EADC_SCTL_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL: TRGDLYDIV Position */ 801 #define EADC_SCTL_TRGDLYDIV_Msk (0x3ul << EADC_SCTL_TRGDLYDIV_Pos) /*!< EADC_T::SCTL: TRGDLYDIV Mask */ 802 803 #define EADC_SCTL_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL: TRGDLYCNT Position */ 804 #define EADC_SCTL_TRGDLYCNT_Msk (0xfful << EADC_SCTL_TRGDLYCNT_Pos) /*!< EADC_T::SCTL: TRGDLYCNT Mask */ 805 806 #define EADC_SCTL_TRGSEL_Pos (16) /*!< EADC_T::SCTL: TRGSEL Position */ 807 #define EADC_SCTL_TRGSEL_Msk (0x1ful << EADC_SCTL_TRGSEL_Pos) /*!< EADC_T::SCTL: TRGSEL Mask */ 808 809 #define EADC_SCTL_INTPOS_Pos (22) /*!< EADC_T::SCTL: INTPOS Position */ 810 #define EADC_SCTL_INTPOS_Msk (0x1ul << EADC_SCTL_INTPOS_Pos) /*!< EADC_T::SCTL: INTPOS Mask */ 811 812 #define EADC_SCTL_DBMEN_Pos (23) /*!< EADC_T::SCTL: DBMEN Position */ 813 #define EADC_SCTL_DBMEN_Msk (0x1ul << EADC_SCTL_DBMEN_Pos) /*!< EADC_T::SCTL: DBMEN Mask */ 814 815 #define EADC_SCTL_EXTSMPT_Pos (24) /*!< EADC_T::SCTL: EXTSMPT Position */ 816 #define EADC_SCTL_EXTSMPT_Msk (0xfful << EADC_SCTL_EXTSMPT_Pos) /*!< EADC_T::SCTL: EXTSMPT Mask */ 817 818 #define EADC_SCTL0_CHSEL_Pos (0) /*!< EADC_T::SCTL0: CHSEL Position */ 819 #define EADC_SCTL0_CHSEL_Msk (0xful << EADC_SCTL0_CHSEL_Pos) /*!< EADC_T::SCTL0: CHSEL Mask */ 820 821 #define EADC_SCTL0_EXTREN_Pos (4) /*!< EADC_T::SCTL0: EXTREN Position */ 822 #define EADC_SCTL0_EXTREN_Msk (0x1ul << EADC_SCTL0_EXTREN_Pos) /*!< EADC_T::SCTL0: EXTREN Mask */ 823 824 #define EADC_SCTL0_EXTFEN_Pos (5) /*!< EADC_T::SCTL0: EXTFEN Position */ 825 #define EADC_SCTL0_EXTFEN_Msk (0x1ul << EADC_SCTL0_EXTFEN_Pos) /*!< EADC_T::SCTL0: EXTFEN Mask */ 826 827 #define EADC_SCTL0_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL0: TRGDLYDIV Position */ 828 #define EADC_SCTL0_TRGDLYDIV_Msk (0x3ul << EADC_SCTL0_TRGDLYDIV_Pos) /*!< EADC_T::SCTL0: TRGDLYDIV Mask */ 829 830 #define EADC_SCTL0_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL0: TRGDLYCNT Position */ 831 #define EADC_SCTL0_TRGDLYCNT_Msk (0xfful << EADC_SCTL0_TRGDLYCNT_Pos) /*!< EADC_T::SCTL0: TRGDLYCNT Mask */ 832 833 #define EADC_SCTL0_TRGSEL_Pos (16) /*!< EADC_T::SCTL0: TRGSEL Position */ 834 #define EADC_SCTL0_TRGSEL_Msk (0x1ful << EADC_SCTL0_TRGSEL_Pos) /*!< EADC_T::SCTL0: TRGSEL Mask */ 835 836 #define EADC_SCTL0_INTPOS_Pos (22) /*!< EADC_T::SCTL0: INTPOS Position */ 837 #define EADC_SCTL0_INTPOS_Msk (0x1ul << EADC_SCTL0_INTPOS_Pos) /*!< EADC_T::SCTL0: INTPOS Mask */ 838 839 #define EADC_SCTL0_DBMEN_Pos (23) /*!< EADC_T::SCTL0: DBMEN Position */ 840 #define EADC_SCTL0_DBMEN_Msk (0x1ul << EADC_SCTL0_DBMEN_Pos) /*!< EADC_T::SCTL0: DBMEN Mask */ 841 842 #define EADC_SCTL0_EXTSMPT_Pos (24) /*!< EADC_T::SCTL0: EXTSMPT Position */ 843 #define EADC_SCTL0_EXTSMPT_Msk (0xfful << EADC_SCTL0_EXTSMPT_Pos) /*!< EADC_T::SCTL0: EXTSMPT Mask */ 844 845 #define EADC_SCTL1_CHSEL_Pos (0) /*!< EADC_T::SCTL1: CHSEL Position */ 846 #define EADC_SCTL1_CHSEL_Msk (0xful << EADC_SCTL1_CHSEL_Pos) /*!< EADC_T::SCTL1: CHSEL Mask */ 847 848 #define EADC_SCTL1_EXTREN_Pos (4) /*!< EADC_T::SCTL1: EXTREN Position */ 849 #define EADC_SCTL1_EXTREN_Msk (0x1ul << EADC_SCTL1_EXTREN_Pos) /*!< EADC_T::SCTL1: EXTREN Mask */ 850 851 #define EADC_SCTL1_EXTFEN_Pos (5) /*!< EADC_T::SCTL1: EXTFEN Position */ 852 #define EADC_SCTL1_EXTFEN_Msk (0x1ul << EADC_SCTL1_EXTFEN_Pos) /*!< EADC_T::SCTL1: EXTFEN Mask */ 853 854 #define EADC_SCTL1_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL1: TRGDLYDIV Position */ 855 #define EADC_SCTL1_TRGDLYDIV_Msk (0x3ul << EADC_SCTL1_TRGDLYDIV_Pos) /*!< EADC_T::SCTL1: TRGDLYDIV Mask */ 856 857 #define EADC_SCTL1_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL1: TRGDLYCNT Position */ 858 #define EADC_SCTL1_TRGDLYCNT_Msk (0xfful << EADC_SCTL1_TRGDLYCNT_Pos) /*!< EADC_T::SCTL1: TRGDLYCNT Mask */ 859 860 #define EADC_SCTL1_TRGSEL_Pos (16) /*!< EADC_T::SCTL1: TRGSEL Position */ 861 #define EADC_SCTL1_TRGSEL_Msk (0x1ful << EADC_SCTL1_TRGSEL_Pos) /*!< EADC_T::SCTL1: TRGSEL Mask */ 862 863 #define EADC_SCTL1_INTPOS_Pos (22) /*!< EADC_T::SCTL1: INTPOS Position */ 864 #define EADC_SCTL1_INTPOS_Msk (0x1ul << EADC_SCTL1_INTPOS_Pos) /*!< EADC_T::SCTL1: INTPOS Mask */ 865 866 #define EADC_SCTL1_DBMEN_Pos (23) /*!< EADC_T::SCTL1: DBMEN Position */ 867 #define EADC_SCTL1_DBMEN_Msk (0x1ul << EADC_SCTL1_DBMEN_Pos) /*!< EADC_T::SCTL1: DBMEN Mask */ 868 869 #define EADC_SCTL1_EXTSMPT_Pos (24) /*!< EADC_T::SCTL1: EXTSMPT Position */ 870 #define EADC_SCTL1_EXTSMPT_Msk (0xfful << EADC_SCTL1_EXTSMPT_Pos) /*!< EADC_T::SCTL1: EXTSMPT Mask */ 871 872 #define EADC_SCTL2_CHSEL_Pos (0) /*!< EADC_T::SCTL2: CHSEL Position */ 873 #define EADC_SCTL2_CHSEL_Msk (0xful << EADC_SCTL2_CHSEL_Pos) /*!< EADC_T::SCTL2: CHSEL Mask */ 874 875 #define EADC_SCTL2_EXTREN_Pos (4) /*!< EADC_T::SCTL2: EXTREN Position */ 876 #define EADC_SCTL2_EXTREN_Msk (0x1ul << EADC_SCTL2_EXTREN_Pos) /*!< EADC_T::SCTL2: EXTREN Mask */ 877 878 #define EADC_SCTL2_EXTFEN_Pos (5) /*!< EADC_T::SCTL2: EXTFEN Position */ 879 #define EADC_SCTL2_EXTFEN_Msk (0x1ul << EADC_SCTL2_EXTFEN_Pos) /*!< EADC_T::SCTL2: EXTFEN Mask */ 880 881 #define EADC_SCTL2_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL2: TRGDLYDIV Position */ 882 #define EADC_SCTL2_TRGDLYDIV_Msk (0x3ul << EADC_SCTL2_TRGDLYDIV_Pos) /*!< EADC_T::SCTL2: TRGDLYDIV Mask */ 883 884 #define EADC_SCTL2_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL2: TRGDLYCNT Position */ 885 #define EADC_SCTL2_TRGDLYCNT_Msk (0xfful << EADC_SCTL2_TRGDLYCNT_Pos) /*!< EADC_T::SCTL2: TRGDLYCNT Mask */ 886 887 #define EADC_SCTL2_TRGSEL_Pos (16) /*!< EADC_T::SCTL2: TRGSEL Position */ 888 #define EADC_SCTL2_TRGSEL_Msk (0x1ful << EADC_SCTL2_TRGSEL_Pos) /*!< EADC_T::SCTL2: TRGSEL Mask */ 889 890 #define EADC_SCTL2_INTPOS_Pos (22) /*!< EADC_T::SCTL2: INTPOS Position */ 891 #define EADC_SCTL2_INTPOS_Msk (0x1ul << EADC_SCTL2_INTPOS_Pos) /*!< EADC_T::SCTL2: INTPOS Mask */ 892 893 #define EADC_SCTL2_DBMEN_Pos (23) /*!< EADC_T::SCTL2: DBMEN Position */ 894 #define EADC_SCTL2_DBMEN_Msk (0x1ul << EADC_SCTL2_DBMEN_Pos) /*!< EADC_T::SCTL2: DBMEN Mask */ 895 896 #define EADC_SCTL2_EXTSMPT_Pos (24) /*!< EADC_T::SCTL2: EXTSMPT Position */ 897 #define EADC_SCTL2_EXTSMPT_Msk (0xfful << EADC_SCTL2_EXTSMPT_Pos) /*!< EADC_T::SCTL2: EXTSMPT Mask */ 898 899 #define EADC_SCTL3_CHSEL_Pos (0) /*!< EADC_T::SCTL3: CHSEL Position */ 900 #define EADC_SCTL3_CHSEL_Msk (0xful << EADC_SCTL3_CHSEL_Pos) /*!< EADC_T::SCTL3: CHSEL Mask */ 901 902 #define EADC_SCTL3_EXTREN_Pos (4) /*!< EADC_T::SCTL3: EXTREN Position */ 903 #define EADC_SCTL3_EXTREN_Msk (0x1ul << EADC_SCTL3_EXTREN_Pos) /*!< EADC_T::SCTL3: EXTREN Mask */ 904 905 #define EADC_SCTL3_EXTFEN_Pos (5) /*!< EADC_T::SCTL3: EXTFEN Position */ 906 #define EADC_SCTL3_EXTFEN_Msk (0x1ul << EADC_SCTL3_EXTFEN_Pos) /*!< EADC_T::SCTL3: EXTFEN Mask */ 907 908 #define EADC_SCTL3_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL3: TRGDLYDIV Position */ 909 #define EADC_SCTL3_TRGDLYDIV_Msk (0x3ul << EADC_SCTL3_TRGDLYDIV_Pos) /*!< EADC_T::SCTL3: TRGDLYDIV Mask */ 910 911 #define EADC_SCTL3_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL3: TRGDLYCNT Position */ 912 #define EADC_SCTL3_TRGDLYCNT_Msk (0xfful << EADC_SCTL3_TRGDLYCNT_Pos) /*!< EADC_T::SCTL3: TRGDLYCNT Mask */ 913 914 #define EADC_SCTL3_TRGSEL_Pos (16) /*!< EADC_T::SCTL3: TRGSEL Position */ 915 #define EADC_SCTL3_TRGSEL_Msk (0x1ful << EADC_SCTL3_TRGSEL_Pos) /*!< EADC_T::SCTL3: TRGSEL Mask */ 916 917 #define EADC_SCTL3_INTPOS_Pos (22) /*!< EADC_T::SCTL3: INTPOS Position */ 918 #define EADC_SCTL3_INTPOS_Msk (0x1ul << EADC_SCTL3_INTPOS_Pos) /*!< EADC_T::SCTL3: INTPOS Mask */ 919 920 #define EADC_SCTL3_DBMEN_Pos (23) /*!< EADC_T::SCTL3: DBMEN Position */ 921 #define EADC_SCTL3_DBMEN_Msk (0x1ul << EADC_SCTL3_DBMEN_Pos) /*!< EADC_T::SCTL3: DBMEN Mask */ 922 923 #define EADC_SCTL3_EXTSMPT_Pos (24) /*!< EADC_T::SCTL3: EXTSMPT Position */ 924 #define EADC_SCTL3_EXTSMPT_Msk (0xfful << EADC_SCTL3_EXTSMPT_Pos) /*!< EADC_T::SCTL3: EXTSMPT Mask */ 925 926 #define EADC_SCTL4_CHSEL_Pos (0) /*!< EADC_T::SCTL4: CHSEL Position */ 927 #define EADC_SCTL4_CHSEL_Msk (0xful << EADC_SCTL4_CHSEL_Pos) /*!< EADC_T::SCTL4: CHSEL Mask */ 928 929 #define EADC_SCTL4_EXTREN_Pos (4) /*!< EADC_T::SCTL4: EXTREN Position */ 930 #define EADC_SCTL4_EXTREN_Msk (0x1ul << EADC_SCTL4_EXTREN_Pos) /*!< EADC_T::SCTL4: EXTREN Mask */ 931 932 #define EADC_SCTL4_EXTFEN_Pos (5) /*!< EADC_T::SCTL4: EXTFEN Position */ 933 #define EADC_SCTL4_EXTFEN_Msk (0x1ul << EADC_SCTL4_EXTFEN_Pos) /*!< EADC_T::SCTL4: EXTFEN Mask */ 934 935 #define EADC_SCTL4_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL4: TRGDLYDIV Position */ 936 #define EADC_SCTL4_TRGDLYDIV_Msk (0x3ul << EADC_SCTL4_TRGDLYDIV_Pos) /*!< EADC_T::SCTL4: TRGDLYDIV Mask */ 937 938 #define EADC_SCTL4_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL4: TRGDLYCNT Position */ 939 #define EADC_SCTL4_TRGDLYCNT_Msk (0xfful << EADC_SCTL4_TRGDLYCNT_Pos) /*!< EADC_T::SCTL4: TRGDLYCNT Mask */ 940 941 #define EADC_SCTL4_TRGSEL_Pos (16) /*!< EADC_T::SCTL4: TRGSEL Position */ 942 #define EADC_SCTL4_TRGSEL_Msk (0x1ful << EADC_SCTL4_TRGSEL_Pos) /*!< EADC_T::SCTL4: TRGSEL Mask */ 943 944 #define EADC_SCTL4_INTPOS_Pos (22) /*!< EADC_T::SCTL4: INTPOS Position */ 945 #define EADC_SCTL4_INTPOS_Msk (0x1ul << EADC_SCTL4_INTPOS_Pos) /*!< EADC_T::SCTL4: INTPOS Mask */ 946 947 #define EADC_SCTL4_EXTSMPT_Pos (24) /*!< EADC_T::SCTL4: EXTSMPT Position */ 948 #define EADC_SCTL4_EXTSMPT_Msk (0xfful << EADC_SCTL4_EXTSMPT_Pos) /*!< EADC_T::SCTL4: EXTSMPT Mask */ 949 950 #define EADC_SCTL5_CHSEL_Pos (0) /*!< EADC_T::SCTL5: CHSEL Position */ 951 #define EADC_SCTL5_CHSEL_Msk (0xful << EADC_SCTL5_CHSEL_Pos) /*!< EADC_T::SCTL5: CHSEL Mask */ 952 953 #define EADC_SCTL5_EXTREN_Pos (4) /*!< EADC_T::SCTL5: EXTREN Position */ 954 #define EADC_SCTL5_EXTREN_Msk (0x1ul << EADC_SCTL5_EXTREN_Pos) /*!< EADC_T::SCTL5: EXTREN Mask */ 955 956 #define EADC_SCTL5_EXTFEN_Pos (5) /*!< EADC_T::SCTL5: EXTFEN Position */ 957 #define EADC_SCTL5_EXTFEN_Msk (0x1ul << EADC_SCTL5_EXTFEN_Pos) /*!< EADC_T::SCTL5: EXTFEN Mask */ 958 959 #define EADC_SCTL5_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL5: TRGDLYDIV Position */ 960 #define EADC_SCTL5_TRGDLYDIV_Msk (0x3ul << EADC_SCTL5_TRGDLYDIV_Pos) /*!< EADC_T::SCTL5: TRGDLYDIV Mask */ 961 962 #define EADC_SCTL5_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL5: TRGDLYCNT Position */ 963 #define EADC_SCTL5_TRGDLYCNT_Msk (0xfful << EADC_SCTL5_TRGDLYCNT_Pos) /*!< EADC_T::SCTL5: TRGDLYCNT Mask */ 964 965 #define EADC_SCTL5_TRGSEL_Pos (16) /*!< EADC_T::SCTL5: TRGSEL Position */ 966 #define EADC_SCTL5_TRGSEL_Msk (0x1ful << EADC_SCTL5_TRGSEL_Pos) /*!< EADC_T::SCTL5: TRGSEL Mask */ 967 968 #define EADC_SCTL5_INTPOS_Pos (22) /*!< EADC_T::SCTL5: INTPOS Position */ 969 #define EADC_SCTL5_INTPOS_Msk (0x1ul << EADC_SCTL5_INTPOS_Pos) /*!< EADC_T::SCTL5: INTPOS Mask */ 970 971 #define EADC_SCTL5_EXTSMPT_Pos (24) /*!< EADC_T::SCTL5: EXTSMPT Position */ 972 #define EADC_SCTL5_EXTSMPT_Msk (0xfful << EADC_SCTL5_EXTSMPT_Pos) /*!< EADC_T::SCTL5: EXTSMPT Mask */ 973 974 #define EADC_SCTL6_CHSEL_Pos (0) /*!< EADC_T::SCTL6: CHSEL Position */ 975 #define EADC_SCTL6_CHSEL_Msk (0xful << EADC_SCTL6_CHSEL_Pos) /*!< EADC_T::SCTL6: CHSEL Mask */ 976 977 #define EADC_SCTL6_EXTREN_Pos (4) /*!< EADC_T::SCTL6: EXTREN Position */ 978 #define EADC_SCTL6_EXTREN_Msk (0x1ul << EADC_SCTL6_EXTREN_Pos) /*!< EADC_T::SCTL6: EXTREN Mask */ 979 980 #define EADC_SCTL6_EXTFEN_Pos (5) /*!< EADC_T::SCTL6: EXTFEN Position */ 981 #define EADC_SCTL6_EXTFEN_Msk (0x1ul << EADC_SCTL6_EXTFEN_Pos) /*!< EADC_T::SCTL6: EXTFEN Mask */ 982 983 #define EADC_SCTL6_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL6: TRGDLYDIV Position */ 984 #define EADC_SCTL6_TRGDLYDIV_Msk (0x3ul << EADC_SCTL6_TRGDLYDIV_Pos) /*!< EADC_T::SCTL6: TRGDLYDIV Mask */ 985 986 #define EADC_SCTL6_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL6: TRGDLYCNT Position */ 987 #define EADC_SCTL6_TRGDLYCNT_Msk (0xfful << EADC_SCTL6_TRGDLYCNT_Pos) /*!< EADC_T::SCTL6: TRGDLYCNT Mask */ 988 989 #define EADC_SCTL6_TRGSEL_Pos (16) /*!< EADC_T::SCTL6: TRGSEL Position */ 990 #define EADC_SCTL6_TRGSEL_Msk (0x1ful << EADC_SCTL6_TRGSEL_Pos) /*!< EADC_T::SCTL6: TRGSEL Mask */ 991 992 #define EADC_SCTL6_INTPOS_Pos (22) /*!< EADC_T::SCTL6: INTPOS Position */ 993 #define EADC_SCTL6_INTPOS_Msk (0x1ul << EADC_SCTL6_INTPOS_Pos) /*!< EADC_T::SCTL6: INTPOS Mask */ 994 995 #define EADC_SCTL6_EXTSMPT_Pos (24) /*!< EADC_T::SCTL6: EXTSMPT Position */ 996 #define EADC_SCTL6_EXTSMPT_Msk (0xfful << EADC_SCTL6_EXTSMPT_Pos) /*!< EADC_T::SCTL6: EXTSMPT Mask */ 997 998 #define EADC_SCTL7_CHSEL_Pos (0) /*!< EADC_T::SCTL7: CHSEL Position */ 999 #define EADC_SCTL7_CHSEL_Msk (0xful << EADC_SCTL7_CHSEL_Pos) /*!< EADC_T::SCTL7: CHSEL Mask */ 1000 1001 #define EADC_SCTL7_EXTREN_Pos (4) /*!< EADC_T::SCTL7: EXTREN Position */ 1002 #define EADC_SCTL7_EXTREN_Msk (0x1ul << EADC_SCTL7_EXTREN_Pos) /*!< EADC_T::SCTL7: EXTREN Mask */ 1003 1004 #define EADC_SCTL7_EXTFEN_Pos (5) /*!< EADC_T::SCTL7: EXTFEN Position */ 1005 #define EADC_SCTL7_EXTFEN_Msk (0x1ul << EADC_SCTL7_EXTFEN_Pos) /*!< EADC_T::SCTL7: EXTFEN Mask */ 1006 1007 #define EADC_SCTL7_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL7: TRGDLYDIV Position */ 1008 #define EADC_SCTL7_TRGDLYDIV_Msk (0x3ul << EADC_SCTL7_TRGDLYDIV_Pos) /*!< EADC_T::SCTL7: TRGDLYDIV Mask */ 1009 1010 #define EADC_SCTL7_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL7: TRGDLYCNT Position */ 1011 #define EADC_SCTL7_TRGDLYCNT_Msk (0xfful << EADC_SCTL7_TRGDLYCNT_Pos) /*!< EADC_T::SCTL7: TRGDLYCNT Mask */ 1012 1013 #define EADC_SCTL7_TRGSEL_Pos (16) /*!< EADC_T::SCTL7: TRGSEL Position */ 1014 #define EADC_SCTL7_TRGSEL_Msk (0x1ful << EADC_SCTL7_TRGSEL_Pos) /*!< EADC_T::SCTL7: TRGSEL Mask */ 1015 1016 #define EADC_SCTL7_INTPOS_Pos (22) /*!< EADC_T::SCTL7: INTPOS Position */ 1017 #define EADC_SCTL7_INTPOS_Msk (0x1ul << EADC_SCTL7_INTPOS_Pos) /*!< EADC_T::SCTL7: INTPOS Mask */ 1018 1019 #define EADC_SCTL7_EXTSMPT_Pos (24) /*!< EADC_T::SCTL7: EXTSMPT Position */ 1020 #define EADC_SCTL7_EXTSMPT_Msk (0xfful << EADC_SCTL7_EXTSMPT_Pos) /*!< EADC_T::SCTL7: EXTSMPT Mask */ 1021 1022 #define EADC_SCTL8_CHSEL_Pos (0) /*!< EADC_T::SCTL8: CHSEL Position */ 1023 #define EADC_SCTL8_CHSEL_Msk (0xful << EADC_SCTL8_CHSEL_Pos) /*!< EADC_T::SCTL8: CHSEL Mask */ 1024 1025 #define EADC_SCTL8_EXTREN_Pos (4) /*!< EADC_T::SCTL8: EXTREN Position */ 1026 #define EADC_SCTL8_EXTREN_Msk (0x1ul << EADC_SCTL8_EXTREN_Pos) /*!< EADC_T::SCTL8: EXTREN Mask */ 1027 1028 #define EADC_SCTL8_EXTFEN_Pos (5) /*!< EADC_T::SCTL8: EXTFEN Position */ 1029 #define EADC_SCTL8_EXTFEN_Msk (0x1ul << EADC_SCTL8_EXTFEN_Pos) /*!< EADC_T::SCTL8: EXTFEN Mask */ 1030 1031 #define EADC_SCTL8_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL8: TRGDLYDIV Position */ 1032 #define EADC_SCTL8_TRGDLYDIV_Msk (0x3ul << EADC_SCTL8_TRGDLYDIV_Pos) /*!< EADC_T::SCTL8: TRGDLYDIV Mask */ 1033 1034 #define EADC_SCTL8_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL8: TRGDLYCNT Position */ 1035 #define EADC_SCTL8_TRGDLYCNT_Msk (0xfful << EADC_SCTL8_TRGDLYCNT_Pos) /*!< EADC_T::SCTL8: TRGDLYCNT Mask */ 1036 1037 #define EADC_SCTL8_TRGSEL_Pos (16) /*!< EADC_T::SCTL8: TRGSEL Position */ 1038 #define EADC_SCTL8_TRGSEL_Msk (0x1ful << EADC_SCTL8_TRGSEL_Pos) /*!< EADC_T::SCTL8: TRGSEL Mask */ 1039 1040 #define EADC_SCTL8_INTPOS_Pos (22) /*!< EADC_T::SCTL8: INTPOS Position */ 1041 #define EADC_SCTL8_INTPOS_Msk (0x1ul << EADC_SCTL8_INTPOS_Pos) /*!< EADC_T::SCTL8: INTPOS Mask */ 1042 1043 #define EADC_SCTL8_EXTSMPT_Pos (24) /*!< EADC_T::SCTL8: EXTSMPT Position */ 1044 #define EADC_SCTL8_EXTSMPT_Msk (0xfful << EADC_SCTL8_EXTSMPT_Pos) /*!< EADC_T::SCTL8: EXTSMPT Mask */ 1045 1046 #define EADC_SCTL9_CHSEL_Pos (0) /*!< EADC_T::SCTL9: CHSEL Position */ 1047 #define EADC_SCTL9_CHSEL_Msk (0xful << EADC_SCTL9_CHSEL_Pos) /*!< EADC_T::SCTL9: CHSEL Mask */ 1048 1049 #define EADC_SCTL9_EXTREN_Pos (4) /*!< EADC_T::SCTL9: EXTREN Position */ 1050 #define EADC_SCTL9_EXTREN_Msk (0x1ul << EADC_SCTL9_EXTREN_Pos) /*!< EADC_T::SCTL9: EXTREN Mask */ 1051 1052 #define EADC_SCTL9_EXTFEN_Pos (5) /*!< EADC_T::SCTL9: EXTFEN Position */ 1053 #define EADC_SCTL9_EXTFEN_Msk (0x1ul << EADC_SCTL9_EXTFEN_Pos) /*!< EADC_T::SCTL9: EXTFEN Mask */ 1054 1055 #define EADC_SCTL9_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL9: TRGDLYDIV Position */ 1056 #define EADC_SCTL9_TRGDLYDIV_Msk (0x3ul << EADC_SCTL9_TRGDLYDIV_Pos) /*!< EADC_T::SCTL9: TRGDLYDIV Mask */ 1057 1058 #define EADC_SCTL9_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL9: TRGDLYCNT Position */ 1059 #define EADC_SCTL9_TRGDLYCNT_Msk (0xfful << EADC_SCTL9_TRGDLYCNT_Pos) /*!< EADC_T::SCTL9: TRGDLYCNT Mask */ 1060 1061 #define EADC_SCTL9_TRGSEL_Pos (16) /*!< EADC_T::SCTL9: TRGSEL Position */ 1062 #define EADC_SCTL9_TRGSEL_Msk (0x1ful << EADC_SCTL9_TRGSEL_Pos) /*!< EADC_T::SCTL9: TRGSEL Mask */ 1063 1064 #define EADC_SCTL9_INTPOS_Pos (22) /*!< EADC_T::SCTL9: INTPOS Position */ 1065 #define EADC_SCTL9_INTPOS_Msk (0x1ul << EADC_SCTL9_INTPOS_Pos) /*!< EADC_T::SCTL9: INTPOS Mask */ 1066 1067 #define EADC_SCTL9_EXTSMPT_Pos (24) /*!< EADC_T::SCTL9: EXTSMPT Position */ 1068 #define EADC_SCTL9_EXTSMPT_Msk (0xfful << EADC_SCTL9_EXTSMPT_Pos) /*!< EADC_T::SCTL9: EXTSMPT Mask */ 1069 1070 #define EADC_SCTL10_CHSEL_Pos (0) /*!< EADC_T::SCTL10: CHSEL Position */ 1071 #define EADC_SCTL10_CHSEL_Msk (0xful << EADC_SCTL10_CHSEL_Pos) /*!< EADC_T::SCTL10: CHSEL Mask */ 1072 1073 #define EADC_SCTL10_EXTREN_Pos (4) /*!< EADC_T::SCTL10: EXTREN Position */ 1074 #define EADC_SCTL10_EXTREN_Msk (0x1ul << EADC_SCTL10_EXTREN_Pos) /*!< EADC_T::SCTL10: EXTREN Mask */ 1075 1076 #define EADC_SCTL10_EXTFEN_Pos (5) /*!< EADC_T::SCTL10: EXTFEN Position */ 1077 #define EADC_SCTL10_EXTFEN_Msk (0x1ul << EADC_SCTL10_EXTFEN_Pos) /*!< EADC_T::SCTL10: EXTFEN Mask */ 1078 1079 #define EADC_SCTL10_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL10: TRGDLYDIV Position */ 1080 #define EADC_SCTL10_TRGDLYDIV_Msk (0x3ul << EADC_SCTL10_TRGDLYDIV_Pos) /*!< EADC_T::SCTL10: TRGDLYDIV Mask */ 1081 1082 #define EADC_SCTL10_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL10: TRGDLYCNT Position */ 1083 #define EADC_SCTL10_TRGDLYCNT_Msk (0xfful << EADC_SCTL10_TRGDLYCNT_Pos) /*!< EADC_T::SCTL10: TRGDLYCNT Mask */ 1084 1085 #define EADC_SCTL10_TRGSEL_Pos (16) /*!< EADC_T::SCTL10: TRGSEL Position */ 1086 #define EADC_SCTL10_TRGSEL_Msk (0x1ful << EADC_SCTL10_TRGSEL_Pos) /*!< EADC_T::SCTL10: TRGSEL Mask */ 1087 1088 #define EADC_SCTL10_INTPOS_Pos (22) /*!< EADC_T::SCTL10: INTPOS Position */ 1089 #define EADC_SCTL10_INTPOS_Msk (0x1ul << EADC_SCTL10_INTPOS_Pos) /*!< EADC_T::SCTL10: INTPOS Mask */ 1090 1091 #define EADC_SCTL10_EXTSMPT_Pos (24) /*!< EADC_T::SCTL10: EXTSMPT Position */ 1092 #define EADC_SCTL10_EXTSMPT_Msk (0xfful << EADC_SCTL10_EXTSMPT_Pos) /*!< EADC_T::SCTL10: EXTSMPT Mask */ 1093 1094 #define EADC_SCTL11_CHSEL_Pos (0) /*!< EADC_T::SCTL11: CHSEL Position */ 1095 #define EADC_SCTL11_CHSEL_Msk (0xful << EADC_SCTL11_CHSEL_Pos) /*!< EADC_T::SCTL11: CHSEL Mask */ 1096 1097 #define EADC_SCTL11_EXTREN_Pos (4) /*!< EADC_T::SCTL11: EXTREN Position */ 1098 #define EADC_SCTL11_EXTREN_Msk (0x1ul << EADC_SCTL11_EXTREN_Pos) /*!< EADC_T::SCTL11: EXTREN Mask */ 1099 1100 #define EADC_SCTL11_EXTFEN_Pos (5) /*!< EADC_T::SCTL11: EXTFEN Position */ 1101 #define EADC_SCTL11_EXTFEN_Msk (0x1ul << EADC_SCTL11_EXTFEN_Pos) /*!< EADC_T::SCTL11: EXTFEN Mask */ 1102 1103 #define EADC_SCTL11_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL11: TRGDLYDIV Position */ 1104 #define EADC_SCTL11_TRGDLYDIV_Msk (0x3ul << EADC_SCTL11_TRGDLYDIV_Pos) /*!< EADC_T::SCTL11: TRGDLYDIV Mask */ 1105 1106 #define EADC_SCTL11_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL11: TRGDLYCNT Position */ 1107 #define EADC_SCTL11_TRGDLYCNT_Msk (0xfful << EADC_SCTL11_TRGDLYCNT_Pos) /*!< EADC_T::SCTL11: TRGDLYCNT Mask */ 1108 1109 #define EADC_SCTL11_TRGSEL_Pos (16) /*!< EADC_T::SCTL11: TRGSEL Position */ 1110 #define EADC_SCTL11_TRGSEL_Msk (0x1ful << EADC_SCTL11_TRGSEL_Pos) /*!< EADC_T::SCTL11: TRGSEL Mask */ 1111 1112 #define EADC_SCTL11_INTPOS_Pos (22) /*!< EADC_T::SCTL11: INTPOS Position */ 1113 #define EADC_SCTL11_INTPOS_Msk (0x1ul << EADC_SCTL11_INTPOS_Pos) /*!< EADC_T::SCTL11: INTPOS Mask */ 1114 1115 #define EADC_SCTL11_EXTSMPT_Pos (24) /*!< EADC_T::SCTL11: EXTSMPT Position */ 1116 #define EADC_SCTL11_EXTSMPT_Msk (0xfful << EADC_SCTL11_EXTSMPT_Pos) /*!< EADC_T::SCTL11: EXTSMPT Mask */ 1117 1118 #define EADC_SCTL12_CHSEL_Pos (0) /*!< EADC_T::SCTL12: CHSEL Position */ 1119 #define EADC_SCTL12_CHSEL_Msk (0xful << EADC_SCTL12_CHSEL_Pos) /*!< EADC_T::SCTL12: CHSEL Mask */ 1120 1121 #define EADC_SCTL12_EXTREN_Pos (4) /*!< EADC_T::SCTL12: EXTREN Position */ 1122 #define EADC_SCTL12_EXTREN_Msk (0x1ul << EADC_SCTL12_EXTREN_Pos) /*!< EADC_T::SCTL12: EXTREN Mask */ 1123 1124 #define EADC_SCTL12_EXTFEN_Pos (5) /*!< EADC_T::SCTL12: EXTFEN Position */ 1125 #define EADC_SCTL12_EXTFEN_Msk (0x1ul << EADC_SCTL12_EXTFEN_Pos) /*!< EADC_T::SCTL12: EXTFEN Mask */ 1126 1127 #define EADC_SCTL12_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL12: TRGDLYDIV Position */ 1128 #define EADC_SCTL12_TRGDLYDIV_Msk (0x3ul << EADC_SCTL12_TRGDLYDIV_Pos) /*!< EADC_T::SCTL12: TRGDLYDIV Mask */ 1129 1130 #define EADC_SCTL12_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL12: TRGDLYCNT Position */ 1131 #define EADC_SCTL12_TRGDLYCNT_Msk (0xfful << EADC_SCTL12_TRGDLYCNT_Pos) /*!< EADC_T::SCTL12: TRGDLYCNT Mask */ 1132 1133 #define EADC_SCTL12_TRGSEL_Pos (16) /*!< EADC_T::SCTL12: TRGSEL Position */ 1134 #define EADC_SCTL12_TRGSEL_Msk (0x1ful << EADC_SCTL12_TRGSEL_Pos) /*!< EADC_T::SCTL12: TRGSEL Mask */ 1135 1136 #define EADC_SCTL12_INTPOS_Pos (22) /*!< EADC_T::SCTL12: INTPOS Position */ 1137 #define EADC_SCTL12_INTPOS_Msk (0x1ul << EADC_SCTL12_INTPOS_Pos) /*!< EADC_T::SCTL12: INTPOS Mask */ 1138 1139 #define EADC_SCTL12_EXTSMPT_Pos (24) /*!< EADC_T::SCTL12: EXTSMPT Position */ 1140 #define EADC_SCTL12_EXTSMPT_Msk (0xfful << EADC_SCTL12_EXTSMPT_Pos) /*!< EADC_T::SCTL12: EXTSMPT Mask */ 1141 1142 #define EADC_SCTL13_CHSEL_Pos (0) /*!< EADC_T::SCTL13: CHSEL Position */ 1143 #define EADC_SCTL13_CHSEL_Msk (0xful << EADC_SCTL13_CHSEL_Pos) /*!< EADC_T::SCTL13: CHSEL Mask */ 1144 1145 #define EADC_SCTL13_EXTREN_Pos (4) /*!< EADC_T::SCTL13: EXTREN Position */ 1146 #define EADC_SCTL13_EXTREN_Msk (0x1ul << EADC_SCTL13_EXTREN_Pos) /*!< EADC_T::SCTL13: EXTREN Mask */ 1147 1148 #define EADC_SCTL13_EXTFEN_Pos (5) /*!< EADC_T::SCTL13: EXTFEN Position */ 1149 #define EADC_SCTL13_EXTFEN_Msk (0x1ul << EADC_SCTL13_EXTFEN_Pos) /*!< EADC_T::SCTL13: EXTFEN Mask */ 1150 1151 #define EADC_SCTL13_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL13: TRGDLYDIV Position */ 1152 #define EADC_SCTL13_TRGDLYDIV_Msk (0x3ul << EADC_SCTL13_TRGDLYDIV_Pos) /*!< EADC_T::SCTL13: TRGDLYDIV Mask */ 1153 1154 #define EADC_SCTL13_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL13: TRGDLYCNT Position */ 1155 #define EADC_SCTL13_TRGDLYCNT_Msk (0xfful << EADC_SCTL13_TRGDLYCNT_Pos) /*!< EADC_T::SCTL13: TRGDLYCNT Mask */ 1156 1157 #define EADC_SCTL13_TRGSEL_Pos (16) /*!< EADC_T::SCTL13: TRGSEL Position */ 1158 #define EADC_SCTL13_TRGSEL_Msk (0x1ful << EADC_SCTL13_TRGSEL_Pos) /*!< EADC_T::SCTL13: TRGSEL Mask */ 1159 1160 #define EADC_SCTL13_INTPOS_Pos (22) /*!< EADC_T::SCTL13: INTPOS Position */ 1161 #define EADC_SCTL13_INTPOS_Msk (0x1ul << EADC_SCTL13_INTPOS_Pos) /*!< EADC_T::SCTL13: INTPOS Mask */ 1162 1163 #define EADC_SCTL13_EXTSMPT_Pos (24) /*!< EADC_T::SCTL13: EXTSMPT Position */ 1164 #define EADC_SCTL13_EXTSMPT_Msk (0xfful << EADC_SCTL13_EXTSMPT_Pos) /*!< EADC_T::SCTL13: EXTSMPT Mask */ 1165 1166 #define EADC_SCTL14_CHSEL_Pos (0) /*!< EADC_T::SCTL14: CHSEL Position */ 1167 #define EADC_SCTL14_CHSEL_Msk (0xful << EADC_SCTL14_CHSEL_Pos) /*!< EADC_T::SCTL14: CHSEL Mask */ 1168 1169 #define EADC_SCTL14_EXTREN_Pos (4) /*!< EADC_T::SCTL14: EXTREN Position */ 1170 #define EADC_SCTL14_EXTREN_Msk (0x1ul << EADC_SCTL14_EXTREN_Pos) /*!< EADC_T::SCTL14: EXTREN Mask */ 1171 1172 #define EADC_SCTL14_EXTFEN_Pos (5) /*!< EADC_T::SCTL14: EXTFEN Position */ 1173 #define EADC_SCTL14_EXTFEN_Msk (0x1ul << EADC_SCTL14_EXTFEN_Pos) /*!< EADC_T::SCTL14: EXTFEN Mask */ 1174 1175 #define EADC_SCTL14_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL14: TRGDLYDIV Position */ 1176 #define EADC_SCTL14_TRGDLYDIV_Msk (0x3ul << EADC_SCTL14_TRGDLYDIV_Pos) /*!< EADC_T::SCTL14: TRGDLYDIV Mask */ 1177 1178 #define EADC_SCTL14_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL14: TRGDLYCNT Position */ 1179 #define EADC_SCTL14_TRGDLYCNT_Msk (0xfful << EADC_SCTL14_TRGDLYCNT_Pos) /*!< EADC_T::SCTL14: TRGDLYCNT Mask */ 1180 1181 #define EADC_SCTL14_TRGSEL_Pos (16) /*!< EADC_T::SCTL14: TRGSEL Position */ 1182 #define EADC_SCTL14_TRGSEL_Msk (0x1ful << EADC_SCTL14_TRGSEL_Pos) /*!< EADC_T::SCTL14: TRGSEL Mask */ 1183 1184 #define EADC_SCTL14_INTPOS_Pos (22) /*!< EADC_T::SCTL14: INTPOS Position */ 1185 #define EADC_SCTL14_INTPOS_Msk (0x1ul << EADC_SCTL14_INTPOS_Pos) /*!< EADC_T::SCTL14: INTPOS Mask */ 1186 1187 #define EADC_SCTL14_EXTSMPT_Pos (24) /*!< EADC_T::SCTL14: EXTSMPT Position */ 1188 #define EADC_SCTL14_EXTSMPT_Msk (0xfful << EADC_SCTL14_EXTSMPT_Pos) /*!< EADC_T::SCTL14: EXTSMPT Mask */ 1189 1190 #define EADC_SCTL15_CHSEL_Pos (0) /*!< EADC_T::SCTL15: CHSEL Position */ 1191 #define EADC_SCTL15_CHSEL_Msk (0xful << EADC_SCTL15_CHSEL_Pos) /*!< EADC_T::SCTL15: CHSEL Mask */ 1192 1193 #define EADC_SCTL15_EXTREN_Pos (4) /*!< EADC_T::SCTL15: EXTREN Position */ 1194 #define EADC_SCTL15_EXTREN_Msk (0x1ul << EADC_SCTL15_EXTREN_Pos) /*!< EADC_T::SCTL15: EXTREN Mask */ 1195 1196 #define EADC_SCTL15_EXTFEN_Pos (5) /*!< EADC_T::SCTL15: EXTFEN Position */ 1197 #define EADC_SCTL15_EXTFEN_Msk (0x1ul << EADC_SCTL15_EXTFEN_Pos) /*!< EADC_T::SCTL15: EXTFEN Mask */ 1198 1199 #define EADC_SCTL15_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL15: TRGDLYDIV Position */ 1200 #define EADC_SCTL15_TRGDLYDIV_Msk (0x3ul << EADC_SCTL15_TRGDLYDIV_Pos) /*!< EADC_T::SCTL15: TRGDLYDIV Mask */ 1201 1202 #define EADC_SCTL15_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL15: TRGDLYCNT Position */ 1203 #define EADC_SCTL15_TRGDLYCNT_Msk (0xfful << EADC_SCTL15_TRGDLYCNT_Pos) /*!< EADC_T::SCTL15: TRGDLYCNT Mask */ 1204 1205 #define EADC_SCTL15_TRGSEL_Pos (16) /*!< EADC_T::SCTL15: TRGSEL Position */ 1206 #define EADC_SCTL15_TRGSEL_Msk (0x1ful << EADC_SCTL15_TRGSEL_Pos) /*!< EADC_T::SCTL15: TRGSEL Mask */ 1207 1208 #define EADC_SCTL15_INTPOS_Pos (22) /*!< EADC_T::SCTL15: INTPOS Position */ 1209 #define EADC_SCTL15_INTPOS_Msk (0x1ul << EADC_SCTL15_INTPOS_Pos) /*!< EADC_T::SCTL15: INTPOS Mask */ 1210 1211 #define EADC_SCTL15_EXTSMPT_Pos (24) /*!< EADC_T::SCTL15: EXTSMPT Position */ 1212 #define EADC_SCTL15_EXTSMPT_Msk (0xfful << EADC_SCTL15_EXTSMPT_Pos) /*!< EADC_T::SCTL15: EXTSMPT Mask */ 1213 1214 #define EADC_SCTL16_EXTSMPT_Pos (24) /*!< EADC_T::SCTL16: EXTSMPT Position */ 1215 #define EADC_SCTL16_EXTSMPT_Msk (0xfful << EADC_SCTL16_EXTSMPT_Pos) /*!< EADC_T::SCTL16: EXTSMPT Mask */ 1216 1217 #define EADC_SCTL17_EXTSMPT_Pos (24) /*!< EADC_T::SCTL17: EXTSMPT Position */ 1218 #define EADC_SCTL17_EXTSMPT_Msk (0xfful << EADC_SCTL17_EXTSMPT_Pos) /*!< EADC_T::SCTL17: EXTSMPT Mask */ 1219 1220 #define EADC_SCTL18_EXTSMPT_Pos (24) /*!< EADC_T::SCTL18: EXTSMPT Position */ 1221 #define EADC_SCTL18_EXTSMPT_Msk (0xfful << EADC_SCTL18_EXTSMPT_Pos) /*!< EADC_T::SCTL18: EXTSMPT Mask */ 1222 1223 #define EADC_INTSRC0_SPLIE0_Pos (0) /*!< EADC_T::INTSRC0: SPLIE0 Position */ 1224 #define EADC_INTSRC0_SPLIE0_Msk (0x1ul << EADC_INTSRC0_SPLIE0_Pos) /*!< EADC_T::INTSRC0: SPLIE0 Mask */ 1225 1226 #define EADC_INTSRC0_SPLIE1_Pos (1) /*!< EADC_T::INTSRC0: SPLIE1 Position */ 1227 #define EADC_INTSRC0_SPLIE1_Msk (0x1ul << EADC_INTSRC0_SPLIE1_Pos) /*!< EADC_T::INTSRC0: SPLIE1 Mask */ 1228 1229 #define EADC_INTSRC0_SPLIE2_Pos (2) /*!< EADC_T::INTSRC0: SPLIE2 Position */ 1230 #define EADC_INTSRC0_SPLIE2_Msk (0x1ul << EADC_INTSRC0_SPLIE2_Pos) /*!< EADC_T::INTSRC0: SPLIE2 Mask */ 1231 1232 #define EADC_INTSRC0_SPLIE3_Pos (3) /*!< EADC_T::INTSRC0: SPLIE3 Position */ 1233 #define EADC_INTSRC0_SPLIE3_Msk (0x1ul << EADC_INTSRC0_SPLIE3_Pos) /*!< EADC_T::INTSRC0: SPLIE3 Mask */ 1234 1235 #define EADC_INTSRC0_SPLIE4_Pos (4) /*!< EADC_T::INTSRC0: SPLIE4 Position */ 1236 #define EADC_INTSRC0_SPLIE4_Msk (0x1ul << EADC_INTSRC0_SPLIE4_Pos) /*!< EADC_T::INTSRC0: SPLIE4 Mask */ 1237 1238 #define EADC_INTSRC0_SPLIE5_Pos (5) /*!< EADC_T::INTSRC0: SPLIE5 Position */ 1239 #define EADC_INTSRC0_SPLIE5_Msk (0x1ul << EADC_INTSRC0_SPLIE5_Pos) /*!< EADC_T::INTSRC0: SPLIE5 Mask */ 1240 1241 #define EADC_INTSRC0_SPLIE6_Pos (6) /*!< EADC_T::INTSRC0: SPLIE6 Position */ 1242 #define EADC_INTSRC0_SPLIE6_Msk (0x1ul << EADC_INTSRC0_SPLIE6_Pos) /*!< EADC_T::INTSRC0: SPLIE6 Mask */ 1243 1244 #define EADC_INTSRC0_SPLIE7_Pos (7) /*!< EADC_T::INTSRC0: SPLIE7 Position */ 1245 #define EADC_INTSRC0_SPLIE7_Msk (0x1ul << EADC_INTSRC0_SPLIE7_Pos) /*!< EADC_T::INTSRC0: SPLIE7 Mask */ 1246 1247 #define EADC_INTSRC0_SPLIE8_Pos (8) /*!< EADC_T::INTSRC0: SPLIE8 Position */ 1248 #define EADC_INTSRC0_SPLIE8_Msk (0x1ul << EADC_INTSRC0_SPLIE8_Pos) /*!< EADC_T::INTSRC0: SPLIE8 Mask */ 1249 1250 #define EADC_INTSRC0_SPLIE9_Pos (9) /*!< EADC_T::INTSRC0: SPLIE9 Position */ 1251 #define EADC_INTSRC0_SPLIE9_Msk (0x1ul << EADC_INTSRC0_SPLIE9_Pos) /*!< EADC_T::INTSRC0: SPLIE9 Mask */ 1252 1253 #define EADC_INTSRC0_SPLIE10_Pos (10) /*!< EADC_T::INTSRC0: SPLIE10 Position */ 1254 #define EADC_INTSRC0_SPLIE10_Msk (0x1ul << EADC_INTSRC0_SPLIE10_Pos) /*!< EADC_T::INTSRC0: SPLIE10 Mask */ 1255 1256 #define EADC_INTSRC0_SPLIE11_Pos (11) /*!< EADC_T::INTSRC0: SPLIE11 Position */ 1257 #define EADC_INTSRC0_SPLIE11_Msk (0x1ul << EADC_INTSRC0_SPLIE11_Pos) /*!< EADC_T::INTSRC0: SPLIE11 Mask */ 1258 1259 #define EADC_INTSRC0_SPLIE12_Pos (12) /*!< EADC_T::INTSRC0: SPLIE12 Position */ 1260 #define EADC_INTSRC0_SPLIE12_Msk (0x1ul << EADC_INTSRC0_SPLIE12_Pos) /*!< EADC_T::INTSRC0: SPLIE12 Mask */ 1261 1262 #define EADC_INTSRC0_SPLIE13_Pos (13) /*!< EADC_T::INTSRC0: SPLIE13 Position */ 1263 #define EADC_INTSRC0_SPLIE13_Msk (0x1ul << EADC_INTSRC0_SPLIE13_Pos) /*!< EADC_T::INTSRC0: SPLIE13 Mask */ 1264 1265 #define EADC_INTSRC0_SPLIE14_Pos (14) /*!< EADC_T::INTSRC0: SPLIE14 Position */ 1266 #define EADC_INTSRC0_SPLIE14_Msk (0x1ul << EADC_INTSRC0_SPLIE14_Pos) /*!< EADC_T::INTSRC0: SPLIE14 Mask */ 1267 1268 #define EADC_INTSRC0_SPLIE15_Pos (15) /*!< EADC_T::INTSRC0: SPLIE15 Position */ 1269 #define EADC_INTSRC0_SPLIE15_Msk (0x1ul << EADC_INTSRC0_SPLIE15_Pos) /*!< EADC_T::INTSRC0: SPLIE15 Mask */ 1270 1271 #define EADC_INTSRC0_SPLIE16_Pos (16) /*!< EADC_T::INTSRC0: SPLIE16 Position */ 1272 #define EADC_INTSRC0_SPLIE16_Msk (0x1ul << EADC_INTSRC0_SPLIE16_Pos) /*!< EADC_T::INTSRC0: SPLIE16 Mask */ 1273 1274 #define EADC_INTSRC0_SPLIE17_Pos (17) /*!< EADC_T::INTSRC0: SPLIE17 Position */ 1275 #define EADC_INTSRC0_SPLIE17_Msk (0x1ul << EADC_INTSRC0_SPLIE17_Pos) /*!< EADC_T::INTSRC0: SPLIE17 Mask */ 1276 1277 #define EADC_INTSRC0_SPLIE18_Pos (18) /*!< EADC_T::INTSRC0: SPLIE18 Position */ 1278 #define EADC_INTSRC0_SPLIE18_Msk (0x1ul << EADC_INTSRC0_SPLIE18_Pos) /*!< EADC_T::INTSRC0: SPLIE18 Mask */ 1279 1280 #define EADC_INTSRC1_SPLIE0_Pos (0) /*!< EADC_T::INTSRC1: SPLIE0 Position */ 1281 #define EADC_INTSRC1_SPLIE0_Msk (0x1ul << EADC_INTSRC1_SPLIE0_Pos) /*!< EADC_T::INTSRC1: SPLIE0 Mask */ 1282 1283 #define EADC_INTSRC1_SPLIE1_Pos (1) /*!< EADC_T::INTSRC1: SPLIE1 Position */ 1284 #define EADC_INTSRC1_SPLIE1_Msk (0x1ul << EADC_INTSRC1_SPLIE1_Pos) /*!< EADC_T::INTSRC1: SPLIE1 Mask */ 1285 1286 #define EADC_INTSRC1_SPLIE2_Pos (2) /*!< EADC_T::INTSRC1: SPLIE2 Position */ 1287 #define EADC_INTSRC1_SPLIE2_Msk (0x1ul << EADC_INTSRC1_SPLIE2_Pos) /*!< EADC_T::INTSRC1: SPLIE2 Mask */ 1288 1289 #define EADC_INTSRC1_SPLIE3_Pos (3) /*!< EADC_T::INTSRC1: SPLIE3 Position */ 1290 #define EADC_INTSRC1_SPLIE3_Msk (0x1ul << EADC_INTSRC1_SPLIE3_Pos) /*!< EADC_T::INTSRC1: SPLIE3 Mask */ 1291 1292 #define EADC_INTSRC1_SPLIE4_Pos (4) /*!< EADC_T::INTSRC1: SPLIE4 Position */ 1293 #define EADC_INTSRC1_SPLIE4_Msk (0x1ul << EADC_INTSRC1_SPLIE4_Pos) /*!< EADC_T::INTSRC1: SPLIE4 Mask */ 1294 1295 #define EADC_INTSRC1_SPLIE5_Pos (5) /*!< EADC_T::INTSRC1: SPLIE5 Position */ 1296 #define EADC_INTSRC1_SPLIE5_Msk (0x1ul << EADC_INTSRC1_SPLIE5_Pos) /*!< EADC_T::INTSRC1: SPLIE5 Mask */ 1297 1298 #define EADC_INTSRC1_SPLIE6_Pos (6) /*!< EADC_T::INTSRC1: SPLIE6 Position */ 1299 #define EADC_INTSRC1_SPLIE6_Msk (0x1ul << EADC_INTSRC1_SPLIE6_Pos) /*!< EADC_T::INTSRC1: SPLIE6 Mask */ 1300 1301 #define EADC_INTSRC1_SPLIE7_Pos (7) /*!< EADC_T::INTSRC1: SPLIE7 Position */ 1302 #define EADC_INTSRC1_SPLIE7_Msk (0x1ul << EADC_INTSRC1_SPLIE7_Pos) /*!< EADC_T::INTSRC1: SPLIE7 Mask */ 1303 1304 #define EADC_INTSRC1_SPLIE8_Pos (8) /*!< EADC_T::INTSRC1: SPLIE8 Position */ 1305 #define EADC_INTSRC1_SPLIE8_Msk (0x1ul << EADC_INTSRC1_SPLIE8_Pos) /*!< EADC_T::INTSRC1: SPLIE8 Mask */ 1306 1307 #define EADC_INTSRC1_SPLIE9_Pos (9) /*!< EADC_T::INTSRC1: SPLIE9 Position */ 1308 #define EADC_INTSRC1_SPLIE9_Msk (0x1ul << EADC_INTSRC1_SPLIE9_Pos) /*!< EADC_T::INTSRC1: SPLIE9 Mask */ 1309 1310 #define EADC_INTSRC1_SPLIE10_Pos (10) /*!< EADC_T::INTSRC1: SPLIE10 Position */ 1311 #define EADC_INTSRC1_SPLIE10_Msk (0x1ul << EADC_INTSRC1_SPLIE10_Pos) /*!< EADC_T::INTSRC1: SPLIE10 Mask */ 1312 1313 #define EADC_INTSRC1_SPLIE11_Pos (11) /*!< EADC_T::INTSRC1: SPLIE11 Position */ 1314 #define EADC_INTSRC1_SPLIE11_Msk (0x1ul << EADC_INTSRC1_SPLIE11_Pos) /*!< EADC_T::INTSRC1: SPLIE11 Mask */ 1315 1316 #define EADC_INTSRC1_SPLIE12_Pos (12) /*!< EADC_T::INTSRC1: SPLIE12 Position */ 1317 #define EADC_INTSRC1_SPLIE12_Msk (0x1ul << EADC_INTSRC1_SPLIE12_Pos) /*!< EADC_T::INTSRC1: SPLIE12 Mask */ 1318 1319 #define EADC_INTSRC1_SPLIE13_Pos (13) /*!< EADC_T::INTSRC1: SPLIE13 Position */ 1320 #define EADC_INTSRC1_SPLIE13_Msk (0x1ul << EADC_INTSRC1_SPLIE13_Pos) /*!< EADC_T::INTSRC1: SPLIE13 Mask */ 1321 1322 #define EADC_INTSRC1_SPLIE14_Pos (14) /*!< EADC_T::INTSRC1: SPLIE14 Position */ 1323 #define EADC_INTSRC1_SPLIE14_Msk (0x1ul << EADC_INTSRC1_SPLIE14_Pos) /*!< EADC_T::INTSRC1: SPLIE14 Mask */ 1324 1325 #define EADC_INTSRC1_SPLIE15_Pos (15) /*!< EADC_T::INTSRC1: SPLIE15 Position */ 1326 #define EADC_INTSRC1_SPLIE15_Msk (0x1ul << EADC_INTSRC1_SPLIE15_Pos) /*!< EADC_T::INTSRC1: SPLIE15 Mask */ 1327 1328 #define EADC_INTSRC1_SPLIE16_Pos (16) /*!< EADC_T::INTSRC1: SPLIE16 Position */ 1329 #define EADC_INTSRC1_SPLIE16_Msk (0x1ul << EADC_INTSRC1_SPLIE16_Pos) /*!< EADC_T::INTSRC1: SPLIE16 Mask */ 1330 1331 #define EADC_INTSRC1_SPLIE17_Pos (17) /*!< EADC_T::INTSRC1: SPLIE17 Position */ 1332 #define EADC_INTSRC1_SPLIE17_Msk (0x1ul << EADC_INTSRC1_SPLIE17_Pos) /*!< EADC_T::INTSRC1: SPLIE17 Mask */ 1333 1334 #define EADC_INTSRC1_SPLIE18_Pos (18) /*!< EADC_T::INTSRC1: SPLIE18 Position */ 1335 #define EADC_INTSRC1_SPLIE18_Msk (0x1ul << EADC_INTSRC1_SPLIE18_Pos) /*!< EADC_T::INTSRC1: SPLIE18 Mask */ 1336 1337 #define EADC_INTSRC2_SPLIE0_Pos (0) /*!< EADC_T::INTSRC2: SPLIE0 Position */ 1338 #define EADC_INTSRC2_SPLIE0_Msk (0x1ul << EADC_INTSRC2_SPLIE0_Pos) /*!< EADC_T::INTSRC2: SPLIE0 Mask */ 1339 1340 #define EADC_INTSRC2_SPLIE1_Pos (1) /*!< EADC_T::INTSRC2: SPLIE1 Position */ 1341 #define EADC_INTSRC2_SPLIE1_Msk (0x1ul << EADC_INTSRC2_SPLIE1_Pos) /*!< EADC_T::INTSRC2: SPLIE1 Mask */ 1342 1343 #define EADC_INTSRC2_SPLIE2_Pos (2) /*!< EADC_T::INTSRC2: SPLIE2 Position */ 1344 #define EADC_INTSRC2_SPLIE2_Msk (0x1ul << EADC_INTSRC2_SPLIE2_Pos) /*!< EADC_T::INTSRC2: SPLIE2 Mask */ 1345 1346 #define EADC_INTSRC2_SPLIE3_Pos (3) /*!< EADC_T::INTSRC2: SPLIE3 Position */ 1347 #define EADC_INTSRC2_SPLIE3_Msk (0x1ul << EADC_INTSRC2_SPLIE3_Pos) /*!< EADC_T::INTSRC2: SPLIE3 Mask */ 1348 1349 #define EADC_INTSRC2_SPLIE4_Pos (4) /*!< EADC_T::INTSRC2: SPLIE4 Position */ 1350 #define EADC_INTSRC2_SPLIE4_Msk (0x1ul << EADC_INTSRC2_SPLIE4_Pos) /*!< EADC_T::INTSRC2: SPLIE4 Mask */ 1351 1352 #define EADC_INTSRC2_SPLIE5_Pos (5) /*!< EADC_T::INTSRC2: SPLIE5 Position */ 1353 #define EADC_INTSRC2_SPLIE5_Msk (0x1ul << EADC_INTSRC2_SPLIE5_Pos) /*!< EADC_T::INTSRC2: SPLIE5 Mask */ 1354 1355 #define EADC_INTSRC2_SPLIE6_Pos (6) /*!< EADC_T::INTSRC2: SPLIE6 Position */ 1356 #define EADC_INTSRC2_SPLIE6_Msk (0x1ul << EADC_INTSRC2_SPLIE6_Pos) /*!< EADC_T::INTSRC2: SPLIE6 Mask */ 1357 1358 #define EADC_INTSRC2_SPLIE7_Pos (7) /*!< EADC_T::INTSRC2: SPLIE7 Position */ 1359 #define EADC_INTSRC2_SPLIE7_Msk (0x1ul << EADC_INTSRC2_SPLIE7_Pos) /*!< EADC_T::INTSRC2: SPLIE7 Mask */ 1360 1361 #define EADC_INTSRC2_SPLIE8_Pos (8) /*!< EADC_T::INTSRC2: SPLIE8 Position */ 1362 #define EADC_INTSRC2_SPLIE8_Msk (0x1ul << EADC_INTSRC2_SPLIE8_Pos) /*!< EADC_T::INTSRC2: SPLIE8 Mask */ 1363 1364 #define EADC_INTSRC2_SPLIE9_Pos (9) /*!< EADC_T::INTSRC2: SPLIE9 Position */ 1365 #define EADC_INTSRC2_SPLIE9_Msk (0x1ul << EADC_INTSRC2_SPLIE9_Pos) /*!< EADC_T::INTSRC2: SPLIE9 Mask */ 1366 1367 #define EADC_INTSRC2_SPLIE10_Pos (10) /*!< EADC_T::INTSRC2: SPLIE10 Position */ 1368 #define EADC_INTSRC2_SPLIE10_Msk (0x1ul << EADC_INTSRC2_SPLIE10_Pos) /*!< EADC_T::INTSRC2: SPLIE10 Mask */ 1369 1370 #define EADC_INTSRC2_SPLIE11_Pos (11) /*!< EADC_T::INTSRC2: SPLIE11 Position */ 1371 #define EADC_INTSRC2_SPLIE11_Msk (0x1ul << EADC_INTSRC2_SPLIE11_Pos) /*!< EADC_T::INTSRC2: SPLIE11 Mask */ 1372 1373 #define EADC_INTSRC2_SPLIE12_Pos (12) /*!< EADC_T::INTSRC2: SPLIE12 Position */ 1374 #define EADC_INTSRC2_SPLIE12_Msk (0x1ul << EADC_INTSRC2_SPLIE12_Pos) /*!< EADC_T::INTSRC2: SPLIE12 Mask */ 1375 1376 #define EADC_INTSRC2_SPLIE13_Pos (13) /*!< EADC_T::INTSRC2: SPLIE13 Position */ 1377 #define EADC_INTSRC2_SPLIE13_Msk (0x1ul << EADC_INTSRC2_SPLIE13_Pos) /*!< EADC_T::INTSRC2: SPLIE13 Mask */ 1378 1379 #define EADC_INTSRC2_SPLIE14_Pos (14) /*!< EADC_T::INTSRC2: SPLIE14 Position */ 1380 #define EADC_INTSRC2_SPLIE14_Msk (0x1ul << EADC_INTSRC2_SPLIE14_Pos) /*!< EADC_T::INTSRC2: SPLIE14 Mask */ 1381 1382 #define EADC_INTSRC2_SPLIE15_Pos (15) /*!< EADC_T::INTSRC2: SPLIE15 Position */ 1383 #define EADC_INTSRC2_SPLIE15_Msk (0x1ul << EADC_INTSRC2_SPLIE15_Pos) /*!< EADC_T::INTSRC2: SPLIE15 Mask */ 1384 1385 #define EADC_INTSRC2_SPLIE16_Pos (16) /*!< EADC_T::INTSRC2: SPLIE16 Position */ 1386 #define EADC_INTSRC2_SPLIE16_Msk (0x1ul << EADC_INTSRC2_SPLIE16_Pos) /*!< EADC_T::INTSRC2: SPLIE16 Mask */ 1387 1388 #define EADC_INTSRC2_SPLIE17_Pos (17) /*!< EADC_T::INTSRC2: SPLIE17 Position */ 1389 #define EADC_INTSRC2_SPLIE17_Msk (0x1ul << EADC_INTSRC2_SPLIE17_Pos) /*!< EADC_T::INTSRC2: SPLIE17 Mask */ 1390 1391 #define EADC_INTSRC2_SPLIE18_Pos (18) /*!< EADC_T::INTSRC2: SPLIE18 Position */ 1392 #define EADC_INTSRC2_SPLIE18_Msk (0x1ul << EADC_INTSRC2_SPLIE18_Pos) /*!< EADC_T::INTSRC2: SPLIE18 Mask */ 1393 1394 #define EADC_INTSRC3_SPLIE0_Pos (0) /*!< EADC_T::INTSRC3: SPLIE0 Position */ 1395 #define EADC_INTSRC3_SPLIE0_Msk (0x1ul << EADC_INTSRC3_SPLIE0_Pos) /*!< EADC_T::INTSRC3: SPLIE0 Mask */ 1396 1397 #define EADC_INTSRC3_SPLIE1_Pos (1) /*!< EADC_T::INTSRC3: SPLIE1 Position */ 1398 #define EADC_INTSRC3_SPLIE1_Msk (0x1ul << EADC_INTSRC3_SPLIE1_Pos) /*!< EADC_T::INTSRC3: SPLIE1 Mask */ 1399 1400 #define EADC_INTSRC3_SPLIE2_Pos (2) /*!< EADC_T::INTSRC3: SPLIE2 Position */ 1401 #define EADC_INTSRC3_SPLIE2_Msk (0x1ul << EADC_INTSRC3_SPLIE2_Pos) /*!< EADC_T::INTSRC3: SPLIE2 Mask */ 1402 1403 #define EADC_INTSRC3_SPLIE3_Pos (3) /*!< EADC_T::INTSRC3: SPLIE3 Position */ 1404 #define EADC_INTSRC3_SPLIE3_Msk (0x1ul << EADC_INTSRC3_SPLIE3_Pos) /*!< EADC_T::INTSRC3: SPLIE3 Mask */ 1405 1406 #define EADC_INTSRC3_SPLIE4_Pos (4) /*!< EADC_T::INTSRC3: SPLIE4 Position */ 1407 #define EADC_INTSRC3_SPLIE4_Msk (0x1ul << EADC_INTSRC3_SPLIE4_Pos) /*!< EADC_T::INTSRC3: SPLIE4 Mask */ 1408 1409 #define EADC_INTSRC3_SPLIE5_Pos (5) /*!< EADC_T::INTSRC3: SPLIE5 Position */ 1410 #define EADC_INTSRC3_SPLIE5_Msk (0x1ul << EADC_INTSRC3_SPLIE5_Pos) /*!< EADC_T::INTSRC3: SPLIE5 Mask */ 1411 1412 #define EADC_INTSRC3_SPLIE6_Pos (6) /*!< EADC_T::INTSRC3: SPLIE6 Position */ 1413 #define EADC_INTSRC3_SPLIE6_Msk (0x1ul << EADC_INTSRC3_SPLIE6_Pos) /*!< EADC_T::INTSRC3: SPLIE6 Mask */ 1414 1415 #define EADC_INTSRC3_SPLIE7_Pos (7) /*!< EADC_T::INTSRC3: SPLIE7 Position */ 1416 #define EADC_INTSRC3_SPLIE7_Msk (0x1ul << EADC_INTSRC3_SPLIE7_Pos) /*!< EADC_T::INTSRC3: SPLIE7 Mask */ 1417 1418 #define EADC_INTSRC3_SPLIE8_Pos (8) /*!< EADC_T::INTSRC3: SPLIE8 Position */ 1419 #define EADC_INTSRC3_SPLIE8_Msk (0x1ul << EADC_INTSRC3_SPLIE8_Pos) /*!< EADC_T::INTSRC3: SPLIE8 Mask */ 1420 1421 #define EADC_INTSRC3_SPLIE9_Pos (9) /*!< EADC_T::INTSRC3: SPLIE9 Position */ 1422 #define EADC_INTSRC3_SPLIE9_Msk (0x1ul << EADC_INTSRC3_SPLIE9_Pos) /*!< EADC_T::INTSRC3: SPLIE9 Mask */ 1423 1424 #define EADC_INTSRC3_SPLIE10_Pos (10) /*!< EADC_T::INTSRC3: SPLIE10 Position */ 1425 #define EADC_INTSRC3_SPLIE10_Msk (0x1ul << EADC_INTSRC3_SPLIE10_Pos) /*!< EADC_T::INTSRC3: SPLIE10 Mask */ 1426 1427 #define EADC_INTSRC3_SPLIE11_Pos (11) /*!< EADC_T::INTSRC3: SPLIE11 Position */ 1428 #define EADC_INTSRC3_SPLIE11_Msk (0x1ul << EADC_INTSRC3_SPLIE11_Pos) /*!< EADC_T::INTSRC3: SPLIE11 Mask */ 1429 1430 #define EADC_INTSRC3_SPLIE12_Pos (12) /*!< EADC_T::INTSRC3: SPLIE12 Position */ 1431 #define EADC_INTSRC3_SPLIE12_Msk (0x1ul << EADC_INTSRC3_SPLIE12_Pos) /*!< EADC_T::INTSRC3: SPLIE12 Mask */ 1432 1433 #define EADC_INTSRC3_SPLIE13_Pos (13) /*!< EADC_T::INTSRC3: SPLIE13 Position */ 1434 #define EADC_INTSRC3_SPLIE13_Msk (0x1ul << EADC_INTSRC3_SPLIE13_Pos) /*!< EADC_T::INTSRC3: SPLIE13 Mask */ 1435 1436 #define EADC_INTSRC3_SPLIE14_Pos (14) /*!< EADC_T::INTSRC3: SPLIE14 Position */ 1437 #define EADC_INTSRC3_SPLIE14_Msk (0x1ul << EADC_INTSRC3_SPLIE14_Pos) /*!< EADC_T::INTSRC3: SPLIE14 Mask */ 1438 1439 #define EADC_INTSRC3_SPLIE15_Pos (15) /*!< EADC_T::INTSRC3: SPLIE15 Position */ 1440 #define EADC_INTSRC3_SPLIE15_Msk (0x1ul << EADC_INTSRC3_SPLIE15_Pos) /*!< EADC_T::INTSRC3: SPLIE15 Mask */ 1441 1442 #define EADC_INTSRC3_SPLIE16_Pos (16) /*!< EADC_T::INTSRC3: SPLIE16 Position */ 1443 #define EADC_INTSRC3_SPLIE16_Msk (0x1ul << EADC_INTSRC3_SPLIE16_Pos) /*!< EADC_T::INTSRC3: SPLIE16 Mask */ 1444 1445 #define EADC_INTSRC3_SPLIE17_Pos (17) /*!< EADC_T::INTSRC3: SPLIE17 Position */ 1446 #define EADC_INTSRC3_SPLIE17_Msk (0x1ul << EADC_INTSRC3_SPLIE17_Pos) /*!< EADC_T::INTSRC3: SPLIE17 Mask */ 1447 1448 #define EADC_INTSRC3_SPLIE18_Pos (18) /*!< EADC_T::INTSRC3: SPLIE18 Position */ 1449 #define EADC_INTSRC3_SPLIE18_Msk (0x1ul << EADC_INTSRC3_SPLIE18_Pos) /*!< EADC_T::INTSRC3: SPLIE18 Mask */ 1450 1451 #define EADC_CMP_ADCMPEN_Pos (0) /*!< EADC_T::CMP: ADCMPEN Position */ 1452 #define EADC_CMP_ADCMPEN_Msk (0x1ul << EADC_CMP_ADCMPEN_Pos) /*!< EADC_T::CMP: ADCMPEN Mask */ 1453 1454 #define EADC_CMP_ADCMPIE_Pos (1) /*!< EADC_T::CMP: ADCMPIE Position */ 1455 #define EADC_CMP_ADCMPIE_Msk (0x1ul << EADC_CMP_ADCMPIE_Pos) /*!< EADC_T::CMP: ADCMPIE Mask */ 1456 1457 #define EADC_CMP_CMPCOND_Pos (2) /*!< EADC_T::CMP: CMPCOND Position */ 1458 #define EADC_CMP_CMPCOND_Msk (0x1ul << EADC_CMP_CMPCOND_Pos) /*!< EADC_T::CMP: CMPCOND Mask */ 1459 1460 #define EADC_CMP_CMPSPL_Pos (3) /*!< EADC_T::CMP: CMPSPL Position */ 1461 #define EADC_CMP_CMPSPL_Msk (0x1ful << EADC_CMP_CMPSPL_Pos) /*!< EADC_T::CMP: CMPSPL Mask */ 1462 1463 #define EADC_CMP_CMPMCNT_Pos (8) /*!< EADC_T::CMP: CMPMCNT Position */ 1464 #define EADC_CMP_CMPMCNT_Msk (0xful << EADC_CMP_CMPMCNT_Pos) /*!< EADC_T::CMP: CMPMCNT Mask */ 1465 1466 #define EADC_CMP_CMPWEN_Pos (15) /*!< EADC_T::CMP: CMPWEN Position */ 1467 #define EADC_CMP_CMPWEN_Msk (0x1ul << EADC_CMP_CMPWEN_Pos) /*!< EADC_T::CMP: CMPWEN Mask */ 1468 1469 #define EADC_CMP_CMPDAT_Pos (16) /*!< EADC_T::CMP: CMPDAT Position */ 1470 #define EADC_CMP_CMPDAT_Msk (0xffful << EADC_CMP_CMPDAT_Pos) /*!< EADC_T::CMP: CMPDAT Mask */ 1471 1472 #define EADC_CMP0_ADCMPEN_Pos (0) /*!< EADC_T::CMP0: ADCMPEN Position */ 1473 #define EADC_CMP0_ADCMPEN_Msk (0x1ul << EADC_CMP0_ADCMPEN_Pos) /*!< EADC_T::CMP0: ADCMPEN Mask */ 1474 1475 #define EADC_CMP0_ADCMPIE_Pos (1) /*!< EADC_T::CMP0: ADCMPIE Position */ 1476 #define EADC_CMP0_ADCMPIE_Msk (0x1ul << EADC_CMP0_ADCMPIE_Pos) /*!< EADC_T::CMP0: ADCMPIE Mask */ 1477 1478 #define EADC_CMP0_CMPCOND_Pos (2) /*!< EADC_T::CMP0: CMPCOND Position */ 1479 #define EADC_CMP0_CMPCOND_Msk (0x1ul << EADC_CMP0_CMPCOND_Pos) /*!< EADC_T::CMP0: CMPCOND Mask */ 1480 1481 #define EADC_CMP0_CMPSPL_Pos (3) /*!< EADC_T::CMP0: CMPSPL Position */ 1482 #define EADC_CMP0_CMPSPL_Msk (0x1ful << EADC_CMP0_CMPSPL_Pos) /*!< EADC_T::CMP0: CMPSPL Mask */ 1483 1484 #define EADC_CMP0_CMPMCNT_Pos (8) /*!< EADC_T::CMP0: CMPMCNT Position */ 1485 #define EADC_CMP0_CMPMCNT_Msk (0xful << EADC_CMP0_CMPMCNT_Pos) /*!< EADC_T::CMP0: CMPMCNT Mask */ 1486 1487 #define EADC_CMP0_CMPWEN_Pos (15) /*!< EADC_T::CMP0: CMPWEN Position */ 1488 #define EADC_CMP0_CMPWEN_Msk (0x1ul << EADC_CMP0_CMPWEN_Pos) /*!< EADC_T::CMP0: CMPWEN Mask */ 1489 1490 #define EADC_CMP0_CMPDAT_Pos (16) /*!< EADC_T::CMP0: CMPDAT Position */ 1491 #define EADC_CMP0_CMPDAT_Msk (0xffful << EADC_CMP0_CMPDAT_Pos) /*!< EADC_T::CMP0: CMPDAT Mask */ 1492 1493 #define EADC_CMP1_ADCMPEN_Pos (0) /*!< EADC_T::CMP1: ADCMPEN Position */ 1494 #define EADC_CMP1_ADCMPEN_Msk (0x1ul << EADC_CMP1_ADCMPEN_Pos) /*!< EADC_T::CMP1: ADCMPEN Mask */ 1495 1496 #define EADC_CMP1_ADCMPIE_Pos (1) /*!< EADC_T::CMP1: ADCMPIE Position */ 1497 #define EADC_CMP1_ADCMPIE_Msk (0x1ul << EADC_CMP1_ADCMPIE_Pos) /*!< EADC_T::CMP1: ADCMPIE Mask */ 1498 1499 #define EADC_CMP1_CMPCOND_Pos (2) /*!< EADC_T::CMP1: CMPCOND Position */ 1500 #define EADC_CMP1_CMPCOND_Msk (0x1ul << EADC_CMP1_CMPCOND_Pos) /*!< EADC_T::CMP1: CMPCOND Mask */ 1501 1502 #define EADC_CMP1_CMPSPL_Pos (3) /*!< EADC_T::CMP1: CMPSPL Position */ 1503 #define EADC_CMP1_CMPSPL_Msk (0x1ful << EADC_CMP1_CMPSPL_Pos) /*!< EADC_T::CMP1: CMPSPL Mask */ 1504 1505 #define EADC_CMP1_CMPMCNT_Pos (8) /*!< EADC_T::CMP1: CMPMCNT Position */ 1506 #define EADC_CMP1_CMPMCNT_Msk (0xful << EADC_CMP1_CMPMCNT_Pos) /*!< EADC_T::CMP1: CMPMCNT Mask */ 1507 1508 #define EADC_CMP1_CMPWEN_Pos (15) /*!< EADC_T::CMP1: CMPWEN Position */ 1509 #define EADC_CMP1_CMPWEN_Msk (0x1ul << EADC_CMP1_CMPWEN_Pos) /*!< EADC_T::CMP1: CMPWEN Mask */ 1510 1511 #define EADC_CMP1_CMPDAT_Pos (16) /*!< EADC_T::CMP1: CMPDAT Position */ 1512 #define EADC_CMP1_CMPDAT_Msk (0xffful << EADC_CMP1_CMPDAT_Pos) /*!< EADC_T::CMP1: CMPDAT Mask */ 1513 1514 #define EADC_CMP2_ADCMPEN_Pos (0) /*!< EADC_T::CMP2: ADCMPEN Position */ 1515 #define EADC_CMP2_ADCMPEN_Msk (0x1ul << EADC_CMP2_ADCMPEN_Pos) /*!< EADC_T::CMP2: ADCMPEN Mask */ 1516 1517 #define EADC_CMP2_ADCMPIE_Pos (1) /*!< EADC_T::CMP2: ADCMPIE Position */ 1518 #define EADC_CMP2_ADCMPIE_Msk (0x1ul << EADC_CMP2_ADCMPIE_Pos) /*!< EADC_T::CMP2: ADCMPIE Mask */ 1519 1520 #define EADC_CMP2_CMPCOND_Pos (2) /*!< EADC_T::CMP2: CMPCOND Position */ 1521 #define EADC_CMP2_CMPCOND_Msk (0x1ul << EADC_CMP2_CMPCOND_Pos) /*!< EADC_T::CMP2: CMPCOND Mask */ 1522 1523 #define EADC_CMP2_CMPSPL_Pos (3) /*!< EADC_T::CMP2: CMPSPL Position */ 1524 #define EADC_CMP2_CMPSPL_Msk (0x1ful << EADC_CMP2_CMPSPL_Pos) /*!< EADC_T::CMP2: CMPSPL Mask */ 1525 1526 #define EADC_CMP2_CMPMCNT_Pos (8) /*!< EADC_T::CMP2: CMPMCNT Position */ 1527 #define EADC_CMP2_CMPMCNT_Msk (0xful << EADC_CMP2_CMPMCNT_Pos) /*!< EADC_T::CMP2: CMPMCNT Mask */ 1528 1529 #define EADC_CMP2_CMPWEN_Pos (15) /*!< EADC_T::CMP2: CMPWEN Position */ 1530 #define EADC_CMP2_CMPWEN_Msk (0x1ul << EADC_CMP2_CMPWEN_Pos) /*!< EADC_T::CMP2: CMPWEN Mask */ 1531 1532 #define EADC_CMP2_CMPDAT_Pos (16) /*!< EADC_T::CMP2: CMPDAT Position */ 1533 #define EADC_CMP2_CMPDAT_Msk (0xffful << EADC_CMP2_CMPDAT_Pos) /*!< EADC_T::CMP2: CMPDAT Mask */ 1534 1535 #define EADC_CMP3_ADCMPEN_Pos (0) /*!< EADC_T::CMP3: ADCMPEN Position */ 1536 #define EADC_CMP3_ADCMPEN_Msk (0x1ul << EADC_CMP3_ADCMPEN_Pos) /*!< EADC_T::CMP3: ADCMPEN Mask */ 1537 1538 #define EADC_CMP3_ADCMPIE_Pos (1) /*!< EADC_T::CMP3: ADCMPIE Position */ 1539 #define EADC_CMP3_ADCMPIE_Msk (0x1ul << EADC_CMP3_ADCMPIE_Pos) /*!< EADC_T::CMP3: ADCMPIE Mask */ 1540 1541 #define EADC_CMP3_CMPCOND_Pos (2) /*!< EADC_T::CMP3: CMPCOND Position */ 1542 #define EADC_CMP3_CMPCOND_Msk (0x1ul << EADC_CMP3_CMPCOND_Pos) /*!< EADC_T::CMP3: CMPCOND Mask */ 1543 1544 #define EADC_CMP3_CMPSPL_Pos (3) /*!< EADC_T::CMP3: CMPSPL Position */ 1545 #define EADC_CMP3_CMPSPL_Msk (0x1ful << EADC_CMP3_CMPSPL_Pos) /*!< EADC_T::CMP3: CMPSPL Mask */ 1546 1547 #define EADC_CMP3_CMPMCNT_Pos (8) /*!< EADC_T::CMP3: CMPMCNT Position */ 1548 #define EADC_CMP3_CMPMCNT_Msk (0xful << EADC_CMP3_CMPMCNT_Pos) /*!< EADC_T::CMP3: CMPMCNT Mask */ 1549 1550 #define EADC_CMP3_CMPWEN_Pos (15) /*!< EADC_T::CMP3: CMPWEN Position */ 1551 #define EADC_CMP3_CMPWEN_Msk (0x1ul << EADC_CMP3_CMPWEN_Pos) /*!< EADC_T::CMP3: CMPWEN Mask */ 1552 1553 #define EADC_CMP3_CMPDAT_Pos (16) /*!< EADC_T::CMP3: CMPDAT Position */ 1554 #define EADC_CMP3_CMPDAT_Msk (0xffful << EADC_CMP3_CMPDAT_Pos) /*!< EADC_T::CMP3: CMPDAT Mask */ 1555 1556 #define EADC_STATUS0_VALID_Pos (0) /*!< EADC_T::STATUS0: VALID Position */ 1557 #define EADC_STATUS0_VALID_Msk (0xfffful << EADC_STATUS0_VALID_Pos) /*!< EADC_T::STATUS0: VALID Mask */ 1558 1559 #define EADC_STATUS0_OV_Pos (16) /*!< EADC_T::STATUS0: OV Position */ 1560 #define EADC_STATUS0_OV_Msk (0xfffful << EADC_STATUS0_OV_Pos) /*!< EADC_T::STATUS0: OV Mask */ 1561 1562 #define EADC_STATUS1_VALID_Pos (0) /*!< EADC_T::STATUS1: VALID Position */ 1563 #define EADC_STATUS1_VALID_Msk (0x7ul << EADC_STATUS1_VALID_Pos) /*!< EADC_T::STATUS1: VALID Mask */ 1564 1565 #define EADC_STATUS1_OV_Pos (16) /*!< EADC_T::STATUS1: OV Position */ 1566 #define EADC_STATUS1_OV_Msk (0x7ul << EADC_STATUS1_OV_Pos) /*!< EADC_T::STATUS1: OV Mask */ 1567 1568 #define EADC_STATUS2_ADIF0_Pos (0) /*!< EADC_T::STATUS2: ADIF0 Position */ 1569 #define EADC_STATUS2_ADIF0_Msk (0x1ul << EADC_STATUS2_ADIF0_Pos) /*!< EADC_T::STATUS2: ADIF0 Mask */ 1570 1571 #define EADC_STATUS2_ADIF1_Pos (1) /*!< EADC_T::STATUS2: ADIF1 Position */ 1572 #define EADC_STATUS2_ADIF1_Msk (0x1ul << EADC_STATUS2_ADIF1_Pos) /*!< EADC_T::STATUS2: ADIF1 Mask */ 1573 1574 #define EADC_STATUS2_ADIF2_Pos (2) /*!< EADC_T::STATUS2: ADIF2 Position */ 1575 #define EADC_STATUS2_ADIF2_Msk (0x1ul << EADC_STATUS2_ADIF2_Pos) /*!< EADC_T::STATUS2: ADIF2 Mask */ 1576 1577 #define EADC_STATUS2_ADIF3_Pos (3) /*!< EADC_T::STATUS2: ADIF3 Position */ 1578 #define EADC_STATUS2_ADIF3_Msk (0x1ul << EADC_STATUS2_ADIF3_Pos) /*!< EADC_T::STATUS2: ADIF3 Mask */ 1579 1580 #define EADC_STATUS2_ADCMPF0_Pos (4) /*!< EADC_T::STATUS2: ADCMPF0 Position */ 1581 #define EADC_STATUS2_ADCMPF0_Msk (0x1ul << EADC_STATUS2_ADCMPF0_Pos) /*!< EADC_T::STATUS2: ADCMPF0 Mask */ 1582 1583 #define EADC_STATUS2_ADCMPF1_Pos (5) /*!< EADC_T::STATUS2: ADCMPF1 Position */ 1584 #define EADC_STATUS2_ADCMPF1_Msk (0x1ul << EADC_STATUS2_ADCMPF1_Pos) /*!< EADC_T::STATUS2: ADCMPF1 Mask */ 1585 1586 #define EADC_STATUS2_ADCMPF2_Pos (6) /*!< EADC_T::STATUS2: ADCMPF2 Position */ 1587 #define EADC_STATUS2_ADCMPF2_Msk (0x1ul << EADC_STATUS2_ADCMPF2_Pos) /*!< EADC_T::STATUS2: ADCMPF2 Mask */ 1588 1589 #define EADC_STATUS2_ADCMPF3_Pos (7) /*!< EADC_T::STATUS2: ADCMPF3 Position */ 1590 #define EADC_STATUS2_ADCMPF3_Msk (0x1ul << EADC_STATUS2_ADCMPF3_Pos) /*!< EADC_T::STATUS2: ADCMPF3 Mask */ 1591 1592 #define EADC_STATUS2_ADOVIF0_Pos (8) /*!< EADC_T::STATUS2: ADOVIF0 Position */ 1593 #define EADC_STATUS2_ADOVIF0_Msk (0x1ul << EADC_STATUS2_ADOVIF0_Pos) /*!< EADC_T::STATUS2: ADOVIF0 Mask */ 1594 1595 #define EADC_STATUS2_ADOVIF1_Pos (9) /*!< EADC_T::STATUS2: ADOVIF1 Position */ 1596 #define EADC_STATUS2_ADOVIF1_Msk (0x1ul << EADC_STATUS2_ADOVIF1_Pos) /*!< EADC_T::STATUS2: ADOVIF1 Mask */ 1597 1598 #define EADC_STATUS2_ADOVIF2_Pos (10) /*!< EADC_T::STATUS2: ADOVIF2 Position */ 1599 #define EADC_STATUS2_ADOVIF2_Msk (0x1ul << EADC_STATUS2_ADOVIF2_Pos) /*!< EADC_T::STATUS2: ADOVIF2 Mask */ 1600 1601 #define EADC_STATUS2_ADOVIF3_Pos (11) /*!< EADC_T::STATUS2: ADOVIF3 Position */ 1602 #define EADC_STATUS2_ADOVIF3_Msk (0x1ul << EADC_STATUS2_ADOVIF3_Pos) /*!< EADC_T::STATUS2: ADOVIF3 Mask */ 1603 1604 #define EADC_STATUS2_ADCMPO0_Pos (12) /*!< EADC_T::STATUS2: ADCMPO0 Position */ 1605 #define EADC_STATUS2_ADCMPO0_Msk (0x1ul << EADC_STATUS2_ADCMPO0_Pos) /*!< EADC_T::STATUS2: ADCMPO0 Mask */ 1606 1607 #define EADC_STATUS2_ADCMPO1_Pos (13) /*!< EADC_T::STATUS2: ADCMPO1 Position */ 1608 #define EADC_STATUS2_ADCMPO1_Msk (0x1ul << EADC_STATUS2_ADCMPO1_Pos) /*!< EADC_T::STATUS2: ADCMPO1 Mask */ 1609 1610 #define EADC_STATUS2_ADCMPO2_Pos (14) /*!< EADC_T::STATUS2: ADCMPO2 Position */ 1611 #define EADC_STATUS2_ADCMPO2_Msk (0x1ul << EADC_STATUS2_ADCMPO2_Pos) /*!< EADC_T::STATUS2: ADCMPO2 Mask */ 1612 1613 #define EADC_STATUS2_ADCMPO3_Pos (15) /*!< EADC_T::STATUS2: ADCMPO3 Position */ 1614 #define EADC_STATUS2_ADCMPO3_Msk (0x1ul << EADC_STATUS2_ADCMPO3_Pos) /*!< EADC_T::STATUS2: ADCMPO3 Mask */ 1615 1616 #define EADC_STATUS2_CHANNEL_Pos (16) /*!< EADC_T::STATUS2: CHANNEL Position */ 1617 #define EADC_STATUS2_CHANNEL_Msk (0x1ful << EADC_STATUS2_CHANNEL_Pos) /*!< EADC_T::STATUS2: CHANNEL Mask */ 1618 1619 #define EADC_STATUS2_BUSY_Pos (23) /*!< EADC_T::STATUS2: BUSY Position */ 1620 #define EADC_STATUS2_BUSY_Msk (0x1ul << EADC_STATUS2_BUSY_Pos) /*!< EADC_T::STATUS2: BUSY Mask */ 1621 1622 #define EADC_STATUS2_ADOVIF_Pos (24) /*!< EADC_T::STATUS2: ADOVIF Position */ 1623 #define EADC_STATUS2_ADOVIF_Msk (0x1ul << EADC_STATUS2_ADOVIF_Pos) /*!< EADC_T::STATUS2: ADOVIF Mask */ 1624 1625 #define EADC_STATUS2_STOVF_Pos (25) /*!< EADC_T::STATUS2: STOVF Position */ 1626 #define EADC_STATUS2_STOVF_Msk (0x1ul << EADC_STATUS2_STOVF_Pos) /*!< EADC_T::STATUS2: STOVF Mask */ 1627 1628 #define EADC_STATUS2_AVALID_Pos (26) /*!< EADC_T::STATUS2: AVALID Position */ 1629 #define EADC_STATUS2_AVALID_Msk (0x1ul << EADC_STATUS2_AVALID_Pos) /*!< EADC_T::STATUS2: AVALID Mask */ 1630 1631 #define EADC_STATUS2_AOV_Pos (27) /*!< EADC_T::STATUS2: AOV Position */ 1632 #define EADC_STATUS2_AOV_Msk (0x1ul << EADC_STATUS2_AOV_Pos) /*!< EADC_T::STATUS2: AOV Mask */ 1633 1634 #define EADC_STATUS3_CURSPL_Pos (0) /*!< EADC_T::STATUS3: CURSPL Position */ 1635 #define EADC_STATUS3_CURSPL_Msk (0x1ful << EADC_STATUS3_CURSPL_Pos) /*!< EADC_T::STATUS3: CURSPL Mask */ 1636 1637 #define EADC_DDAT0_RESULT_Pos (0) /*!< EADC_T::DDAT0: RESULT Position */ 1638 #define EADC_DDAT0_RESULT_Msk (0xfffful << EADC_DDAT0_RESULT_Pos) /*!< EADC_T::DDAT0: RESULT Mask */ 1639 1640 #define EADC_DDAT0_OV_Pos (16) /*!< EADC_T::DDAT0: OV Position */ 1641 #define EADC_DDAT0_OV_Msk (0x1ul << EADC_DDAT0_OV_Pos) /*!< EADC_T::DDAT0: OV Mask */ 1642 1643 #define EADC_DDAT0_VALID_Pos (17) /*!< EADC_T::DDAT0: VALID Position */ 1644 #define EADC_DDAT0_VALID_Msk (0x1ul << EADC_DDAT0_VALID_Pos) /*!< EADC_T::DDAT0: VALID Mask */ 1645 1646 #define EADC_DDAT1_RESULT_Pos (0) /*!< EADC_T::DDAT1: RESULT Position */ 1647 #define EADC_DDAT1_RESULT_Msk (0xfffful << EADC_DDAT1_RESULT_Pos) /*!< EADC_T::DDAT1: RESULT Mask */ 1648 1649 #define EADC_DDAT1_OV_Pos (16) /*!< EADC_T::DDAT1: OV Position */ 1650 #define EADC_DDAT1_OV_Msk (0x1ul << EADC_DDAT1_OV_Pos) /*!< EADC_T::DDAT1: OV Mask */ 1651 1652 #define EADC_DDAT1_VALID_Pos (17) /*!< EADC_T::DDAT1: VALID Position */ 1653 #define EADC_DDAT1_VALID_Msk (0x1ul << EADC_DDAT1_VALID_Pos) /*!< EADC_T::DDAT1: VALID Mask */ 1654 1655 #define EADC_DDAT2_RESULT_Pos (0) /*!< EADC_T::DDAT2: RESULT Position */ 1656 #define EADC_DDAT2_RESULT_Msk (0xfffful << EADC_DDAT2_RESULT_Pos) /*!< EADC_T::DDAT2: RESULT Mask */ 1657 1658 #define EADC_DDAT2_OV_Pos (16) /*!< EADC_T::DDAT2: OV Position */ 1659 #define EADC_DDAT2_OV_Msk (0x1ul << EADC_DDAT2_OV_Pos) /*!< EADC_T::DDAT2: OV Mask */ 1660 1661 #define EADC_DDAT2_VALID_Pos (17) /*!< EADC_T::DDAT2: VALID Position */ 1662 #define EADC_DDAT2_VALID_Msk (0x1ul << EADC_DDAT2_VALID_Pos) /*!< EADC_T::DDAT2: VALID Mask */ 1663 1664 #define EADC_DDAT3_RESULT_Pos (0) /*!< EADC_T::DDAT3: RESULT Position */ 1665 #define EADC_DDAT3_RESULT_Msk (0xfffful << EADC_DDAT3_RESULT_Pos) /*!< EADC_T::DDAT3: RESULT Mask */ 1666 1667 #define EADC_DDAT3_OV_Pos (16) /*!< EADC_T::DDAT3: OV Position */ 1668 #define EADC_DDAT3_OV_Msk (0x1ul << EADC_DDAT3_OV_Pos) /*!< EADC_T::DDAT3: OV Mask */ 1669 1670 #define EADC_DDAT3_VALID_Pos (17) /*!< EADC_T::DDAT3: VALID Position */ 1671 #define EADC_DDAT3_VALID_Msk (0x1ul << EADC_DDAT3_VALID_Pos) /*!< EADC_T::DDAT3: VALID Mask */ 1672 1673 #define EADC_PWRM_PWUPRDY_Pos (0) /*!< EADC_T::PWRM: PWUPRDY Position */ 1674 #define EADC_PWRM_PWUPRDY_Msk (0x1ul << EADC_PWRM_PWUPRDY_Pos) /*!< EADC_T::PWRM: PWUPRDY Mask */ 1675 1676 #define EADC_PWRM_PWUCALEN_Pos (1) /*!< EADC_T::PWRM: PWUCALEN Position */ 1677 #define EADC_PWRM_PWUCALEN_Msk (0x1ul << EADC_PWRM_PWUCALEN_Pos) /*!< EADC_T::PWRM: PWUCALEN Mask */ 1678 1679 #define EADC_PWRM_PWDMOD_Pos (2) /*!< EADC_T::PWRM: PWDMOD Position */ 1680 #define EADC_PWRM_PWDMOD_Msk (0x3ul << EADC_PWRM_PWDMOD_Pos) /*!< EADC_T::PWRM: PWDMOD Mask */ 1681 1682 #define EADC_PWRM_LDOSUT_Pos (8) /*!< EADC_T::PWRM: LDOSUT Position */ 1683 #define EADC_PWRM_LDOSUT_Msk (0xffful << EADC_PWRM_LDOSUT_Pos) /*!< EADC_T::PWRM: LDOSUT Mask */ 1684 1685 #define EADC_CALCTL_CALSTART_Pos (1) /*!< EADC_T::CALCTL: CALSTART Position */ 1686 #define EADC_CALCTL_CALSTART_Msk (0x1ul << EADC_CALCTL_CALSTART_Pos) /*!< EADC_T::CALCTL: CALSTART Mask */ 1687 1688 #define EADC_CALCTL_CALDONE_Pos (2) /*!< EADC_T::CALCTL: CALDONE Position */ 1689 #define EADC_CALCTL_CALDONE_Msk (0x1ul << EADC_CALCTL_CALDONE_Pos) /*!< EADC_T::CALCTL: CALDONE Mask */ 1690 1691 #define EADC_CALCTL_CALSEL_Pos (3) /*!< EADC_T::CALCTL: CALSEL Position */ 1692 #define EADC_CALCTL_CALSEL_Msk (0x1ul << EADC_CALCTL_CALSEL_Pos) /*!< EADC_T::CALCTL: CALSEL Mask */ 1693 1694 #define EADC_CALDWRD_CALWORD_Pos (0) /*!< EADC_T::CALDWRD: CALWORD Position */ 1695 #define EADC_CALDWRD_CALWORD_Msk (0x7ful << EADC_CALDWRD_CALWORD_Pos) /*!< EADC_T::CALDWRD: CALWORD Mask */ 1696 1697 #define EADC_PDMACTL_PDMATEN_Pos (0) /*!< EADC_T::PDMACTL: PDMATEN Position */ 1698 #define EADC_PDMACTL_PDMATEN_Msk (0x7fffful << EADC_PDMACTL_PDMATEN_Pos) /*!< EADC_T::PDMACTL: PDMATEN Mask */ 1699 1700 1701 /**@}*/ /* EADC_CONST */ 1702 /**@}*/ /* end of EADC register group */ 1703 /**@}*/ /* end of REGISTER group */ 1704 1705 1706 1707 #endif /* __EADC_REG_H__ */ 1708
