1 /**************************************************************************//** 2 * @file dac_reg.h 3 * @version V1.00 4 * @brief DAC register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __DAC_REG_H__ 10 #define __DAC_REG_H__ 11 12 13 /** @addtogroup REGISTER Control Register 14 15 @{ 16 17 */ 18 19 /*---------------------- Digital to Analog Converter -------------------------*/ 20 /** 21 @addtogroup DAC Digital to Analog Converter(DAC) 22 Memory Mapped Structure for DAC Controller 23 @{ 24 */ 25 26 27 typedef struct 28 { 29 30 31 32 /** 33 * @var DAC_T::CTL 34 * Offset: 0x00 DAC Control Register 35 * --------------------------------------------------------------------------------------------------- 36 * |Bits |Field |Descriptions 37 * | :----: | :----: | :---- | 38 * |[0] |DACEN |DAC Enable Bit 39 * | | |0 = DAC is Disabled. 40 * | | |1 = DAC is Enabled. 41 * |[1] |DACIEN |DAC Interrupt Enable Bit 42 * | | |0 = Interrupt is Disabled. 43 * | | |1 = Interrupt is Enabled. 44 * |[2] |DMAEN |DMA Mode Enable Bit 45 * | | |0 = DMA mode Disabled. 46 * | | |1 = DMA mode Enabled. 47 * |[3] |DMAURIEN |DMA Under-run Interrupt Enable Bit 48 * | | |0 = DMA under-run interrupt Disabled. 49 * | | |1 = DMA under-run interrupt Enabled. 50 * |[4] |TRGEN |Trigger Mode Enable Bit 51 * | | |0 = DAC event trigger mode Disabled. 52 * | | |1 = DAC event trigger mode Enabled. 53 * |[7:5] |TRGSEL |Trigger Source Selection 54 * | | |000 = Software trigger. 55 * | | |001 = External pin DAC0_ST trigger. 56 * | | |010 = Timer 0 trigger. 57 * | | |011 = Timer 1 trigger. 58 * | | |100 = Timer 2 trigger. 59 * | | |101 = Timer 3 trigger. 60 * | | |110 = EPWM0 trigger. 61 * | | |111 = EPWM1 trigger. 62 * |[8] |BYPASS |Bypass Buffer Mode 63 * | | |0 = Output voltage buffer Enabled. 64 * | | |1 = Output voltage buffer Disabled. 65 * |[10] |LALIGN |DAC Data Left-aligned Enabled Control 66 * | | |0 = Right alignment. 67 * | | |1 = Left alignment. 68 * |[13:12] |ETRGSEL |External Pin Trigger Selection 69 * | | |00 = Low level trigger. 70 * | | |01 = High level trigger. 71 * | | |10 = Falling edge trigger. 72 * | | |11 = Rising edge trigger. 73 * |[15:14] |BWSEL |DAC Data Bit-width Selection 74 * | | |00 = data is 12 bits. 75 * | | |01 = data is 8 bits. 76 * | | |Others = reserved. 77 * |[16] |GRPEN |DAC Group Mode Enable Bit 78 * | | |0 = DAC0 and DAC1 are not grouped. 79 * | | |1 = DAC0 and DAC1 are grouped. 80 * @var DAC_T::SWTRG 81 * Offset: 0x04 DAC Software Trigger Control Register 82 * --------------------------------------------------------------------------------------------------- 83 * |Bits |Field |Descriptions 84 * | :----: | :----: | :---- | 85 * |[0] |SWTRG |Software Trigger 86 * | | |0 = Software trigger Disabled. 87 * | | |1 = Software trigger Enabled. 88 * | | |User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0. 89 * @var DAC_T::DAT 90 * Offset: 0x08 DAC Data Holding Register 91 * --------------------------------------------------------------------------------------------------- 92 * |Bits |Field |Descriptions 93 * | :----: | :----: | :---- | 94 * |[15:0] |DACDAT |DAC 12-bit Holding Data 95 * | | |These bits are written by user software which specifies 12-bit conversion data for DAC output. 96 * | | |The unused bits (DACDAT[3:0] in left-alignment mode and DACDAT[15:12] in right alignment mode) are ignored by DAC controller hardware. 97 * | | |12 bit left alignment: user has to load data into DACDAT[15:4] bits. 98 * | | |12 bit right alignment: user has to load data into DACDAT[11:0] bits. 99 * @var DAC_T::DATOUT 100 * Offset: 0x0C DAC Data Output Register 101 * --------------------------------------------------------------------------------------------------- 102 * |Bits |Field |Descriptions 103 * | :----: | :----: | :---- | 104 * |[11:0] |DATOUT |DAC 12-bit Output Data 105 * | | |These bits are current digital data for DAC output conversion. 106 * | | |It is loaded from DAC_DAT register and user cannot write it directly. 107 * @var DAC_T::STATUS 108 * Offset: 0x10 DAC Status Register 109 * --------------------------------------------------------------------------------------------------- 110 * |Bits |Field |Descriptions 111 * | :----: | :----: | :---- | 112 * |[0] |FINISH |DAC Conversion Complete Finish Flag 113 * | | |0 = DAC is in conversion state. 114 * | | |1 = DAC conversion finish. 115 * | | |This bit set to 1 when conversion time counter counts to SETTLET. 116 * | | |It is cleared to 0 when DAC starts a new conversion. 117 * | | |User writes 1 to clear this bit to 0. 118 * |[1] |DMAUDR |DMA Under-run Interrupt Flag 119 * | | |0 = No DMA under-run error condition occurred. 120 * | | |1 = DMA under-run error condition occurred. 121 * | | |User writes 1 to clear this bit. 122 * |[8] |BUSY |DAC Busy Flag (Read Only) 123 * | | |0 = DAC is ready for next conversion. 124 * | | |1 = DAC is busy in conversion. 125 * | | |This is read only bit. 126 * @var DAC_T::TCTL 127 * Offset: 0x14 DAC Timing Control Register 128 * --------------------------------------------------------------------------------------------------- 129 * |Bits |Field |Descriptions 130 * | :----: | :----: | :---- | 131 * |[9:0] |SETTLET |DAC Output Settling Time 132 * | | |User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed. 133 * | | |For example, DAC controller clock speed is 64MHz and DAC conversion setting time is 1 us, SETTLET value must be greater than 0x40. 134 */ 135 __IO uint32_t CTL; /*!< [0x0000] DAC Control Register */ 136 __IO uint32_t SWTRG; /*!< [0x0004] DAC Software Trigger Control Register */ 137 __IO uint32_t DAT; /*!< [0x0008] DAC Data Holding Register */ 138 __I uint32_t DATOUT; /*!< [0x000c] DAC Data Output Register */ 139 __IO uint32_t STATUS; /*!< [0x0010] DAC Status Register */ 140 __IO uint32_t TCTL; /*!< [0x0014] DAC Timing Control Register */ 141 142 } DAC_T; 143 144 /** 145 @addtogroup DAC_CONST DAC Bit Field Definition 146 Constant Definitions for DAC Controller 147 @{ 148 */ 149 150 #define DAC_CTL_DACEN_Pos (0) /*!< DAC_T::CTL: DACEN Position */ 151 #define DAC_CTL_DACEN_Msk (0x1ul << DAC_CTL_DACEN_Pos) /*!< DAC_T::CTL: DACEN Mask */ 152 153 #define DAC_CTL_DACIEN_Pos (1) /*!< DAC_T::CTL: DACIEN Position */ 154 #define DAC_CTL_DACIEN_Msk (0x1ul << DAC_CTL_DACIEN_Pos) /*!< DAC_T::CTL: DACIEN Mask */ 155 156 #define DAC_CTL_DMAEN_Pos (2) /*!< DAC_T::CTL: DMAEN Position */ 157 #define DAC_CTL_DMAEN_Msk (0x1ul << DAC_CTL_DMAEN_Pos) /*!< DAC_T::CTL: DMAEN Mask */ 158 159 #define DAC_CTL_DMAURIEN_Pos (3) /*!< DAC_T::CTL: DMAURIEN Position */ 160 #define DAC_CTL_DMAURIEN_Msk (0x1ul << DAC_CTL_DMAURIEN_Pos) /*!< DAC_T::CTL: DMAURIEN Mask */ 161 162 #define DAC_CTL_TRGEN_Pos (4) /*!< DAC_T::CTL: TRGEN Position */ 163 #define DAC_CTL_TRGEN_Msk (0x1ul << DAC_CTL_TRGEN_Pos) /*!< DAC_T::CTL: TRGEN Mask */ 164 165 #define DAC_CTL_TRGSEL_Pos (5) /*!< DAC_T::CTL: TRGSEL Position */ 166 #define DAC_CTL_TRGSEL_Msk (0x7ul << DAC_CTL_TRGSEL_Pos) /*!< DAC_T::CTL: TRGSEL Mask */ 167 168 #define DAC_CTL_BYPASS_Pos (8) /*!< DAC_T::CTL: BYPASS Position */ 169 #define DAC_CTL_BYPASS_Msk (0x1ul << DAC_CTL_BYPASS_Pos) /*!< DAC_T::CTL: BYPASS Mask */ 170 171 #define DAC_CTL_LALIGN_Pos (10) /*!< DAC_T::CTL: LALIGN Position */ 172 #define DAC_CTL_LALIGN_Msk (0x1ul << DAC_CTL_LALIGN_Pos) /*!< DAC_T::CTL: LALIGN Mask */ 173 174 #define DAC_CTL_ETRGSEL_Pos (12) /*!< DAC_T::CTL: ETRGSEL Position */ 175 #define DAC_CTL_ETRGSEL_Msk (0x3ul << DAC_CTL_ETRGSEL_Pos) /*!< DAC_T::CTL: ETRGSEL Mask */ 176 177 #define DAC_CTL_BWSEL_Pos (14) /*!< DAC_T::CTL: BWSEL Position */ 178 #define DAC_CTL_BWSEL_Msk (0x3ul << DAC_CTL_BWSEL_Pos) /*!< DAC_T::CTL: BWSEL Mask */ 179 180 #define DAC_CTL_GRPEN_Pos (16) /*!< DAC_T::CTL: GRPEN Position */ 181 #define DAC_CTL_GRPEN_Msk (0x1ul << DAC_CTL_GRPEN_Pos) /*!< DAC_T::CTL: GRPEN Mask */ 182 183 #define DAC_SWTRG_SWTRG_Pos (0) /*!< DAC_T::SWTRG: SWTRG Position */ 184 #define DAC_SWTRG_SWTRG_Msk (0x1ul << DAC_SWTRG_SWTRG_Pos) /*!< DAC_T::SWTRG: SWTRG Mask */ 185 186 #define DAC_DAT_DACDAT_Pos (0) /*!< DAC_T::DAT: DACDAT Position */ 187 #define DAC_DAT_DACDAT_Msk (0xfffful << DAC_DAT_DACDAT_Pos) /*!< DAC_T::DAT: DACDAT Mask */ 188 189 #define DAC_DATOUT_DATOUT_Pos (0) /*!< DAC_T::DATOUT: DATOUT Position */ 190 #define DAC_DATOUT_DATOUT_Msk (0xffful << DAC_DATOUT_DATOUT_Pos) /*!< DAC_T::DATOUT: DATOUT Mask */ 191 192 #define DAC_STATUS_FINISH_Pos (0) /*!< DAC_T::STATUS: FINISH Position */ 193 #define DAC_STATUS_FINISH_Msk (0x1ul << DAC_STATUS_FINISH_Pos) /*!< DAC_T::STATUS: FINISH Mask */ 194 195 #define DAC_STATUS_DMAUDR_Pos (1) /*!< DAC_T::STATUS: DMAUDR Position */ 196 #define DAC_STATUS_DMAUDR_Msk (0x1ul << DAC_STATUS_DMAUDR_Pos) /*!< DAC_T::STATUS: DMAUDR Mask */ 197 198 #define DAC_STATUS_BUSY_Pos (8) /*!< DAC_T::STATUS: BUSY Position */ 199 #define DAC_STATUS_BUSY_Msk (0x1ul << DAC_STATUS_BUSY_Pos) /*!< DAC_T::STATUS: BUSY Mask */ 200 201 #define DAC_TCTL_SETTLET_Pos (0) /*!< DAC_T::TCTL: SETTLET Position */ 202 #define DAC_TCTL_SETTLET_Msk (0x3fful << DAC_TCTL_SETTLET_Pos) /*!< DAC_T::TCTL: SETTLET Mask */ 203 204 /**@}*/ /* DAC_CONST */ 205 /**@}*/ /* end of DAC register group */ 206 /**@}*/ /* end of REGISTER group */ 207 208 #endif /* __DAC_REG_H__ */ 209
