1 /*
2  * Copyright (c) 2017-2022 Arm Limited. All rights reserved.
3  * Copyright (c) 2020 Nordic Semiconductor ASA. All rights reserved.
4  * Copyright (c) 2021 Laird Connectivity. All rights reserved.
5  *
6  * Licensed under the Apache License, Version 2.0 (the "License");
7  * you may not use this file except in compliance with the License.
8  * You may obtain a copy of the License at
9  *
10  *     http://www.apache.org/licenses/LICENSE-2.0
11  *
12  * Unless required by applicable law or agreed to in writing, software
13  * distributed under the License is distributed on an "AS IS" BASIS,
14  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15  * See the License for the specific language governing permissions and
16  * limitations under the License.
17  */
18 
19 #ifndef __REGION_DEFS_H__
20 #define __REGION_DEFS_H__
21 
22 #include "flash_layout.h"
23 
24 #define BL2_HEAP_SIZE           (0x00001000)
25 #define BL2_MSP_STACK_SIZE      (0x00002000)
26 
27 #ifdef ENABLE_HEAP
28     #define S_HEAP_SIZE             (0x0000200)
29 #endif
30 
31 #define S_MSP_STACK_SIZE        (0x00000800)
32 #define S_PSP_STACK_SIZE        (0x00000800)
33 
34 #define NS_HEAP_SIZE            (0x00001000)
35 #define NS_STACK_SIZE           (0x000001E0)
36 
37 /* Size of nRF SPU (Nordic IDAU) regions */
38 #define SPU_FLASH_REGION_SIZE   (0x00004000)
39 #define SPU_SRAM_REGION_SIZE    (0x00002000)
40 
41 /*
42  * SPU flash region granularity is 16KB on nRF5340. Alignment
43  * of partitions is defined in accordance with this constraint.
44  */
45 #ifdef BL2
46 #ifndef LINK_TO_SECONDARY_PARTITION
47 #define S_IMAGE_PRIMARY_PARTITION_OFFSET   (FLASH_AREA_0_OFFSET)
48 #define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET)
49 #else
50 #define S_IMAGE_PRIMARY_PARTITION_OFFSET   (FLASH_AREA_2_OFFSET)
51 #define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET)
52 #endif /* !LINK_TO_SECONDARY_PARTITION */
53 #else
54 #define S_IMAGE_PRIMARY_PARTITION_OFFSET (0x0)
55 #endif /* BL2 */
56 
57 #ifndef LINK_TO_SECONDARY_PARTITION
58 #define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET \
59                                            + FLASH_S_PARTITION_SIZE)
60 #else
61 #define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET \
62                                            + FLASH_S_PARTITION_SIZE)
63 #endif /* !LINK_TO_SECONDARY_PARTITION */
64 
65 /* Boot partition structure if MCUBoot is used:
66  * 0x0_0000 Bootloader header
67  * 0x0_0400 Image area
68  * 0x0_FC00 Trailer
69  */
70 /* IMAGE_CODE_SIZE is the space available for the software binary image.
71  * It is less than the FLASH_S_PARTITION_SIZE + FLASH_NS_PARTITION_SIZE
72  * because we reserve space for the image header and trailer introduced
73  * by the bootloader.
74  */
75 
76 #if (!defined(MCUBOOT_IMAGE_NUMBER) || (MCUBOOT_IMAGE_NUMBER == 1)) && \
77     (NS_IMAGE_PRIMARY_PARTITION_OFFSET > S_IMAGE_PRIMARY_PARTITION_OFFSET)
78 /* If secure image and nonsecure image are concatenated, and nonsecure image
79  * locates at the higher memory range, then the secure image does not need
80  * the trailer area.
81  */
82 #define IMAGE_S_CODE_SIZE \
83             (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE)
84 #else
85 #define IMAGE_S_CODE_SIZE \
86             (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
87 #endif
88 
89 #define IMAGE_NS_CODE_SIZE \
90             (FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
91 
92 /* Alias definitions for secure and non-secure areas*/
93 #define S_ROM_ALIAS(x)  (S_ROM_ALIAS_BASE + (x))
94 #define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x))
95 
96 #define S_RAM_ALIAS(x)  (S_RAM_ALIAS_BASE + (x))
97 #define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + (x))
98 
99 /* Secure regions */
100 #define S_IMAGE_PRIMARY_AREA_OFFSET \
101                         (S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
102 #define S_CODE_START    (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET))
103 #define S_CODE_SIZE     (IMAGE_S_CODE_SIZE)
104 #define S_CODE_LIMIT    (S_CODE_START + S_CODE_SIZE - 1)
105 
106 #define S_DATA_START    (S_RAM_ALIAS(0x0))
107 #define S_DATA_SIZE     (TOTAL_RAM_SIZE / 2)
108 #define S_DATA_LIMIT    (S_DATA_START + S_DATA_SIZE - 1)
109 
110 #define S_CODE_VECTOR_TABLE_SIZE (0x154)
111 
112 /* The veneers needs to be placed at the end of the secure image.
113  * This is because the NCS sub-region is defined as starting at the highest
114  * address of an SPU region and going downwards.
115  */
116 #define TFM_LINKER_VENEERS_LOCATION_END
117 /* The CMSE veneers shall be placed in an NSC region
118  * which will be placed in a secure SPU region with the given alignment.
119  */
120 #define TFM_LINKER_VENEERS_SIZE     (0x400)
121 /* The Nordic SPU has different alignment requirements than the ARM SAU, so
122  * these override the default start and end alignments. */
123 #define TFM_LINKER_VENEERS_START \
124             (ALIGN(SPU_FLASH_REGION_SIZE) - TFM_LINKER_VENEERS_SIZE + \
125                 (. > (ALIGN(SPU_FLASH_REGION_SIZE) - TFM_LINKER_VENEERS_SIZE) \
126                     ? SPU_FLASH_REGION_SIZE : 0))
127 
128 #define TFM_LINKER_VENEERS_END ALIGN(SPU_FLASH_REGION_SIZE)
129 
130 /* Non-secure regions */
131 #define NS_IMAGE_PRIMARY_AREA_OFFSET \
132                         (NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
133 #define NS_CODE_START   (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_AREA_OFFSET))
134 #define NS_CODE_SIZE    (IMAGE_NS_CODE_SIZE)
135 #define NS_CODE_LIMIT   (NS_CODE_START + NS_CODE_SIZE - 1)
136 
137 #define NS_DATA_START   (NS_RAM_ALIAS(S_DATA_SIZE))
138 #define NS_DATA_SIZE    (TOTAL_RAM_SIZE - S_DATA_SIZE)
139 #define NS_DATA_LIMIT   (NS_DATA_START + NS_DATA_SIZE - 1)
140 
141 /* NS partition information is used for SPU configuration */
142 #define NS_PARTITION_START \
143             (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_PARTITION_OFFSET))
144 #define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE)
145 
146 /* Secondary partition for new images in case of firmware upgrade */
147 #define SECONDARY_PARTITION_START \
148             (NS_ROM_ALIAS(S_IMAGE_SECONDARY_PARTITION_OFFSET))
149 #define SECONDARY_PARTITION_SIZE (FLASH_S_PARTITION_SIZE + \
150                                   FLASH_NS_PARTITION_SIZE)
151 
152 #ifdef BL2
153 /* Bootloader regions */
154 #define BL2_CODE_START    (S_ROM_ALIAS(FLASH_AREA_BL2_OFFSET))
155 #define BL2_CODE_SIZE     (FLASH_AREA_BL2_SIZE)
156 #define BL2_CODE_LIMIT    (BL2_CODE_START + BL2_CODE_SIZE - 1)
157 
158 #define BL2_DATA_START    (S_RAM_ALIAS(0x0))
159 #define BL2_DATA_SIZE     (TOTAL_RAM_SIZE)
160 #define BL2_DATA_LIMIT    (BL2_DATA_START + BL2_DATA_SIZE - 1)
161 #endif /* BL2 */
162 
163 /* Shared data area between bootloader and runtime firmware.
164  * Shared data area is allocated at the beginning of the RAM, it is overlapping
165  * with TF-M Secure code's MSP stack
166  */
167 #define BOOT_TFM_SHARED_DATA_BASE S_RAM_ALIAS_BASE
168 #define BOOT_TFM_SHARED_DATA_SIZE (0x400)
169 #define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \
170                                     BOOT_TFM_SHARED_DATA_SIZE - 1)
171 
172 #endif /* __REGION_DEFS_H__ */
173