1 /*
2  * Copyright (c) 2018-2021, Arm Limited. All rights reserved.
3  * Copyright (c) 2020-2023 Cypress Semiconductor Corporation (an Infineon company)
4  * or an affiliate of Cypress Semiconductor Corporation. All rights reserved.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  *
8  */
9 
10 #ifndef __TFM_PERIPHERALS_DEF_H__
11 #define __TFM_PERIPHERALS_DEF_H__
12 
13 #include "platform_irq.h"
14 
15 #ifdef __cplusplus
16 extern "C" {
17 #endif
18 
19 /*
20  * Quantized default IRQ priority, the value is:
21  * (Number of configurable priority) / 4: (1UL << __NVIC_PRIO_BITS) / 4
22  */
23 #define DEFAULT_IRQ_PRIORITY    (1UL << (__NVIC_PRIO_BITS - 2))
24 
25 #define TFM_TIMER0_IRQ              (NvicMux3_IRQn)
26 #define TFM_TIMER1_IRQ              (tcpwm_0_interrupts_1_IRQn)
27 
28 struct platform_data_t;
29 
30 extern struct platform_data_t tfm_peripheral_std_uart;
31 extern struct platform_data_t tfm_peripheral_timer0;
32 
33 #define TFM_PERIPHERAL_STD_UART     (&tfm_peripheral_std_uart)
34 #define TFM_PERIPHERAL_TIMER0       (&tfm_peripheral_timer0)
35 
36 /* NSPE-to-SPE interrupt */
37 #define MAILBOX_IRQ NvicMux7_IRQn
38 
39 #ifdef __cplusplus
40 }
41 #endif
42 
43 #endif /* __TFM_PERIPHERALS_DEF_H__ */
44