1 /* 2 * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved. 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __DRIVER_PPU_H__ 18 #define __DRIVER_PPU_H__ 19 20 #include "cy_prot.h" 21 #include "RTE_Device.h" 22 23 /* PSoC 6 has 6 different kinds of PPU */ 24 enum ppu_type { 25 MS_PPU_PR, 26 MS_PPU_FX, 27 PPU_PR, 28 PPU_GR, 29 GR_PPU_SL, 30 GR_PPU_RG, 31 NO_PPU 32 }; 33 34 typedef struct ppu_resources PPU_Resources; 35 36 /* Shared Driver wrapper functions */ 37 cy_en_prot_status_t PPU_Configure(const PPU_Resources *ppu_dev); 38 39 /* Per-PPU macros */ 40 #define DECLARE_MS_PPU_PR(N) extern const PPU_Resources N##_PPU_Resources; 41 #define DECLARE_MS_PPU_FX(N) extern const PPU_Resources N##_PPU_Resources; 42 #define DECLARE_PPU_PR(N) extern const PPU_Resources N##_PPU_Resources; 43 #define DECLARE_PPU_GR(N) extern const PPU_Resources N##_PPU_Resources; 44 #define DECLARE_GR_PPU_SL(N) extern const PPU_Resources N##_PPU_Resources; 45 #define DECLARE_GR_PPU_RG(N) extern const PPU_Resources N##_PPU_Resources; 46 47 #if (RTE_MS_PPU_PR7) 48 DECLARE_MS_PPU_PR(PR7) 49 #endif 50 51 #if (RTE_MS_PPU_PERI_MAIN) 52 DECLARE_MS_PPU_FX(PERI_MAIN) 53 #endif 54 55 #if (RTE_MS_PPU_PERI_GR0_GROUP) 56 DECLARE_MS_PPU_FX(PERI_GR0_GROUP) 57 #endif 58 59 #if (RTE_MS_PPU_PERI_GR1_GROUP) 60 DECLARE_MS_PPU_FX(PERI_GR1_GROUP) 61 #endif 62 63 #if (RTE_MS_PPU_PERI_GR2_GROUP) 64 DECLARE_MS_PPU_FX(PERI_GR2_GROUP) 65 #endif 66 67 #if (RTE_MS_PPU_PERI_GR3_GROUP) 68 DECLARE_MS_PPU_FX(PERI_GR3_GROUP) 69 #endif 70 71 #if (RTE_MS_PPU_PERI_GR4_GROUP) 72 DECLARE_MS_PPU_FX(PERI_GR4_GROUP) 73 #endif 74 75 #if (RTE_MS_PPU_PERI_GR6_GROUP) 76 DECLARE_MS_PPU_FX(PERI_GR6_GROUP) 77 #endif 78 79 #if (RTE_MS_PPU_PERI_GR9_GROUP) 80 DECLARE_MS_PPU_FX(PERI_GR9_GROUP) 81 #endif 82 83 #if (RTE_MS_PPU_PERI_GR10_GROUP) 84 DECLARE_MS_PPU_FX(PERI_GR10_GROUP) 85 #endif 86 87 #if (RTE_MS_PPU_PERI_TR) 88 DECLARE_MS_PPU_FX(PERI_TR) 89 #endif 90 91 #if (RTE_MS_PPU_CRYPTO_MAIN) 92 DECLARE_MS_PPU_FX(CRYPTO_MAIN) 93 #endif 94 95 #if (RTE_MS_PPU_CRYPTO_CRYPTO) 96 DECLARE_MS_PPU_FX(CRYPTO_CRYPTO) 97 #endif 98 99 #if (RTE_MS_PPU_CRYPTO_BOOT) 100 DECLARE_MS_PPU_FX(CRYPTO_BOOT) 101 #endif 102 103 #if (RTE_MS_PPU_CRYPTO_KEY0) 104 DECLARE_MS_PPU_FX(CRYPTO_KEY0) 105 #endif 106 107 #if (RTE_MS_PPU_CRYPTO_KEY1) 108 DECLARE_MS_PPU_FX(CRYPTO_KEY1) 109 #endif 110 111 #if (RTE_MS_PPU_CRYPTO_BUF) 112 DECLARE_MS_PPU_FX(CRYPTO_BUF) 113 #endif 114 115 #if (RTE_MS_PPU_CPUSS_CM4) 116 DECLARE_MS_PPU_FX(CPUSS_CM4) 117 #endif 118 119 #if (RTE_MS_PPU_CPUSS_CM0) 120 DECLARE_MS_PPU_FX(CPUSS_CM0) 121 #endif 122 123 #if (RTE_MS_PPU_CPUSS_CM0_INT) 124 DECLARE_MS_PPU_FX(CPUSS_CM0_INT) 125 #endif 126 127 #if (RTE_MS_PPU_CPUSS_CM4_INT) 128 DECLARE_MS_PPU_FX(CPUSS_CM4_INT) 129 #endif 130 131 #if (RTE_MS_PPU_FAULT_STRUCT0_MAIN) 132 DECLARE_MS_PPU_FX(FAULT_STRUCT0_MAIN) 133 #endif 134 135 #if (RTE_MS_PPU_FAULT_STRUCT1_MAIN) 136 DECLARE_MS_PPU_FX(FAULT_STRUCT1_MAIN) 137 #endif 138 139 #if (RTE_MS_PPU_IPC_STRUCT0_IPC) 140 DECLARE_MS_PPU_FX(IPC_STRUCT0_IPC) 141 #endif 142 143 #if (RTE_MS_PPU_IPC_STRUCT1_IPC) 144 DECLARE_MS_PPU_FX(IPC_STRUCT1_IPC) 145 #endif 146 147 #if (RTE_MS_PPU_IPC_STRUCT2_IPC) 148 DECLARE_MS_PPU_FX(IPC_STRUCT2_IPC) 149 #endif 150 151 #if (RTE_MS_PPU_IPC_STRUCT3_IPC) 152 DECLARE_MS_PPU_FX(IPC_STRUCT3_IPC) 153 #endif 154 155 #if (RTE_MS_PPU_IPC_STRUCT4_IPC) 156 DECLARE_MS_PPU_FX(IPC_STRUCT4_IPC) 157 #endif 158 159 #if (RTE_MS_PPU_IPC_STRUCT5_IPC) 160 DECLARE_MS_PPU_FX(IPC_STRUCT5_IPC) 161 #endif 162 163 #if (RTE_MS_PPU_IPC_STRUCT6_IPC) 164 DECLARE_MS_PPU_FX(IPC_STRUCT6_IPC) 165 #endif 166 167 #if (RTE_MS_PPU_IPC_STRUCT7_IPC) 168 DECLARE_MS_PPU_FX(IPC_STRUCT7_IPC) 169 #endif 170 171 #if (RTE_MS_PPU_IPC_STRUCT8_IPC) 172 DECLARE_MS_PPU_FX(IPC_STRUCT8_IPC) 173 #endif 174 175 #if (RTE_MS_PPU_IPC_STRUCT9_IPC) 176 DECLARE_MS_PPU_FX(IPC_STRUCT9_IPC) 177 #endif 178 179 #if (RTE_MS_PPU_IPC_STRUCT10_IPC) 180 DECLARE_MS_PPU_FX(IPC_STRUCT10_IPC) 181 #endif 182 183 #if (RTE_MS_PPU_IPC_STRUCT11_IPC) 184 DECLARE_MS_PPU_FX(IPC_STRUCT11_IPC) 185 #endif 186 187 #if (RTE_MS_PPU_IPC_STRUCT12_IPC) 188 DECLARE_MS_PPU_FX(IPC_STRUCT12_IPC) 189 #endif 190 191 #if (RTE_MS_PPU_IPC_STRUCT13_IPC) 192 DECLARE_MS_PPU_FX(IPC_STRUCT13_IPC) 193 #endif 194 195 #if (RTE_MS_PPU_IPC_STRUCT14_IPC) 196 DECLARE_MS_PPU_FX(IPC_STRUCT14_IPC) 197 #endif 198 199 #if (RTE_MS_PPU_IPC_STRUCT15_IPC) 200 DECLARE_MS_PPU_FX(IPC_STRUCT15_IPC) 201 #endif 202 203 #if (RTE_MS_PPU_IPC_INTR_STRUCT1_INTR) 204 DECLARE_MS_PPU_FX(IPC_INTR_STRUCT1_INTR) 205 #endif 206 207 #if (RTE_MS_PPU_IPC_INTR_STRUCT2_INTR) 208 DECLARE_MS_PPU_FX(IPC_INTR_STRUCT2_INTR) 209 #endif 210 211 #if (RTE_MS_PPU_IPC_INTR_STRUCT3_INTR) 212 DECLARE_MS_PPU_FX(IPC_INTR_STRUCT3_INTR) 213 #endif 214 215 #if (RTE_MS_PPU_IPC_INTR_STRUCT4_INTR) 216 DECLARE_MS_PPU_FX(IPC_INTR_STRUCT4_INTR) 217 #endif 218 219 #if (RTE_MS_PPU_IPC_INTR_STRUCT5_INTR) 220 DECLARE_MS_PPU_FX(IPC_INTR_STRUCT5_INTR) 221 #endif 222 223 #if (RTE_MS_PPU_IPC_INTR_STRUCT6_INTR) 224 DECLARE_MS_PPU_FX(IPC_INTR_STRUCT6_INTR) 225 #endif 226 227 #if (RTE_MS_PPU_IPC_INTR_STRUCT7_INTR) 228 DECLARE_MS_PPU_FX(IPC_INTR_STRUCT7_INTR) 229 #endif 230 231 #if (RTE_MS_PPU_IPC_INTR_STRUCT8_INTR) 232 DECLARE_MS_PPU_FX(IPC_INTR_STRUCT8_INTR) 233 #endif 234 235 #if (RTE_MS_PPU_IPC_INTR_STRUCT9_INTR) 236 DECLARE_MS_PPU_FX(IPC_INTR_STRUCT9_INTR) 237 #endif 238 239 #if (RTE_MS_PPU_IPC_INTR_STRUCT10_INTR) 240 DECLARE_MS_PPU_FX(IPC_INTR_STRUCT10_INTR) 241 #endif 242 243 #if (RTE_MS_PPU_IPC_INTR_STRUCT11_INTR) 244 DECLARE_MS_PPU_FX(IPC_INTR_STRUCT11_INTR) 245 #endif 246 247 #if (RTE_MS_PPU_IPC_INTR_STRUCT12_INTR) 248 DECLARE_MS_PPU_FX(IPC_INTR_STRUCT12_INTR) 249 #endif 250 251 #if (RTE_MS_PPU_IPC_INTR_STRUCT13_INTR) 252 DECLARE_MS_PPU_FX(IPC_INTR_STRUCT13_INTR) 253 #endif 254 255 #if (RTE_MS_PPU_IPC_INTR_STRUCT14_INTR) 256 DECLARE_MS_PPU_FX(IPC_INTR_STRUCT14_INTR) 257 #endif 258 259 #if (RTE_MS_PPU_IPC_INTR_STRUCT15_INTR) 260 DECLARE_MS_PPU_FX(IPC_INTR_STRUCT15_INTR) 261 #endif 262 263 #if (RTE_MS_PPU_PROT_SMPU_MAIN) 264 DECLARE_MS_PPU_FX(PROT_SMPU_MAIN) 265 #endif 266 267 #if (RTE_MS_PPU_PROT_MPU0_MAIN) 268 DECLARE_MS_PPU_FX(PROT_MPU0_MAIN) 269 #endif 270 271 #if (RTE_MS_PPU_PROT_MPU5_MAIN) 272 DECLARE_MS_PPU_FX(PROT_MPU5_MAIN) 273 #endif 274 275 #if (RTE_MS_PPU_PROT_MPU6_MAIN) 276 DECLARE_MS_PPU_FX(PROT_MPU6_MAIN) 277 #endif 278 279 #if (RTE_MS_PPU_PROT_MPU14_MAIN) 280 DECLARE_MS_PPU_FX(PROT_MPU14_MAIN) 281 #endif 282 283 #if (RTE_MS_PPU_FLASHC_MAIN) 284 DECLARE_MS_PPU_FX(FLASHC_MAIN) 285 #endif 286 287 #if (RTE_MS_PPU_FLASHC_CMD) 288 DECLARE_MS_PPU_FX(FLASHC_CMD) 289 #endif 290 291 #if (RTE_MS_PPU_SRSS_MAIN1) 292 DECLARE_MS_PPU_FX(SRSS_MAIN1) 293 #endif 294 295 #if (RTE_MS_PPU_SRSS_MAIN2) 296 DECLARE_MS_PPU_FX(SRSS_MAIN2) 297 #endif 298 299 #if (RTE_MS_PPU_WDT) 300 DECLARE_MS_PPU_FX(WDT) 301 #endif 302 303 #if (RTE_MS_PPU_MAIN) 304 DECLARE_MS_PPU_FX(MAIN) 305 #endif 306 307 #if (RTE_MS_PPU_SRSS_MAIN3) 308 DECLARE_MS_PPU_FX(SRSS_MAIN3) 309 #endif 310 311 #if (RTE_MS_PPU_SRSS_MAIN4) 312 DECLARE_MS_PPU_FX(SRSS_MAIN4) 313 #endif 314 315 #if (RTE_MS_PPU_SRSS_MAIN5) 316 DECLARE_MS_PPU_FX(SRSS_MAIN5) 317 #endif 318 319 #if (RTE_MS_PPU_SRSS_MAIN6) 320 DECLARE_MS_PPU_FX(SRSS_MAIN6) 321 #endif 322 323 #if (RTE_MS_PPU_SRSS_MAIN7) 324 DECLARE_MS_PPU_FX(SRSS_MAIN7) 325 #endif 326 327 #if (RTE_MS_PPU_BACKUP_BACKUP) 328 DECLARE_MS_PPU_FX(BACKUP_BACKUP) 329 #endif 330 331 #if (RTE_MS_PPU_DW0_DW) 332 DECLARE_MS_PPU_FX(DW0_DW) 333 #endif 334 335 #if (RTE_MS_PPU_DW1_DW) 336 DECLARE_MS_PPU_FX(DW1_DW) 337 #endif 338 339 #if (RTE_MS_PPU_DW0_DW_CRC) 340 DECLARE_MS_PPU_FX(DW0_DW_CRC) 341 #endif 342 343 #if (RTE_MS_PPU_DW1_DW_CRC) 344 DECLARE_MS_PPU_FX(DW1_DW_CRC) 345 #endif 346 347 #if (RTE_MS_PPU_DW0_CH_STRUCT0_CH) 348 DECLARE_MS_PPU_FX(DW0_CH_STRUCT0_CH) 349 #endif 350 351 #if (RTE_MS_PPU_DW0_CH_STRUCT1_CH) 352 DECLARE_MS_PPU_FX(DW0_CH_STRUCT1_CH) 353 #endif 354 355 #if (RTE_MS_PPU_DW0_CH_STRUCT2_CH) 356 DECLARE_MS_PPU_FX(DW0_CH_STRUCT2_CH) 357 #endif 358 359 #if (RTE_MS_PPU_DW0_CH_STRUCT3_CH) 360 DECLARE_MS_PPU_FX(DW0_CH_STRUCT3_CH) 361 #endif 362 363 #if (RTE_MS_PPU_DW0_CH_STRUCT4_CH) 364 DECLARE_MS_PPU_FX(DW0_CH_STRUCT4_CH) 365 #endif 366 367 #if (RTE_MS_PPU_DW0_CH_STRUCT5_CH) 368 DECLARE_MS_PPU_FX(DW0_CH_STRUCT5_CH) 369 #endif 370 371 #if (RTE_MS_PPU_DW0_CH_STRUCT6_CH) 372 DECLARE_MS_PPU_FX(DW0_CH_STRUCT6_CH) 373 #endif 374 375 #if (RTE_MS_PPU_DW0_CH_STRUCT7_CH) 376 DECLARE_MS_PPU_FX(DW0_CH_STRUCT7_CH) 377 #endif 378 379 #if (RTE_MS_PPU_DW0_CH_STRUCT8_CH) 380 DECLARE_MS_PPU_FX(DW0_CH_STRUCT8_CH) 381 #endif 382 383 #if (RTE_MS_PPU_DW0_CH_STRUCT9_CH) 384 DECLARE_MS_PPU_FX(DW0_CH_STRUCT9_CH) 385 #endif 386 387 #if (RTE_MS_PPU_DW0_CH_STRUCT10_CH) 388 DECLARE_MS_PPU_FX(DW0_CH_STRUCT10_CH) 389 #endif 390 391 #if (RTE_MS_PPU_DW0_CH_STRUCT11_CH) 392 DECLARE_MS_PPU_FX(DW0_CH_STRUCT11_CH) 393 #endif 394 395 #if (RTE_MS_PPU_DW0_CH_STRUCT12_CH) 396 DECLARE_MS_PPU_FX(DW0_CH_STRUCT12_CH) 397 #endif 398 399 #if (RTE_MS_PPU_DW0_CH_STRUCT13_CH) 400 DECLARE_MS_PPU_FX(DW0_CH_STRUCT13_CH) 401 #endif 402 403 #if (RTE_MS_PPU_DW0_CH_STRUCT14_CH) 404 DECLARE_MS_PPU_FX(DW0_CH_STRUCT14_CH) 405 #endif 406 407 #if (RTE_MS_PPU_DW0_CH_STRUCT15_CH) 408 DECLARE_MS_PPU_FX(DW0_CH_STRUCT15_CH) 409 #endif 410 411 #if (RTE_MS_PPU_DW0_CH_STRUCT16_CH) 412 DECLARE_MS_PPU_FX(DW0_CH_STRUCT16_CH) 413 #endif 414 415 #if (RTE_MS_PPU_DW0_CH_STRUCT17_CH) 416 DECLARE_MS_PPU_FX(DW0_CH_STRUCT17_CH) 417 #endif 418 419 #if (RTE_MS_PPU_DW0_CH_STRUCT18_CH) 420 DECLARE_MS_PPU_FX(DW0_CH_STRUCT18_CH) 421 #endif 422 423 #if (RTE_MS_PPU_DW0_CH_STRUCT19_CH) 424 DECLARE_MS_PPU_FX(DW0_CH_STRUCT19_CH) 425 #endif 426 427 #if (RTE_MS_PPU_DW0_CH_STRUCT20_CH) 428 DECLARE_MS_PPU_FX(DW0_CH_STRUCT20_CH) 429 #endif 430 431 #if (RTE_MS_PPU_DW0_CH_STRUCT21_CH) 432 DECLARE_MS_PPU_FX(DW0_CH_STRUCT21_CH) 433 #endif 434 435 #if (RTE_MS_PPU_DW0_CH_STRUCT22_CH) 436 DECLARE_MS_PPU_FX(DW0_CH_STRUCT22_CH) 437 #endif 438 439 #if (RTE_MS_PPU_DW0_CH_STRUCT23_CH) 440 DECLARE_MS_PPU_FX(DW0_CH_STRUCT23_CH) 441 #endif 442 443 #if (RTE_MS_PPU_DW0_CH_STRUCT24_CH) 444 DECLARE_MS_PPU_FX(DW0_CH_STRUCT24_CH) 445 #endif 446 447 #if (RTE_MS_PPU_DW0_CH_STRUCT25_CH) 448 DECLARE_MS_PPU_FX(DW0_CH_STRUCT25_CH) 449 #endif 450 451 #if (RTE_MS_PPU_DW0_CH_STRUCT26_CH) 452 DECLARE_MS_PPU_FX(DW0_CH_STRUCT26_CH) 453 #endif 454 455 #if (RTE_MS_PPU_DW0_CH_STRUCT27_CH) 456 DECLARE_MS_PPU_FX(DW0_CH_STRUCT27_CH) 457 #endif 458 459 #if (RTE_MS_PPU_DW0_CH_STRUCT28_CH) 460 DECLARE_MS_PPU_FX(DW0_CH_STRUCT28_CH) 461 #endif 462 463 #if (RTE_MS_PPU_DW1_CH_STRUCT0_CH) 464 DECLARE_MS_PPU_FX(DW1_CH_STRUCT0_CH) 465 #endif 466 467 #if (RTE_MS_PPU_DW1_CH_STRUCT1_CH) 468 DECLARE_MS_PPU_FX(DW1_CH_STRUCT1_CH) 469 #endif 470 471 #if (RTE_MS_PPU_DW1_CH_STRUCT2_CH) 472 DECLARE_MS_PPU_FX(DW1_CH_STRUCT2_CH) 473 #endif 474 475 #if (RTE_MS_PPU_DW1_CH_STRUCT3_CH) 476 DECLARE_MS_PPU_FX(DW1_CH_STRUCT3_CH) 477 #endif 478 479 #if (RTE_MS_PPU_DW1_CH_STRUCT4_CH) 480 DECLARE_MS_PPU_FX(DW1_CH_STRUCT4_CH) 481 #endif 482 483 #if (RTE_MS_PPU_DW1_CH_STRUCT5_CH) 484 DECLARE_MS_PPU_FX(DW1_CH_STRUCT5_CH) 485 #endif 486 487 #if (RTE_MS_PPU_DW1_CH_STRUCT6_CH) 488 DECLARE_MS_PPU_FX(DW1_CH_STRUCT6_CH) 489 #endif 490 491 #if (RTE_MS_PPU_DW1_CH_STRUCT7_CH) 492 DECLARE_MS_PPU_FX(DW1_CH_STRUCT7_CH) 493 #endif 494 495 #if (RTE_MS_PPU_DW1_CH_STRUCT8_CH) 496 DECLARE_MS_PPU_FX(DW1_CH_STRUCT8_CH) 497 #endif 498 499 #if (RTE_MS_PPU_DW1_CH_STRUCT9_CH) 500 DECLARE_MS_PPU_FX(DW1_CH_STRUCT9_CH) 501 #endif 502 503 #if (RTE_MS_PPU_DW1_CH_STRUCT10_CH) 504 DECLARE_MS_PPU_FX(DW1_CH_STRUCT10_CH) 505 #endif 506 507 #if (RTE_MS_PPU_DW1_CH_STRUCT11_CH) 508 DECLARE_MS_PPU_FX(DW1_CH_STRUCT11_CH) 509 #endif 510 511 #if (RTE_MS_PPU_DW1_CH_STRUCT12_CH) 512 DECLARE_MS_PPU_FX(DW1_CH_STRUCT12_CH) 513 #endif 514 515 #if (RTE_MS_PPU_DW1_CH_STRUCT13_CH) 516 DECLARE_MS_PPU_FX(DW1_CH_STRUCT13_CH) 517 #endif 518 519 #if (RTE_MS_PPU_DW1_CH_STRUCT14_CH) 520 DECLARE_MS_PPU_FX(DW1_CH_STRUCT14_CH) 521 #endif 522 523 #if (RTE_MS_PPU_DW1_CH_STRUCT15_CH) 524 DECLARE_MS_PPU_FX(DW1_CH_STRUCT15_CH) 525 #endif 526 527 #if (RTE_MS_PPU_DW1_CH_STRUCT16_CH) 528 DECLARE_MS_PPU_FX(DW1_CH_STRUCT16_CH) 529 #endif 530 531 #if (RTE_MS_PPU_DW1_CH_STRUCT17_CH) 532 DECLARE_MS_PPU_FX(DW1_CH_STRUCT17_CH) 533 #endif 534 535 #if (RTE_MS_PPU_DW1_CH_STRUCT18_CH) 536 DECLARE_MS_PPU_FX(DW1_CH_STRUCT18_CH) 537 #endif 538 539 #if (RTE_MS_PPU_DW1_CH_STRUCT19_CH) 540 DECLARE_MS_PPU_FX(DW1_CH_STRUCT19_CH) 541 #endif 542 543 #if (RTE_MS_PPU_DW1_CH_STRUCT20_CH) 544 DECLARE_MS_PPU_FX(DW1_CH_STRUCT20_CH) 545 #endif 546 547 #if (RTE_MS_PPU_DW1_CH_STRUCT21_CH) 548 DECLARE_MS_PPU_FX(DW1_CH_STRUCT21_CH) 549 #endif 550 551 #if (RTE_MS_PPU_DW1_CH_STRUCT22_CH) 552 DECLARE_MS_PPU_FX(DW1_CH_STRUCT22_CH) 553 #endif 554 555 #if (RTE_MS_PPU_DW1_CH_STRUCT23_CH) 556 DECLARE_MS_PPU_FX(DW1_CH_STRUCT23_CH) 557 #endif 558 559 #if (RTE_MS_PPU_DW1_CH_STRUCT24_CH) 560 DECLARE_MS_PPU_FX(DW1_CH_STRUCT24_CH) 561 #endif 562 563 #if (RTE_MS_PPU_DW1_CH_STRUCT25_CH) 564 DECLARE_MS_PPU_FX(DW1_CH_STRUCT25_CH) 565 #endif 566 567 #if (RTE_MS_PPU_DW1_CH_STRUCT26_CH) 568 DECLARE_MS_PPU_FX(DW1_CH_STRUCT26_CH) 569 #endif 570 571 #if (RTE_MS_PPU_DW1_CH_STRUCT27_CH) 572 DECLARE_MS_PPU_FX(DW1_CH_STRUCT27_CH) 573 #endif 574 575 #if (RTE_MS_PPU_DW1_CH_STRUCT28_CH) 576 DECLARE_MS_PPU_FX(DW1_CH_STRUCT28_CH) 577 #endif 578 579 #if (RTE_MS_PPU_DMAC_TOP) 580 DECLARE_MS_PPU_FX(DMAC_TOP) 581 #endif 582 583 #if (RTE_MS_PPU_DMAC_CH0_CH) 584 DECLARE_MS_PPU_FX(DMAC_CH0_CH) 585 #endif 586 587 #if (RTE_MS_PPU_DMAC_CH1_CH) 588 DECLARE_MS_PPU_FX(DMAC_CH1_CH) 589 #endif 590 591 #if (RTE_MS_PPU_DMAC_CH2_CH) 592 DECLARE_MS_PPU_FX(DMAC_CH2_CH) 593 #endif 594 595 #if (RTE_MS_PPU_DMAC_CH3_CH) 596 DECLARE_MS_PPU_FX(DMAC_CH3_CH) 597 #endif 598 599 #if (RTE_MS_PPU_EFUSE_DATA) 600 DECLARE_MS_PPU_FX(EFUSE_DATA) 601 #endif 602 603 #if (RTE_MS_PPU_PROFILE) 604 DECLARE_MS_PPU_FX(PROFILE) 605 #endif 606 607 #if (RTE_MS_PPU_HSIOM_PRT0_PRT) 608 DECLARE_MS_PPU_FX(HSIOM_PRT0_PRT) 609 #endif 610 611 #if (RTE_MS_PPU_HSIOM_PRT1_PRT) 612 DECLARE_MS_PPU_FX(HSIOM_PRT1_PRT) 613 #endif 614 615 #if (RTE_MS_PPU_HSIOM_PRT2_PRT) 616 DECLARE_MS_PPU_FX(HSIOM_PRT2_PRT) 617 #endif 618 619 #if (RTE_MS_PPU_HSIOM_PRT3_PRT) 620 DECLARE_MS_PPU_FX(HSIOM_PRT3_PRT) 621 #endif 622 623 #if (RTE_MS_PPU_HSIOM_PRT4_PRT) 624 DECLARE_MS_PPU_FX(HSIOM_PRT4_PRT) 625 #endif 626 627 #if (RTE_MS_PPU_HSIOM_PRT5_PRT) 628 DECLARE_MS_PPU_FX(HSIOM_PRT5_PRT) 629 #endif 630 631 #if (RTE_MS_PPU_HSIOM_PRT6_PRT) 632 DECLARE_MS_PPU_FX(HSIOM_PRT6_PRT) 633 #endif 634 635 #if (RTE_MS_PPU_HSIOM_PRT7_PRT) 636 DECLARE_MS_PPU_FX(HSIOM_PRT7_PRT) 637 #endif 638 639 #if (RTE_MS_PPU_HSIOM_PRT8_PRT) 640 DECLARE_MS_PPU_FX(HSIOM_PRT8_PRT) 641 #endif 642 643 #if (RTE_MS_PPU_HSIOM_PRT9_PRT) 644 DECLARE_MS_PPU_FX(HSIOM_PRT9_PRT) 645 #endif 646 647 #if (RTE_MS_PPU_HSIOM_PRT10_PRT) 648 DECLARE_MS_PPU_FX(HSIOM_PRT10_PRT) 649 #endif 650 651 #if (RTE_MS_PPU_HSIOM_PRT11_PRT) 652 DECLARE_MS_PPU_FX(HSIOM_PRT11_PRT) 653 #endif 654 655 #if (RTE_MS_PPU_HSIOM_PRT12_PRT) 656 DECLARE_MS_PPU_FX(HSIOM_PRT12_PRT) 657 #endif 658 659 #if (RTE_MS_PPU_HSIOM_PRT13_PRT) 660 DECLARE_MS_PPU_FX(HSIOM_PRT13_PRT) 661 #endif 662 663 #if (RTE_MS_PPU_HSIOM_PRT14_PRT) 664 DECLARE_MS_PPU_FX(HSIOM_PRT14_PRT) 665 #endif 666 667 #if (RTE_MS_PPU_HSIOM_AMUX) 668 DECLARE_MS_PPU_FX(HSIOM_AMUX) 669 #endif 670 671 #if (RTE_MS_PPU_HSIOM_MON) 672 DECLARE_MS_PPU_FX(HSIOM_MON) 673 #endif 674 675 #if (RTE_MS_PPU_GPIO_PRT0_PRT) 676 DECLARE_MS_PPU_FX(GPIO_PRT0_PRT) 677 #endif 678 679 #if (RTE_MS_PPU_GPIO_PRT1_PRT) 680 DECLARE_MS_PPU_FX(GPIO_PRT1_PRT) 681 #endif 682 683 #if (RTE_MS_PPU_GPIO_PRT2_PRT) 684 DECLARE_MS_PPU_FX(GPIO_PRT2_PRT) 685 #endif 686 687 #if (RTE_MS_PPU_GPIO_PRT3_PRT) 688 DECLARE_MS_PPU_FX(GPIO_PRT3_PRT) 689 #endif 690 691 #if (RTE_MS_PPU_GPIO_PRT4_PRT) 692 DECLARE_MS_PPU_FX(GPIO_PRT4_PRT) 693 #endif 694 695 #if (RTE_MS_PPU_GPIO_PRT5_PRT) 696 DECLARE_MS_PPU_FX(GPIO_PRT5_PRT) 697 #endif 698 699 #if (RTE_MS_PPU_GPIO_PRT6_PRT) 700 DECLARE_MS_PPU_FX(GPIO_PRT6_PRT) 701 #endif 702 703 #if (RTE_MS_PPU_GPIO_PRT7_PRT) 704 DECLARE_MS_PPU_FX(GPIO_PRT7_PRT) 705 #endif 706 707 #if (RTE_MS_PPU_GPIO_PRT8_PRT) 708 DECLARE_MS_PPU_FX(GPIO_PRT8_PRT) 709 #endif 710 711 #if (RTE_MS_PPU_GPIO_PRT9_PRT) 712 DECLARE_MS_PPU_FX(GPIO_PRT9_PRT) 713 #endif 714 715 #if (RTE_MS_PPU_GPIO_PRT10_PRT) 716 DECLARE_MS_PPU_FX(GPIO_PRT10_PRT) 717 #endif 718 719 #if (RTE_MS_PPU_GPIO_PRT11_PRT) 720 DECLARE_MS_PPU_FX(GPIO_PRT11_PRT) 721 #endif 722 723 #if (RTE_MS_PPU_GPIO_PRT12_PRT) 724 DECLARE_MS_PPU_FX(GPIO_PRT12_PRT) 725 #endif 726 727 #if (RTE_MS_PPU_GPIO_PRT13_PRT) 728 DECLARE_MS_PPU_FX(GPIO_PRT13_PRT) 729 #endif 730 731 #if (RTE_MS_PPU_GPIO_PRT14_PRT) 732 DECLARE_MS_PPU_FX(GPIO_PRT14_PRT) 733 #endif 734 735 #if (RTE_MS_PPU_GPIO_PRT0_CFG) 736 DECLARE_MS_PPU_FX(GPIO_PRT0_CFG) 737 #endif 738 739 #if (RTE_MS_PPU_GPIO_PRT1_CFG) 740 DECLARE_MS_PPU_FX(GPIO_PRT1_CFG) 741 #endif 742 743 #if (RTE_MS_PPU_GPIO_PRT2_CFG) 744 DECLARE_MS_PPU_FX(GPIO_PRT2_CFG) 745 #endif 746 747 #if (RTE_MS_PPU_GPIO_PRT3_CFG) 748 DECLARE_MS_PPU_FX(GPIO_PRT3_CFG) 749 #endif 750 751 #if (RTE_MS_PPU_GPIO_PRT4_CFG) 752 DECLARE_MS_PPU_FX(GPIO_PRT4_CFG) 753 #endif 754 755 #if (RTE_MS_PPU_GPIO_PRT5_CFG) 756 DECLARE_MS_PPU_FX(GPIO_PRT5_CFG) 757 #endif 758 759 #if (RTE_MS_PPU_GPIO_PRT6_CFG) 760 DECLARE_MS_PPU_FX(GPIO_PRT6_CFG) 761 #endif 762 763 #if (RTE_MS_PPU_GPIO_PRT7_CFG) 764 DECLARE_MS_PPU_FX(GPIO_PRT7_CFG) 765 #endif 766 767 #if (RTE_MS_PPU_GPIO_PRT8_CFG) 768 DECLARE_MS_PPU_FX(GPIO_PRT8_CFG) 769 #endif 770 771 #if (RTE_MS_PPU_GPIO_PRT9_CFG) 772 DECLARE_MS_PPU_FX(GPIO_PRT9_CFG) 773 #endif 774 775 #if (RTE_MS_PPU_GPIO_PRT10_CFG) 776 DECLARE_MS_PPU_FX(GPIO_PRT10_CFG) 777 #endif 778 779 #if (RTE_MS_PPU_GPIO_PRT11_CFG) 780 DECLARE_MS_PPU_FX(GPIO_PRT11_CFG) 781 #endif 782 783 #if (RTE_MS_PPU_GPIO_PRT12_CFG) 784 DECLARE_MS_PPU_FX(GPIO_PRT12_CFG) 785 #endif 786 787 #if (RTE_MS_PPU_GPIO_PRT13_CFG) 788 DECLARE_MS_PPU_FX(GPIO_PRT13_CFG) 789 #endif 790 791 #if (RTE_MS_PPU_GPIO_PRT14_CFG) 792 DECLARE_MS_PPU_FX(GPIO_PRT14_CFG) 793 #endif 794 795 #if (RTE_MS_PPU_GPIO_GPIO) 796 DECLARE_MS_PPU_FX(GPIO_GPIO) 797 #endif 798 799 #if (RTE_MS_PPU_SMARTIO_PRT8_PRT) 800 DECLARE_MS_PPU_FX(SMARTIO_PRT8_PRT) 801 #endif 802 803 #if (RTE_MS_PPU_SMARTIO_PRT9_PRT) 804 DECLARE_MS_PPU_FX(SMARTIO_PRT9_PRT) 805 #endif 806 807 #if (RTE_MS_PPU_LPCOMP) 808 DECLARE_MS_PPU_FX(LPCOMP) 809 #endif 810 811 #if (RTE_MS_PPU_CSD0) 812 DECLARE_MS_PPU_FX(CSD0) 813 #endif 814 815 #if (RTE_MS_PPU_TCPWM0) 816 DECLARE_MS_PPU_FX(TCPWM0) 817 #endif 818 819 #if (RTE_MS_PPU_TCPWM1) 820 DECLARE_MS_PPU_FX(TCPWM1) 821 #endif 822 823 #if (RTE_MS_PPU_LCD0) 824 DECLARE_MS_PPU_FX(LCD0) 825 #endif 826 827 #if (RTE_MS_PPU_USBFS0) 828 DECLARE_MS_PPU_FX(USBFS0) 829 #endif 830 831 #if (RTE_MS_PPU_SMIF0) 832 DECLARE_MS_PPU_FX(SMIF0) 833 #endif 834 835 #if (RTE_MS_PPU_SDHC0) 836 DECLARE_MS_PPU_FX(SDHC0) 837 #endif 838 839 #if (RTE_MS_PPU_SDHC1) 840 DECLARE_MS_PPU_FX(SDHC1) 841 #endif 842 843 #if (RTE_MS_PPU_SCB0) 844 DECLARE_MS_PPU_FX(SCB0) 845 #endif 846 847 #if (RTE_MS_PPU_SCB1) 848 DECLARE_MS_PPU_FX(SCB1) 849 #endif 850 851 #if (RTE_MS_PPU_SCB2) 852 DECLARE_MS_PPU_FX(SCB2) 853 #endif 854 855 #if (RTE_MS_PPU_SCB3) 856 DECLARE_MS_PPU_FX(SCB3) 857 #endif 858 859 #if (RTE_MS_PPU_SCB4) 860 DECLARE_MS_PPU_FX(SCB4) 861 #endif 862 863 #if (RTE_MS_PPU_SCB5) 864 DECLARE_MS_PPU_FX(SCB5) 865 #endif 866 867 #if (RTE_MS_PPU_SCB6) 868 DECLARE_MS_PPU_FX(SCB6) 869 #endif 870 871 #if (RTE_MS_PPU_SCB7) 872 DECLARE_MS_PPU_FX(SCB7) 873 #endif 874 875 #if (RTE_MS_PPU_SCB8) 876 DECLARE_MS_PPU_FX(SCB8) 877 #endif 878 879 #if (RTE_MS_PPU_SCB9) 880 DECLARE_MS_PPU_FX(SCB9) 881 #endif 882 883 #if (RTE_MS_PPU_SCB10) 884 DECLARE_MS_PPU_FX(SCB10) 885 #endif 886 887 #if (RTE_MS_PPU_SCB11) 888 DECLARE_MS_PPU_FX(SCB11) 889 #endif 890 891 #if (RTE_MS_PPU_SCB12) 892 DECLARE_MS_PPU_FX(SCB12) 893 #endif 894 895 #if (RTE_MS_PPU_PDM0) 896 DECLARE_MS_PPU_FX(PDM0) 897 #endif 898 899 #if (RTE_MS_PPU_I2S0) 900 DECLARE_MS_PPU_FX(I2S0) 901 #endif 902 903 #if (RTE_MS_PPU_I2S1) 904 DECLARE_MS_PPU_FX(I2S1) 905 #endif 906 907 #endif /* __DRIVER_PPU_H__ */ 908
