1 /*
2 * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8 #include "boot_hal.h"
9
10 #include <string.h>
11
12 #ifdef PLATFORM_HAS_BOOT_DMA
13 #include "boot_dma.h"
14 #endif /* PLATFORM_HAS_BOOT_DMA */
15 #include "flash_layout.h"
16 #include "bootutil/bootutil_log.h"
17 #include "bootutil/bootutil.h"
18 #include "device_definition.h"
19 #include "host_base_address.h"
20 #include "platform_base_address.h"
21 #include "platform_regs.h"
22
23 #ifdef CRYPTO_HW_ACCELERATOR
24 #include "crypto_hw.h"
25 #endif /* CRYPTO_HW_ACCELERATOR */
26 #include "fih.h"
27 #include "bl2_image_id.h"
28 #include "Driver_Flash.h"
29 #include "host_flash_atu.h"
30 #include "sic_boot.h"
31 #include "plat_def_fip_uuid.h"
32 #include "flash_map/flash_map.h"
33
34 #ifdef FLASH_DEV_NAME
35 extern ARM_DRIVER_FLASH FLASH_DEV_NAME;
36 #endif /* FLASH_DEV_NAME */
37
38 extern struct boot_rsp rsp;
39 extern struct flash_area flash_map[];
40 extern const int flash_map_entry_num;
41
boot_platform_post_init(void)42 int32_t boot_platform_post_init(void)
43 {
44 enum mhu_v2_x_error_t status;
45 #ifdef PLATFORM_HAS_BOOT_DMA
46 enum tfm_plat_err_t plat_err;
47 #endif /* PLATFORM_HAS_BOOT_DMA */
48
49 #ifdef CRYPTO_HW_ACCELERATOR
50 int32_t result;
51
52 result = crypto_hw_accelerator_init();
53 if (result) {
54 return 1;
55 }
56
57 (void)fih_delay_init();
58 #endif /* CRYPTO_HW_ACCELERATOR */
59
60 status = mhu_v2_x_driver_init(&MHU_SCP_TO_RSE_DEV, MHU_REV_READ_FROM_HW);
61 if (status != MHU_V_2_X_ERR_NONE) {
62 BOOT_LOG_ERR("SCP->RSE MHU driver initialization failed");
63 return 1;
64 }
65 BOOT_LOG_INF("SCP->RSE MHU driver initialized successfully");
66
67 status = mhu_v2_x_driver_init(&MHU_RSE_TO_SCP_DEV, MHU_REV_READ_FROM_HW);
68 if (status != MHU_V_2_X_ERR_NONE) {
69 BOOT_LOG_ERR("RSE->SCP MHU driver initialization failed");
70 return 1;
71 }
72 BOOT_LOG_INF("RSE->SCP MHU driver initialized successfully");
73
74 #ifdef PLATFORM_HAS_BOOT_DMA
75 plat_err = boot_dma_init_cfg();
76 if (plat_err != TFM_PLAT_ERR_SUCCESS) {
77 BOOT_LOG_ERR("DMA driver initialization failed: ", plat_err);
78 return 1;
79 }
80 BOOT_LOG_INF("DMA350 driver initialized successfully.");
81 #endif /* PLATFORM_HAS_BOOT_DMA */
82
83 #ifdef RSE_XIP
84 result = sic_boot_init();
85 if (result) {
86 return result;
87 }
88 #endif /* RSE_XIP */
89
90 return 0;
91 }
92
flash_map_slot_from_flash_area_id(uint32_t area_id)93 static struct flash_area *flash_map_slot_from_flash_area_id(uint32_t area_id)
94 {
95 uint32_t idx;
96 for (idx = 0; idx < flash_map_entry_num; idx++) {
97 if (area_id == flash_map[idx].fa_id) {
98 return &flash_map[idx];
99 }
100 }
101 return NULL;
102 }
103
boot_platform_pre_load(uint32_t image_id)104 int boot_platform_pre_load(uint32_t image_id)
105 {
106 uuid_t uuid;
107 uint32_t offsets[2];
108 struct flash_area *flash_area_primary =
109 flash_map_slot_from_flash_area_id(FLASH_AREA_IMAGE_PRIMARY(image_id));
110 struct flash_area *flash_area_secondary =
111 flash_map_slot_from_flash_area_id(FLASH_AREA_IMAGE_SECONDARY(image_id));
112 int rc;
113
114 kmu_random_delay(&KMU_DEV_S, KMU_DELAY_LIMIT_32_CYCLES);
115
116 if (flash_area_primary == NULL || flash_area_secondary == NULL) {
117 return 1;
118 }
119
120 switch(image_id) {
121 case RSE_BL2_IMAGE_SCP:
122 uuid = UUID_RSE_FIRMWARE_SCP_BL1;
123 break;
124 case RSE_BL2_IMAGE_AP:
125 uuid = UUID_RSE_FIRMWARE_AP_BL1;
126 break;
127 case RSE_BL2_IMAGE_NS:
128 #ifndef RSE_XIP
129 uuid = UUID_RSE_FIRMWARE_NS;
130 #else
131 uuid = UUID_RSE_SIC_TABLES_NS;
132 #endif /* RSE_XIP */
133 break;
134 case RSE_BL2_IMAGE_S:
135 #ifndef RSE_XIP
136 uuid = UUID_RSE_FIRMWARE_S;
137 #else
138 uuid = UUID_RSE_SIC_TABLES_S;
139 #endif /* RSE_XIP */
140 break;
141 default:
142 return 1;
143 }
144
145 rc = host_flash_atu_init_regions_for_image(uuid, offsets);
146 if (rc) {
147 return rc;
148 }
149
150 flash_area_primary->fa_off += offsets[0];
151 flash_area_secondary->fa_off += offsets[1];
152
153 return 0;
154 }
155
boot_platform_post_load(uint32_t image_id)156 int boot_platform_post_load(uint32_t image_id)
157 {
158 int err;
159
160 #ifdef RSE_XIP
161 if (sic_boot_post_load(image_id, rsp.br_image_off) != SIC_BOOT_SUCCESS) {
162 return 1;
163 }
164 #endif /* RSE_XIP */
165
166 if (image_id == RSE_BL2_IMAGE_SCP) {
167 memset((void *)HOST_BOOT_IMAGE1_LOAD_BASE_S, 0, HOST_IMAGE_HEADER_SIZE);
168 uint32_t channel_stat = 0;
169 struct rse_sysctrl_t *sysctrl =
170 (struct rse_sysctrl_t *)RSE_SYSCTRL_BASE_S;
171
172 /* Release SCP CPU from wait */
173 sysctrl->gretreg = 0x1;
174
175 /* Wait for SCP to finish its startup */
176 BOOT_LOG_INF("Waiting for SCP BL1 started event");
177 while (channel_stat == 0) {
178 mhu_v2_x_channel_receive(&MHU_SCP_TO_RSE_DEV, 0, &channel_stat);
179 }
180 BOOT_LOG_INF("Got SCP BL1 started event");
181
182 } else if (image_id == RSE_BL2_IMAGE_AP) {
183 memset((void *)HOST_BOOT_IMAGE0_LOAD_BASE_S, 0, HOST_IMAGE_HEADER_SIZE);
184 BOOT_LOG_INF("Telling SCP to start AP cores");
185 mhu_v2_x_initiate_transfer(&MHU_RSE_TO_SCP_DEV);
186 /* Slot 0 is used in the SCP protocol */
187 mhu_v2_x_channel_send(&MHU_RSE_TO_SCP_DEV, 0, 1);
188 }
189
190 err = host_flash_atu_uninit_regions();
191 if (err) {
192 return err;
193 }
194
195 return 0;
196 }
197
boot_platform_should_load_image(uint32_t image_id)198 bool boot_platform_should_load_image(uint32_t image_id)
199 {
200 #ifndef RSE_LOAD_NS_IMAGE
201 if (image_id == RSE_BL2_IMAGE_NS) {
202 return false;
203 }
204 #endif /* RSE_LOAD_NS_IMAGE */
205
206 return true;
207 }
208
boot_platform_quit(struct boot_arm_vector_table * vt)209 void boot_platform_quit(struct boot_arm_vector_table *vt)
210 {
211 /* Clang at O0, stores variables on the stack with SP relative addressing.
212 * When manually set the SP then the place of reset vector is lost.
213 * Static variables are stored in 'data' or 'bss' section, change of SP has
214 * no effect on them.
215 */
216 static struct boot_arm_vector_table *vt_cpy;
217 int32_t result;
218
219 vt_cpy = vt;
220
221 #ifdef RSE_XIP
222 if (sic_boot_pre_quit(&vt_cpy) != SIC_BOOT_SUCCESS) {
223 FIH_PANIC;
224 }
225 #endif /* RSE_XIP */
226
227 #ifdef CRYPTO_HW_ACCELERATOR
228 result = crypto_hw_accelerator_finish();
229 if (result) {
230 while(1){}
231 }
232 #endif /* CRYPTO_HW_ACCELERATOR */
233
234 #ifdef FLASH_DEV_NAME
235 result = FLASH_DEV_NAME.Uninitialize();
236 if (result != ARM_DRIVER_OK) {
237 while(1){}
238 }
239 #endif /* FLASH_DEV_NAME */
240 #ifdef FLASH_DEV_NAME_2
241 result = FLASH_DEV_NAME_2.Uninitialize();
242 if (result != ARM_DRIVER_OK) {
243 while(1){}
244 }
245 #endif /* FLASH_DEV_NAME_2 */
246 #ifdef FLASH_DEV_NAME_3
247 result = FLASH_DEV_NAME_3.Uninitialize();
248 if (result != ARM_DRIVER_OK) {
249 while(1){}
250 }
251 #endif /* FLASH_DEV_NAME_3 */
252 #ifdef FLASH_DEV_NAME_SCRATCH
253 result = FLASH_DEV_NAME_SCRATCH.Uninitialize();
254 if (result != ARM_DRIVER_OK) {
255 while(1){}
256 }
257 #endif /* FLASH_DEV_NAME_SCRATCH */
258
259 kmu_random_delay(&KMU_DEV_S, KMU_DELAY_LIMIT_32_CYCLES);
260
261 #if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__) \
262 || defined(__ARM_ARCH_8_1M_MAIN__)
263 /* Restore the Main Stack Pointer Limit register's reset value
264 * before passing execution to runtime firmware to make the
265 * bootloader transparent to it.
266 */
267 __set_MSPLIM(0);
268 #endif /* defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__) \
269 || defined(__ARM_ARCH_8_1M_MAIN__) */
270
271 __set_MSP(vt_cpy->msp);
272 __DSB();
273 __ISB();
274
275 boot_jump_to_next_image(vt_cpy->reset);
276 }
277
