1 /*
2 * Copyright (c) 2024, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7 #include "bootutil/bootutil_log.h"
8 #include "host_device_definition.h"
9 #include "host_base_address.h"
10 #include "ni_tower_lib.h"
11
12 #include <stddef.h>
13
14 /* Chip ID enumerations */
15 enum rse_supported_chip_ids {
16 RSE_CHIP_ID_0 = 0,
17 RSE_CHIP_ID_1,
18 RSE_CHIP_ID_2,
19 RSE_CHIP_ID_3,
20 RSE_MAX_SUPPORTED_CHIPS,
21 };
22
23 #define MHU_SEND_FRAME_SIZE (RSE_MAX_SUPPORTED_CHIPS - 1)
24
25 /* System Control NI-Tower component nodes */
26 const struct ni_tower_component_node sysctrl_rse_main_asni = {
27 .type = NI_TOWER_ASNI,
28 .id = SYSCTRL_RSE_MAIN_ASNI_ID,
29 };
30
31 const struct ni_tower_component_node sysctrl_scp_asni = {
32 .type = NI_TOWER_ASNI,
33 .id = SYSCTRL_SCP_ASNI_ID,
34 };
35
36 const struct ni_tower_component_node sysctrl_mcp_asni = {
37 .type = NI_TOWER_ASNI,
38 .id = SYSCTRL_MCP_ASNI_ID,
39 };
40
41 const struct ni_tower_component_node sysctrl_rse_scp_asni = {
42 .type = NI_TOWER_ASNI,
43 .id = SYSCTRL_RSE_SCP_ASNI_ID,
44 };
45
46 const struct ni_tower_component_node sysctrl_app_asni = {
47 .type = NI_TOWER_ASNI,
48 .id = SYSCTRL_APP_ASNI_ID,
49 };
50
51 const struct ni_tower_component_node sysctrl_lcp_asni = {
52 .type = NI_TOWER_ASNI,
53 .id = SYSCTRL_LCP_ASNI_ID,
54 };
55
56 const struct ni_tower_component_node sysctrl_rsm_amni = {
57 .type = NI_TOWER_AMNI,
58 .id = SYSCTRL_RSM_AMNI_ID,
59 };
60
61 const struct ni_tower_component_node sysctrl_rsm_pmni = {
62 .type = NI_TOWER_PMNI,
63 .id = SYSCTRL_RSM_PMNI_ID,
64 };
65
66 const struct ni_tower_component_node sysctrl_rse_scp_amni = {
67 .type = NI_TOWER_AMNI,
68 .id = SYSCTRL_RSE_SCP_AMNI_ID,
69 };
70
71 const struct ni_tower_component_node sysctrl_rse_mcp_amni = {
72 .type = NI_TOWER_AMNI,
73 .id = SYSCTRL_RSE_MCP_AMNI_ID,
74 };
75
76 const struct ni_tower_component_node sysctrl_app_amni = {
77 .type = NI_TOWER_AMNI,
78 .id = SYSCTRL_APP_AMNI_ID,
79 };
80
81 const struct ni_tower_component_node sysctrl_lcp_amni = {
82 .type = NI_TOWER_AMNI,
83 .id = SYSCTRL_LCP_AMNI_ID,
84 };
85
86 /*
87 * System Control NI-Tower is the interconnect between the AXI interfaces of
88 * RSE, SCP/MCP and the CMN interconnect. Following block diagram depicts an
89 * abstract overview of the routing map for these interfaces.
90 *
91 * +-----+
92 * | |
93 * | |---------------------------> tcu_apbm
94 * | |
95 * | |
96 * | | +-----+
97 * | |-----------------| APU |---> rse_scp_axim
98 * | | +-----+
99 * | |
100 * rse_main_axis ------------->| | +-----+
101 * | |-----------------| APU |---> rse_mcp_axim
102 * | | +-----+
103 * | |
104 * | | +-----+
105 * | |------>| |
106 * | | | |-------------> cmn_apbm
107 * +-----+ | |
108 * | | +-----+
109 * | |---| APU |---> rsm_axim
110 * scp_axis --------------------------->| | +-----+
111 * | |
112 * | | +-----+
113 * | |---| APU |---> rsm_apbm
114 * +-----+ | | +-----+
115 * | | | |
116 * | |------>| | +-----+
117 * | | | |---| APU |---> app_axim
118 * | | | | +-----+
119 * +-----+ | | +-----+
120 * mcp_axis ---| APU |--->| |
121 * +-----+ | |
122 * | | +-----+
123 * | | | |
124 * | |------>| |
125 * | | | |
126 * +-----+ | |
127 * | |
128 * | |-------------> app_scp_axim
129 * +-----+ | |
130 * | | | |
131 * | |------>| |
132 * | | | |
133 * | | | |
134 * +-----+ | | +-----+
135 * app_axis ---| APU |--->| |
136 * +-----+ | |
137 * | |
138 * | |
139 * | |---------------------------> app_mcp_axim
140 * | |
141 * +-----+
142 *
143 * +-----+
144 * | |
145 * +-----+ | |
146 * lcp_axis ---| APU |--->| |---------------------------> lcp_scp_axim
147 * +-----+ | |
148 * | |
149 * +-----+
150 *
151 * +-----+
152 * | |
153 * | | +-----+
154 * rse_scp_axis ------------->| |----------| APU |---------> lcp_axim
155 * | | +-----+
156 * | |
157 * +-----+
158 *
159 * The following matrix shows the connections within System Control NI-Tower.
160 *
161 * +------------+---------------+----------+----------+--------------+----------+----------+
162 * | | rse_main_axis | scp_axis | mcp_axis | rse_scp_axis | app_axis | lcp_axis |
163 * +============+===============+==========+==========+==============+==========+==========+
164 * |rse_scp_axim| X | | | | | |
165 * +------------+---------------+----------+----------+--------------+----------+----------+
166 * |rse_mcp_axim| X | | | | | |
167 * +------------+---------------+----------+----------+--------------+----------+----------+
168 * | rsm_axim | X | X | X | | | |
169 * +------------+---------------+----------+----------+--------------+----------+----------+
170 * | rsm_apbm | X | X | X | | | |
171 * +------------+---------------+----------+----------+--------------+----------+----------+
172 * | cmn_apbm | X | X | X | | | |
173 * +------------+---------------+----------+----------+--------------+----------+----------+
174 * | tcu_apbm | X | | | | | |
175 * +------------+---------------+----------+----------+--------------+----------+----------+
176 * | lcp_axim | | | | X | | |
177 * +------------+---------------+----------+----------+--------------+----------+----------+
178 * | app_axim | X | X | X | | | |
179 * +------------+---------------+----------+----------+--------------+----------+----------+
180 * |app_scp_axim| | | X | | X | |
181 * +------------+---------------+----------+----------+--------------+----------+----------+
182 * |app_mcp_axim| | | | | X | |
183 * +------------+---------------+----------+----------+--------------+----------+----------+
184 * |lcp_scp_axim| | | | | | X |
185 * +------------+---------------+----------+----------+--------------+----------+----------+
186 * NOTE: 'X' means there is a connection.
187 */
188
189 /*
190 * Request originating from RSE ATU is mapped to targets based on following
191 * address map.
192 */
193 static const struct ni_tower_psam_reg_cfg_info rse_main_axis_0_psam[] = {
194 /* Shared SRAM + AP Memory Expansion 1 */
195 {
196 HOST_AP_SHARED_SRAM_PHYS_BASE,
197 HOST_AP_MEM_EXP_1_PHYS_LIMIT,
198 SYSCTRL_APP_AMNI_ID
199 },
200 /* System Control Block NI-Tower */
201 {
202 HOST_SYSCTRL_NI_TOWER_PHYS_BASE,
203 HOST_SYSCTRL_NI_TOWER_PHYS_LIMIT,
204 SYSCTRL_CONFIG_SPACE_ID
205 },
206 /*
207 * IO Block NI-Tower + Peripheral Block NI-Tower + System Fabric
208 * NI-Tower + Debug Block NCI GPV + UART Peripherals + Generic refclk +
209 * AP Watchdog peripherals + SID + ECC error record registers
210 */
211 {
212 HOST_IO_MACRO_NI_TOWER_PHYS_BASE,
213 HOST_RSE_RL_ARSM_RAM_ECC_REC_PHYS_LIMIT,
214 SYSCTRL_APP_AMNI_ID
215 },
216 /* ECC error record for RSM block */
217 {
218 HOST_RSE_S_RSM_RAM_ECC_REC_PHYS_BASE,
219 HOST_RSE_NS_RSM_RAM_ECC_REC_PHYS_LIMIT,
220 SYSCTRL_RSM_PMNI_ID
221 },
222 /*
223 * Generic refclk registers + AP<->SCP MHUv3 registers +
224 * AP<->MCP MHUv3 registers + AP<->RSE MHUv3 registers +
225 * SCP<->SCP MHU registers + MCP<->MCP MHU registers
226 */
227 {
228 HOST_GENERIC_REFCLK_CNTREAD_PHYS_BASE,
229 HOST_MCP_TO_MCP_MHU_PHYS_LIMIT,
230 SYSCTRL_APP_AMNI_ID
231 },
232 /* RSE<->RSE Cross-chip MHU registers */
233 {
234 HOST_RSE_TO_RSE_MHU_PHYS_BASE,
235 HOST_RSE_TO_RSE_MHU_PHYS_LIMIT,
236 SYSCTRL_APP_AMNI_ID
237 },
238 /* Timer synchronization registers */
239 {
240 HOST_SYNCNT_MSTUPDTVAL_ADDR_PHYS_BASE,
241 HOST_SYNCNT_MSTUPDTVAL_ADDR_PHYS_LIMIT,
242 SYSCTRL_APP_AMNI_ID
243 },
244 /* Shared RSM SRAM */
245 {
246 HOST_RSM_SRAM_PHYS_BASE,
247 HOST_RSM_SRAM_PHYS_LIMIT,
248 SYSCTRL_RSM_AMNI_ID
249 },
250 /* GIC-700 */
251 {
252 HOST_GIC_700_PHYS_BASE,
253 HOST_GIC_700_PHYS_LIMIT,
254 SYSCTRL_APP_AMNI_ID
255 },
256 /* PCIe NCI Memory Space 1 + DRAM */
257 {
258 HOST_PCIE_NCI_1_PHYS_BASE,
259 HOST_DRAM_PHYS_LIMIT,
260 SYSCTRL_APP_AMNI_ID
261 },
262 /* CMN GPV */
263 {
264 HOST_CMN_GPV_PHYS_BASE,
265 HOST_CMN_GPV_PHYS_LIMIT,
266 SYSCTRL_CMN_PMNI_ID
267 },
268 /* Memory Controller + MPE register space */
269 {
270 HOST_MPE_PHYS_BASE,
271 HOST_MPE_PHYS_LIMIT,
272 SYSCTRL_APP_AMNI_ID
273 },
274 /* LCP peripherals + Cluster Utility memory region */
275 {
276 HOST_CLUST_UTIL_PHYS_BASE,
277 HOST_CLUST_UTIL_PHYS_LIMIT,
278 SYSCTRL_APP_AMNI_ID
279 },
280 /* IO Block SMMU + NCI GPV + PCIe CTRL + PHY */
281 {
282 HOST_IO_BLOCK_PHYS_BASE,
283 HOST_IO_BLOCK_PHYS_LIMIT,
284 SYSCTRL_APP_AMNI_ID
285 },
286 /* SYSCTRL SMMU */
287 {
288 HOST_SYSCTRL_SMMU_PHYS_BASE,
289 HOST_SYSCTRL_SMMU_PHYS_LIMIT,
290 SYSCTRL_TCU_PMNI_ID
291 },
292 /* Debug Memory Map + AP Memory Expansion 2 */
293 {
294 HOST_DEBUG_MMAP_PHYS_BASE,
295 HOST_AP_MEM_EXP_2_PHYS_LIMIT,
296 SYSCTRL_APP_AMNI_ID
297 },
298 };
299
300 /*
301 * Request coming from RSE ATU is mapped to targets based on following
302 * address map.
303 */
304 static const struct ni_tower_psam_reg_cfg_info rse_main_axis_1_psam[] = {
305 /*
306 * PCIe NCI Memory space 2 + PCIe NCI Memory space 3 + DRAM +
307 * AP Memory Expansion 3
308 */
309 {
310 HOST_PCIE_NCI_2_PHYS_BASE,
311 HOST_AP_MEM_EXP_3_PHYS_LIMIT,
312 SYSCTRL_APP_AMNI_ID
313 },
314 /* SCP Access region */
315 {
316 HOST_SCP_PHYS_BASE,
317 HOST_SCP_PHYS_LIMIT,
318 SYSCTRL_RSE_SCP_AMNI_ID
319 },
320 /* MCP Access region */
321 {
322 HOST_MCP_PHYS_BASE,
323 HOST_MCP_PHYS_LIMIT,
324 SYSCTRL_RSE_MCP_AMNI_ID
325 }
326 };
327
328 /*
329 * Multi-chip environment contains set of MHUs for RSE-RSE cross chip
330 * communications. Request coming from RSE ATU is mapped to targets based on
331 * following address map for RSE chip-to-chip MHU send frame between the
332 * current chip and other 3 chips.
333 */
334 static const struct ni_tower_psam_reg_cfg_info
335 rse_main_axis_psam_mhu_send_frame[][MHU_SEND_FRAME_SIZE] =
336 {
337 [RSE_CHIP_ID_0] = {
338 /* RSE Cross chip 0 to chip 1 MHU send frame */
339 {
340 HOST_RSE_N_TO_RSE_N_MHU_PHYS_BASE(0,1),
341 HOST_RSE_N_TO_RSE_N_MHU_PHYS_LIMIT(0,1),
342 SYSCTRL_APP_AMNI_ID
343 },
344 /* RSE Cross chip 0 to chip 2 MHU send frame */
345 {
346 HOST_RSE_N_TO_RSE_N_MHU_PHYS_BASE(0,2),
347 HOST_RSE_N_TO_RSE_N_MHU_PHYS_LIMIT(0,2),
348 SYSCTRL_APP_AMNI_ID
349 },
350 /* RSE Cross chip 0 to chip 3 MHU send frame */
351 {
352 HOST_RSE_N_TO_RSE_N_MHU_PHYS_BASE(0,3),
353 HOST_RSE_N_TO_RSE_N_MHU_PHYS_LIMIT(0,3),
354 SYSCTRL_APP_AMNI_ID
355 },
356 },
357 [RSE_CHIP_ID_1] = {
358 /* RSE Cross chip 1 to chip 0 MHU send frame */
359 {
360 HOST_RSE_N_TO_RSE_N_MHU_PHYS_BASE(1,0),
361 HOST_RSE_N_TO_RSE_N_MHU_PHYS_LIMIT(1,0),
362 SYSCTRL_APP_AMNI_ID
363 },
364 /* RSE Cross chip 1 to chip 2 MHU send frame */
365 {
366 HOST_RSE_N_TO_RSE_N_MHU_PHYS_BASE(1,2),
367 HOST_RSE_N_TO_RSE_N_MHU_PHYS_LIMIT(1,2),
368 SYSCTRL_APP_AMNI_ID
369 },
370 /* RSE Cross chip 1 to chip 3 MHU send frame */
371 {
372 HOST_RSE_N_TO_RSE_N_MHU_PHYS_BASE(1,3),
373 HOST_RSE_N_TO_RSE_N_MHU_PHYS_LIMIT(1,3),
374 SYSCTRL_APP_AMNI_ID
375 },
376 },
377 [RSE_CHIP_ID_2] = {
378 /* RSE Cross chip 2 to chip 0 MHU send frame */
379 {
380 HOST_RSE_N_TO_RSE_N_MHU_PHYS_BASE(2,0),
381 HOST_RSE_N_TO_RSE_N_MHU_PHYS_LIMIT(2,0),
382 SYSCTRL_APP_AMNI_ID
383 },
384 /* RSE Cross chip 2 to chip 1 MHU send frame */
385 {
386 HOST_RSE_N_TO_RSE_N_MHU_PHYS_BASE(2,1),
387 HOST_RSE_N_TO_RSE_N_MHU_PHYS_LIMIT(2,1),
388 SYSCTRL_APP_AMNI_ID
389 },
390 /* RSE Cross chip 2 to chip 3 MHU send frame */
391 {
392 HOST_RSE_N_TO_RSE_N_MHU_PHYS_BASE(2,3),
393 HOST_RSE_N_TO_RSE_N_MHU_PHYS_LIMIT(2,3),
394 SYSCTRL_APP_AMNI_ID
395 },
396 },
397 [RSE_CHIP_ID_3] = {
398 /* RSE Cross chip 3 to chip 0 MHU send frame */
399 {
400 HOST_RSE_N_TO_RSE_N_MHU_PHYS_BASE(3,0),
401 HOST_RSE_N_TO_RSE_N_MHU_PHYS_LIMIT(3,0),
402 SYSCTRL_APP_AMNI_ID
403 },
404 /* RSE Cross chip 3 to chip 1 MHU send frame */
405 {
406 HOST_RSE_N_TO_RSE_N_MHU_PHYS_BASE(3,1),
407 HOST_RSE_N_TO_RSE_N_MHU_PHYS_LIMIT(3,1),
408 SYSCTRL_APP_AMNI_ID
409 },
410 /* RSE Cross chip 3 to chip 2 MHU send frame */
411 {
412 HOST_RSE_N_TO_RSE_N_MHU_PHYS_BASE(3,2),
413 HOST_RSE_N_TO_RSE_N_MHU_PHYS_LIMIT(3,2),
414 SYSCTRL_APP_AMNI_ID
415 },
416 },
417 };
418
419 /*
420 * Request originating from SCP ATU is mapped to targets based on following
421 * address map.
422 */
423 static const struct ni_tower_psam_reg_cfg_info scp_axis_0_psam[] = {
424 /* Shared SRAM + AP Memory Expansion 1 */
425 {
426 HOST_AP_SHARED_SRAM_PHYS_BASE,
427 HOST_AP_MEM_EXP_1_PHYS_LIMIT,
428 SYSCTRL_APP_AMNI_ID
429 },
430 /* Generic refclk registers */
431 {
432 HOST_GENERIC_REFCLK_CNTCONTROL_PHYS_BASE,
433 HOST_GENERIC_REFCLK_CNTCONTROL_PHYS_LIMIT,
434 SYSCTRL_APP_AMNI_ID
435 },
436 /* SCP ECC error record */
437 {
438 HOST_SCP_S_ARSM_RAM_ECC_REC_PHYS_BASE,
439 HOST_SCP_RL_ARSM_RAM_ECC_REC_PHYS_LIMIT,
440 SYSCTRL_APP_AMNI_ID
441 },
442 /* SCP/MCP RSM ECC error record */
443 {
444 HOST_SCP_S_RSM_RAM_ECC_REC_PHYS_BASE,
445 HOST_MCP_NS_RSM_RAM_ECC_REC_PHYS_LIMIT,
446 SYSCTRL_RSM_PMNI_ID
447 },
448 /* Refclk registers */
449 {
450 HOST_GENERIC_REFCLK_CNTREAD_PHYS_BASE,
451 HOST_AP_NS_REFCLK_CNTBASE1_PHYS_LIMIT,
452 SYSCTRL_APP_AMNI_ID
453 },
454 /* AP<->SCP MHUv3 registers */
455 {
456 HOST_AP_NS_SCP_MHUV3_PHYS_BASE,
457 HOST_AP_RT_SCP_MHUV3_PHYS_LIMIT,
458 SYSCTRL_APP_AMNI_ID
459 },
460 /* Shared RSM SRAM */
461 {
462 HOST_RSM_SRAM_PHYS_BASE,
463 HOST_RSM_SRAM_PHYS_LIMIT,
464 SYSCTRL_RSM_AMNI_ID
465 },
466 /* CMN GPV */
467 {
468 HOST_CMN_GPV_PHYS_BASE,
469 HOST_CMN_GPV_PHYS_LIMIT,
470 SYSCTRL_CMN_PMNI_ID
471 },
472 /* Memory Controller + MPE register space */
473 {
474 HOST_MPE_PHYS_BASE,
475 HOST_MPE_PHYS_LIMIT,
476 SYSCTRL_APP_AMNI_ID
477 },
478 /* LCP peripherals + Cluster Utility memory region */
479 {
480 HOST_CLUST_UTIL_PHYS_BASE,
481 HOST_CLUST_UTIL_PHYS_LIMIT,
482 SYSCTRL_APP_AMNI_ID
483 },
484 /* SMMU + NCI GPV + PCIe CTRL + PHY */
485 {
486 HOST_IO_BLOCK_PHYS_BASE,
487 HOST_IO_BLOCK_PHYS_LIMIT,
488 SYSCTRL_APP_AMNI_ID
489 },
490 /* AP Memory Expansion 2 */
491 {
492 HOST_AP_MEM_EXP_2_PHYS_BASE,
493 HOST_AP_MEM_EXP_2_PHYS_LIMIT,
494 SYSCTRL_APP_AMNI_ID
495 },
496 };
497
498 /*
499 * Request coming from SCP ATU is mapped to targets based on following
500 * address map.
501 */
502 static const struct ni_tower_psam_reg_cfg_info scp_axis_1_psam[] = {
503 /*
504 * PCIe NCI Memory space 2 + PCIe NCI Memory space 3 + DRAM +
505 * AP Memory Expansion 3
506 */
507 {
508 HOST_PCIE_NCI_2_PHYS_BASE,
509 HOST_PCIE_NCI_3_PHYS_LIMIT,
510 SYSCTRL_APP_AMNI_ID
511 },
512 };
513
514 /*
515 * Multi-chip environment contains set of MHUs for SCP-SCP cross chip
516 * communications. Request coming from SCP ATU is mapped to targets based on
517 * following address map for SCP chip-to-chip MHU send frame between the
518 * current chip and other 3 chips.
519 */
520 static const struct ni_tower_psam_reg_cfg_info
521 scp_axis_psam_mhu_send_frame[][MHU_SEND_FRAME_SIZE] =
522 {
523 [RSE_CHIP_ID_0] = {
524 /* SCP Cross chip 0 to chip 1 MHU send frame */
525 {
526 HOST_SCP_N_TO_SCP_N_MHU_PHYS_BASE(0,1),
527 HOST_SCP_N_TO_SCP_N_MHU_PHYS_LIMIT(0,1),
528 SYSCTRL_APP_AMNI_ID
529 },
530 /* SCP Cross chip 0 to chip 2 MHU send frame */
531 {
532 HOST_SCP_N_TO_SCP_N_MHU_PHYS_BASE(0,2),
533 HOST_SCP_N_TO_SCP_N_MHU_PHYS_LIMIT(0,2),
534 SYSCTRL_APP_AMNI_ID
535 },
536 /* SCP Cross chip 0 to chip 3 MHU send frame */
537 {
538 HOST_SCP_N_TO_SCP_N_MHU_PHYS_BASE(0,3),
539 HOST_SCP_N_TO_SCP_N_MHU_PHYS_LIMIT(0,3),
540 SYSCTRL_APP_AMNI_ID
541 },
542 },
543 [RSE_CHIP_ID_1] = {
544 /* SCP Cross chip 1 to chip 0 MHU send frame */
545 {
546 HOST_SCP_N_TO_SCP_N_MHU_PHYS_BASE(1,0),
547 HOST_SCP_N_TO_SCP_N_MHU_PHYS_LIMIT(1,0),
548 SYSCTRL_APP_AMNI_ID
549 },
550 /* SCP Cross chip 1 to chip 2 MHU send frame */
551 {
552 HOST_SCP_N_TO_SCP_N_MHU_PHYS_BASE(1,2),
553 HOST_SCP_N_TO_SCP_N_MHU_PHYS_LIMIT(1,2),
554 SYSCTRL_APP_AMNI_ID
555 },
556 /* SCP Cross chip 1 to chip 3 MHU send frame */
557 {
558 HOST_SCP_N_TO_SCP_N_MHU_PHYS_BASE(1,3),
559 HOST_SCP_N_TO_SCP_N_MHU_PHYS_LIMIT(1,3),
560 SYSCTRL_APP_AMNI_ID
561 },
562 },
563 [RSE_CHIP_ID_2] = {
564 /* SCP Cross chip 2 to chip 0 MHU send frame */
565 {
566 HOST_SCP_N_TO_SCP_N_MHU_PHYS_BASE(2,0),
567 HOST_SCP_N_TO_SCP_N_MHU_PHYS_LIMIT(2,0),
568 SYSCTRL_APP_AMNI_ID
569 },
570 /* SCP Cross chip 2 to chip 1 MHU send frame */
571 {
572 HOST_SCP_N_TO_SCP_N_MHU_PHYS_BASE(2,1),
573 HOST_SCP_N_TO_SCP_N_MHU_PHYS_LIMIT(2,1),
574 SYSCTRL_APP_AMNI_ID
575 },
576 /* SCP Cross chip 2 to chip 3 MHU send frame */
577 {
578 HOST_SCP_N_TO_SCP_N_MHU_PHYS_BASE(2,3),
579 HOST_SCP_N_TO_SCP_N_MHU_PHYS_LIMIT(2,3),
580 SYSCTRL_APP_AMNI_ID
581 },
582 },
583 [RSE_CHIP_ID_3] = {
584 /* SCP Cross chip 3 to chip 0 MHU send frame */
585 {
586 HOST_SCP_N_TO_SCP_N_MHU_PHYS_BASE(3,0),
587 HOST_SCP_N_TO_SCP_N_MHU_PHYS_LIMIT(3,0),
588 SYSCTRL_APP_AMNI_ID
589 },
590 /* SCP Cross chip 3 to chip 1 MHU send frame */
591 {
592 HOST_SCP_N_TO_SCP_N_MHU_PHYS_BASE(3,1),
593 HOST_SCP_N_TO_SCP_N_MHU_PHYS_LIMIT(3,1),
594 SYSCTRL_APP_AMNI_ID
595 },
596 /* SCP Cross chip 3 to chip 2 MHU send frame */
597 {
598 HOST_SCP_N_TO_SCP_N_MHU_PHYS_BASE(3,2),
599 HOST_SCP_N_TO_SCP_N_MHU_PHYS_LIMIT(3,2),
600 SYSCTRL_APP_AMNI_ID
601 },
602 },
603 };
604
605 /*
606 * Request originating from MCP ATU is mapped to targets based on following
607 * address map.
608 */
609 static const struct ni_tower_psam_reg_cfg_info mcp_axis_psam[] = {
610 /* Shared SRAM */
611 {
612 HOST_AP_SHARED_SRAM_PHYS_BASE,
613 HOST_AP_SHARED_SRAM_PHYS_LIMIT,
614 SYSCTRL_APP_AMNI_ID
615 },
616 /* Generic refclk registers */
617 {
618 HOST_GENERIC_REFCLK_CNTCONTROL_PHYS_BASE,
619 HOST_GENERIC_REFCLK_CNTCONTROL_PHYS_LIMIT,
620 SYSCTRL_APP_SCP_AMNI_ID
621 },
622 /* AP ECC error record */
623 {
624 HOST_AP_S_ARSM_RAM_ECC_REC_PHYS_BASE,
625 HOST_RSE_RL_ARSM_RAM_ECC_REC_PHYS_LIMIT,
626 SYSCTRL_APP_AMNI_ID
627 },
628 /* SCP/MCP RSM ECC error record */
629 {
630 HOST_SCP_S_RSM_RAM_ECC_REC_PHYS_BASE,
631 HOST_MCP_NS_RSM_RAM_ECC_REC_PHYS_LIMIT,
632 SYSCTRL_RSM_PMNI_ID
633 },
634 /* AP<->MCP MHUv3 registers + AP<->RSE MHUv3 registers */
635 {
636 HOST_AP_NS_MCP_MHUV3_SEND_BASE,
637 HOST_AP_RL_RSE_MHUV3_PHYS_LIMIT,
638 SYSCTRL_APP_AMNI_ID
639 },
640 /* MCP<->MCP MHU registers */
641 {
642 HOST_MCP_TO_MCP_MHU_PHYS_BASE,
643 HOST_MCP_TO_MCP_MHU_PHYS_LIMIT,
644 SYSCTRL_APP_AMNI_ID
645 },
646 /* Shared RSM SRAM */
647 {
648 HOST_RSM_SRAM_PHYS_BASE,
649 HOST_RSM_SRAM_PHYS_LIMIT,
650 SYSCTRL_RSM_AMNI_ID
651 },
652 };
653
654 /*
655 * Multi-chip environment contains set of MHUs for MCP-MCP cross chip
656 * communications. Request coming from MCP ATU is mapped to targets based on
657 * following address map for MCP chip-to-chip MHU send frame between the
658 * current chip and other 3 chips.
659 */
660 static const struct ni_tower_psam_reg_cfg_info
661 mcp_axis_psam_mhu_send_frame[][MHU_SEND_FRAME_SIZE] =
662 {
663 [RSE_CHIP_ID_0] = {
664 /* MCP Cross chip 0 to chip 1 MHU send frame */
665 {
666 HOST_MCP_N_TO_MCP_N_MHU_PHYS_BASE(0,1),
667 HOST_MCP_N_TO_MCP_N_MHU_PHYS_LIMIT(0,1),
668 SYSCTRL_APP_AMNI_ID
669 },
670 /* MCP Cross chip 0 to chip 2 MHU send frame */
671 {
672 HOST_MCP_N_TO_MCP_N_MHU_PHYS_BASE(0,2),
673 HOST_MCP_N_TO_MCP_N_MHU_PHYS_LIMIT(0,2),
674 SYSCTRL_APP_AMNI_ID
675 },
676 /* MCP Cross chip 0 to chip 3 MHU send frame */
677 {
678 HOST_MCP_N_TO_MCP_N_MHU_PHYS_BASE(0,3),
679 HOST_MCP_N_TO_MCP_N_MHU_PHYS_LIMIT(0,3),
680 SYSCTRL_APP_AMNI_ID
681 },
682 },
683 [RSE_CHIP_ID_1] = {
684 /* MCP Cross chip 1 to chip 0 MHU send frame */
685 {
686 HOST_MCP_N_TO_MCP_N_MHU_PHYS_BASE(1,0),
687 HOST_MCP_N_TO_MCP_N_MHU_PHYS_LIMIT(1,0),
688 SYSCTRL_APP_AMNI_ID
689 },
690 /* MCP Cross chip 1 to chip 2 MHU send frame */
691 {
692 HOST_MCP_N_TO_MCP_N_MHU_PHYS_BASE(1,2),
693 HOST_MCP_N_TO_MCP_N_MHU_PHYS_LIMIT(1,2),
694 SYSCTRL_APP_AMNI_ID
695 },
696 /* MCP Cross chip 1 to chip 3 MHU send frame */
697 {
698 HOST_MCP_N_TO_MCP_N_MHU_PHYS_BASE(1,3),
699 HOST_MCP_N_TO_MCP_N_MHU_PHYS_LIMIT(1,3),
700 SYSCTRL_APP_AMNI_ID
701 },
702 },
703 [RSE_CHIP_ID_2] = {
704 /* MCP Cross chip 2 to chip 0 MHU send frame */
705 {
706 HOST_MCP_N_TO_MCP_N_MHU_PHYS_BASE(2,0),
707 HOST_MCP_N_TO_MCP_N_MHU_PHYS_LIMIT(2,0),
708 SYSCTRL_APP_AMNI_ID
709 },
710 /* MCP Cross chip 2 to chip 1 MHU send frame */
711 {
712 HOST_MCP_N_TO_MCP_N_MHU_PHYS_BASE(2,1),
713 HOST_MCP_N_TO_MCP_N_MHU_PHYS_LIMIT(2,1),
714 SYSCTRL_APP_AMNI_ID
715 },
716 /* MCP Cross chip 2 to chip 3 MHU send frame */
717 {
718 HOST_MCP_N_TO_MCP_N_MHU_PHYS_BASE(2,3),
719 HOST_MCP_N_TO_MCP_N_MHU_PHYS_LIMIT(2,3),
720 SYSCTRL_APP_AMNI_ID
721 },
722 },
723 [RSE_CHIP_ID_3] = {
724 /* MCP Cross chip 3 to chip 0 MHU send frame */
725 {
726 HOST_MCP_N_TO_MCP_N_MHU_PHYS_BASE(3,0),
727 HOST_MCP_N_TO_MCP_N_MHU_PHYS_LIMIT(3,0),
728 SYSCTRL_APP_AMNI_ID
729 },
730 /* MCP Cross chip 3 to chip 1 MHU send frame */
731 {
732 HOST_MCP_N_TO_MCP_N_MHU_PHYS_BASE(3,1),
733 HOST_MCP_N_TO_MCP_N_MHU_PHYS_LIMIT(3,1),
734 SYSCTRL_APP_AMNI_ID
735 },
736 /* MCP Cross chip 3 to chip 2 MHU send frame */
737 {
738 HOST_MCP_N_TO_MCP_N_MHU_PHYS_BASE(3,2),
739 HOST_MCP_N_TO_MCP_N_MHU_PHYS_LIMIT(3,2),
740 SYSCTRL_APP_AMNI_ID
741 },
742 },
743 };
744
745 /*
746 * Accesses from RSE and SCP targeting LCP address space are handled by a
747 * NIC-400 which then forwards only the bottom [20:0] address bits of the
748 * request to rse_scp_axis interface. The bottom [20:0] address bits
749 * (range: 0x0 - 0x1FFFFF) are sent from NIC-400 to System Control NI-Tower
750 * for APU filtering of request from RSE/SCP to LCPs.
751 */
752 static const struct ni_tower_psam_reg_cfg_info rse_scp_axis_psam[] = {
753 {
754 HOST_CLUS_UTIL_LCP_SMCF_OFF_ADDR_PHYS_BASE,
755 HOST_CLUS_UTIL_MPMM_OFF_ADDR_PHYS_LIMIT,
756 SYSCTRL_LCP_AMNI_ID
757 },
758 };
759
760 /*
761 * Request originating from AP is mapped to targets based on following
762 * address map.
763 */
764 static const struct ni_tower_psam_reg_cfg_info app_axis_psam[] = {
765 /*
766 * Generic refclk + AP Watchdog peripherals + SID + ECC error record
767 * registers
768 */
769 {
770 HOST_GENERIC_REFCLK_CNTCONTROL_PHYS_BASE,
771 HOST_RSE_RL_ARSM_RAM_ECC_REC_PHYS_LIMIT,
772 SYSCTRL_APP_SCP_AMNI_ID
773 },
774 /* Refclk registers */
775 {
776 HOST_GENERIC_REFCLK_CNTREAD_PHYS_BASE,
777 HOST_AP_NS_REFCLK_CNTBASE1_PHYS_LIMIT,
778 SYSCTRL_APP_SCP_AMNI_ID
779 },
780 /* AP<->SCP MHUv3 registers */
781 {
782 HOST_AP_NS_SCP_MHUV3_PHYS_BASE,
783 HOST_AP_RT_SCP_MHUV3_PHYS_LIMIT,
784 SYSCTRL_APP_SCP_AMNI_ID
785 },
786 /* AP<->MCP MHUv3 registers */
787 {
788 HOST_AP_NS_MCP_MHUV3_SEND_BASE,
789 HOST_AP_RT_MCP_MHUV3_PHYS_LIMIT,
790 SYSCTRL_APP_MCP_AMNI_ID
791 },
792 /* AP<->RSE MHUv3 registers */
793 {
794 HOST_AP_NS_RSE_MHUV3_PHYS_BASE,
795 HOST_AP_RL_RSE_MHUV3_PHYS_LIMIT,
796 SYSCTRL_APP_SCP_AMNI_ID
797 },
798 };
799
800 /* Request from LCP is targeted completely to LCP_SCP_AXIM */
801 static const struct ni_tower_psam_reg_cfg_info lcp_axis_psam[] = {
802 {
803 HOST_LCP_MMAP_PHYS_BASE,
804 HOST_LCP_MMAP_PHYS_LIMIT,
805 SYSCTRL_LCP_SCP_AMNI_ID
806 },
807 };
808
809 /*
810 * Requester side MCP AXIS APU to check access permission targeting Generic
811 * refclk in SCP and shared RSM SRAM
812 */
813 static const struct ni_tower_apu_reg_cfg_info mcp_axis_apu[] = {
814 /* Root read-write permission : Generic refclk registers */
815 INIT_APU_REGION(HOST_GENERIC_REFCLK_CNTCONTROL_PHYS_BASE,
816 HOST_GENERIC_REFCLK_CNTCONTROL_PHYS_LIMIT,
817 NI_T_ROOT_RW),
818 /* Full permission : Shared RSM SRAM */
819 INIT_APU_REGION(HOST_RSM_SRAM_PHYS_BASE,
820 HOST_RSM_SRAM_PHYS_LIMIT,
821 NI_T_ALL_PERM),
822 };
823
824 /*
825 * Completer side RSM AXIM APU to check access permission targeting Shared RAM
826 * between RSE, SCP and MCP
827 */
828 static const struct ni_tower_apu_reg_cfg_info rsm_axim_apu[] = {
829 INIT_APU_REGION(HOST_RSM_SRAM_PHYS_BASE,
830 HOST_RSM_SRAM_PHYS_LIMIT,
831 NI_T_ALL_PERM),
832 };
833
834 /*
835 * RSM APBM APU to check the ECC Error record register block for Shared RAM
836 * between RSE, SCP and MCP
837 */
838 static const struct ni_tower_apu_reg_cfg_info rsm_apbm_apu[] = {
839 INIT_APU_REGION(HOST_RSE_S_RSM_RAM_ECC_REC_PHYS_BASE,
840 HOST_RSE_S_RSM_RAM_ECC_REC_PHYS_LIMIT,
841 NI_T_SEC_RW | NI_T_ROOT_RW),
842 INIT_APU_REGION(HOST_RSE_NS_RSM_RAM_ECC_REC_PHYS_BASE,
843 HOST_RSE_NS_RSM_RAM_ECC_REC_PHYS_LIMIT,
844 NI_T_ALL_PERM),
845 INIT_APU_REGION(HOST_SCP_S_RSM_RAM_ECC_REC_PHYS_BASE,
846 HOST_SCP_S_RSM_RAM_ECC_REC_PHYS_LIMIT,
847 NI_T_SEC_RW | NI_T_ROOT_RW),
848 INIT_APU_REGION(HOST_SCP_NS_RSM_RAM_ECC_REC_PHYS_BASE,
849 HOST_SCP_NS_RSM_RAM_ECC_REC_PHYS_LIMIT,
850 NI_T_ALL_PERM),
851 INIT_APU_REGION(HOST_MCP_S_RSM_RAM_ECC_REC_PHYS_BASE,
852 HOST_MCP_S_RSM_RAM_ECC_REC_PHYS_LIMIT,
853 NI_T_SEC_RW | NI_T_ROOT_RW),
854 INIT_APU_REGION(HOST_MCP_NS_RSM_RAM_ECC_REC_PHYS_BASE,
855 HOST_MCP_NS_RSM_RAM_ECC_REC_PHYS_LIMIT,
856 NI_T_ALL_PERM),
857 };
858
859 /*
860 * Completer side RSE-SCP AXIM APU to check access permission targeting the SCP
861 */
862 static const struct ni_tower_apu_reg_cfg_info rse_scp_axim_apu[] = {
863 INIT_APU_REGION(HOST_SCP_PHYS_BASE,
864 HOST_SCP_PHYS_LIMIT,
865 NI_T_ALL_PERM),
866 };
867
868 /*
869 * Completer side RSE-MCP AXIM APU to check access permission targeting the MCP
870 */
871 static const struct ni_tower_apu_reg_cfg_info rse_mcp_axim_apu[] = {
872 INIT_APU_REGION(HOST_MCP_PHYS_BASE,
873 HOST_MCP_PHYS_LIMIT,
874 NI_T_ALL_PERM),
875 };
876
877 /*
878 * Requester side APP AXIS APU to check access permission targeting the
879 * peripherals in SCP, MCP and RSE
880 */
881 static const struct ni_tower_apu_reg_cfg_info app_axis_apu[] = {
882 /* Root read-write permission : Generic refclk registers */
883 INIT_APU_REGION(HOST_GENERIC_REFCLK_CNTCONTROL_PHYS_BASE,
884 HOST_GENERIC_REFCLK_CNTCONTROL_PHYS_LIMIT,
885 NI_T_ROOT_RW),
886 /* Full permission : AP Watchdog peripheral */
887 INIT_APU_REGION(HOST_AP_NS_WDOG_PHYS_BASE,
888 HOST_AP_NS_WDOG_PHYS_LIMIT,
889 NI_T_ALL_PERM),
890 /* Root read-write permission : AP Watchdog peripheral */
891 INIT_APU_REGION(HOST_AP_RT_WDOG_PHYS_BASE,
892 HOST_AP_RT_WDOG_PHYS_LIMIT,
893 NI_T_ROOT_RW),
894 /* Secure read-write permission : AP Watchdog peripheral */
895 INIT_APU_REGION(HOST_AP_S_WDOG_PHYS_BASE,
896 HOST_AP_S_WDOG_PHYS_LIMIT,
897 NI_T_SEC_RW),
898 /* Full permission : SID */
899 INIT_APU_REGION(HOST_SID_PHYS_BASE,
900 HOST_SID_PHYS_LIMIT,
901 NI_T_ALL_PERM),
902 /* Secure read-write permission : AP ECC error record */
903 INIT_APU_REGION(HOST_AP_S_ARSM_RAM_ECC_REC_PHYS_BASE,
904 HOST_AP_S_ARSM_RAM_ECC_REC_PHYS_LIMIT,
905 NI_T_SEC_RW),
906 /* Full permission : AP ECC error record */
907 INIT_APU_REGION(HOST_AP_NS_ARSM_RAM_ECC_REC_PHYS_BASE,
908 HOST_AP_NS_ARSM_RAM_ECC_REC_PHYS_LIMIT,
909 NI_T_ALL_PERM),
910 /* Root read-write permission : AP ECC error record */
911 INIT_APU_REGION(HOST_AP_RT_ARSM_RAM_ECC_REC_PHYS_BASE,
912 HOST_AP_RT_ARSM_RAM_ECC_REC_PHYS_LIMIT,
913 NI_T_ROOT_RW),
914 /* Realm read-write permission : AP ECC error record */
915 INIT_APU_REGION(HOST_AP_RL_ARSM_RAM_ECC_REC_PHYS_BASE,
916 HOST_AP_RL_ARSM_RAM_ECC_REC_PHYS_LIMIT,
917 NI_T_REALM_RW),
918 /*
919 * Secure & Root read-write permission : SCP/MCP/RSE ECC error record +
920 * SCP/MCP/RSE RSM ECC error record + Generic refclk registers +
921 * AP refclk registers
922 */
923 INIT_APU_REGION(HOST_SCP_S_ARSM_RAM_ECC_REC_PHYS_BASE,
924 HOST_AP_NS_REFCLK_CNTBASE1_PHYS_LIMIT,
925 NI_T_SEC_RW),
926 /* Full permission : AP<->SCP MHUv3 registers */
927 INIT_APU_REGION(HOST_AP_NS_SCP_MHUV3_PHYS_BASE,
928 HOST_AP_NS_SCP_MHUV3_PHYS_LIMIT,
929 NI_T_ALL_PERM),
930 /* Secure & Root read-write permission : AP<->SCP MHUv3 registers */
931 INIT_APU_REGION(HOST_AP_S_SCP_MHUV3_PHYS_BASE,
932 HOST_AP_S_SCP_MHUV3_PHYS_LIMIT,
933 NI_T_SEC_RW | NI_T_ROOT_RW),
934 /* Root read-write permission : AP<->SCP MHUv3 registers */
935 INIT_APU_REGION(HOST_AP_RT_SCP_MHUV3_PHYS_BASE,
936 HOST_AP_RT_SCP_MHUV3_PHYS_LIMIT,
937 NI_T_ROOT_RW),
938 /* Full permission : AP<->MCP MHUv3 registers */
939 INIT_APU_REGION(HOST_AP_NS_MCP_MHUV3_SEND_BASE,
940 HOST_AP_NS_MCP_MHUV3_SEND_LIMIT,
941 NI_T_ALL_PERM),
942 /* Secure read-write permission : AP<->MCP MHUv3 registers */
943 INIT_APU_REGION(HOST_AP_S_MCP_MHUV3_PHYS_BASE,
944 HOST_AP_S_MCP_MHUV3_PHYS_LIMIT,
945 NI_T_SEC_RW),
946 /* Root read-write permission : AP<->MCP MHUv3 registers */
947 INIT_APU_REGION(HOST_AP_RT_MCP_MHUV3_PHYS_BASE,
948 HOST_AP_RT_MCP_MHUV3_PHYS_LIMIT,
949 NI_T_ROOT_RW),
950 /* Full permission : AP<->RSE MHUv3 registers */
951 INIT_APU_REGION(HOST_AP_NS_RSE_MHUV3_PHYS_BASE,
952 HOST_AP_NS_RSE_MHUV3_PHYS_LIMIT,
953 NI_T_ALL_PERM),
954 /* Secure read-write permission : AP<->RSE MHUv3 registers */
955 INIT_APU_REGION(HOST_AP_S_RSE_MHUV3_PHYS_BASE,
956 HOST_AP_S_RSE_MHUV3_PHYS_LIMIT,
957 NI_T_SEC_RW),
958 /* Root read-write permission : AP<->RSE MHUv3 registers */
959 INIT_APU_REGION(HOST_AP_RT_RSE_MHUV3_PHYS_BASE,
960 HOST_AP_RT_RSE_MHUV3_PHYS_LIMIT,
961 NI_T_ROOT_RW),
962 /* Root & Realm read-write permission : AP<->RSE MHUv3 registers */
963 INIT_APU_REGION(HOST_AP_RL_RSE_MHUV3_PHYS_BASE,
964 HOST_AP_RL_RSE_MHUV3_PHYS_LIMIT,
965 NI_T_ROOT_RW | NI_T_REALM_RW),
966 };
967
968 /*
969 * Completer side APP AXIM APU to check access permission targeting the IO
970 * block and the memory controller + MPE registers space
971 */
972 static const struct ni_tower_apu_reg_cfg_info app_axim_apu[] = {
973 /*
974 * Full permission for the entire AP address expect for the following
975 * regions:
976 * 1. Root & Secure read-write permission for IO integration control
977 * registers.
978 * 2. Deny full access to MCP for Memory Controller, MPE register
979 * space, LCP peripherals and Cluster Utility region.
980 */
981 INIT_APU_REGION(HOST_AP_SHARED_SRAM_PHYS_BASE,
982 HOST_CMN_GPV_PHYS_LIMIT,
983 NI_T_ALL_PERM),
984 INIT_APU_REGION(HOST_IO_BLOCK_PHYS_BASE,
985 HOST_IO_NCI_GPV_PHYS_LIMIT(0),
986 NI_T_ALL_PERM),
987 INIT_APU_REGION(HOST_IO_INTEGRATION_CTRL_PHYS_BASE(0),
988 HOST_IO_INTEGRATION_CTRL_PHYS_LIMIT(0),
989 NI_T_ROOT_RW | NI_T_SEC_RW),
990 INIT_APU_REGION(HOST_IO_EXP_INTERFACE_PHYS_BASE(0),
991 HOST_IO_NCI_GPV_PHYS_LIMIT(1),
992 NI_T_ALL_PERM),
993 INIT_APU_REGION(HOST_IO_INTEGRATION_CTRL_PHYS_BASE(1),
994 HOST_IO_INTEGRATION_CTRL_PHYS_LIMIT(1),
995 NI_T_ROOT_RW | NI_T_SEC_RW),
996 INIT_APU_REGION(HOST_IO_EXP_INTERFACE_PHYS_BASE(1),
997 HOST_IO_PCIE_CTRL_EXP_PHYS_LIMIT(1),
998 NI_T_ALL_PERM),
999 INIT_APU_REGION(HOST_IO_NCI_GPV_PHYS_BASE(2),
1000 HOST_IO_NCI_GPV_PHYS_LIMIT(2),
1001 NI_T_ALL_PERM),
1002 INIT_APU_REGION(HOST_IO_NCI_GPV_PHYS_BASE(3),
1003 HOST_IO_NCI_GPV_PHYS_LIMIT(3),
1004 NI_T_ALL_PERM),
1005 INIT_APU_REGION(HOST_SYSCTRL_SMMU_PHYS_BASE,
1006 HOST_AP_MEM_EXP_3_PHYS_LIMIT,
1007 NI_T_ALL_PERM),
1008 /* Allow only for RSE, SCP and AP */
1009 INIT_APU_REGION_WITH_ALL_ID_FILTER(HOST_MPE_PHYS_BASE,
1010 HOST_MPE_PHYS_LIMIT,
1011 /* mcp_perm */ 0,
1012 /* scp_perm */ NI_T_ALL_PERM,
1013 /* rse_perm */ NI_T_ALL_PERM,
1014 /* dap_perm */ 0),
1015 /* Allow only for RSE, SCP and AP */
1016 INIT_APU_REGION_WITH_ALL_ID_FILTER(HOST_CLUST_UTIL_PHYS_BASE,
1017 HOST_CLUST_UTIL_PHYS_LIMIT,
1018 /* mcp_perm */ 0,
1019 /* scp_perm */ NI_T_ALL_PERM,
1020 /* rse_perm */ NI_T_ALL_PERM,
1021 /* dap_perm */ 0),
1022 };
1023
1024 /*
1025 * Completer side LCP AXIM APU to check access permission targeting the Cluster
1026 * Utility space.
1027 */
1028 static const struct ni_tower_apu_reg_cfg_info lcp_axim_apu[] = {
1029 INIT_APU_REGION(HOST_CLUS_UTIL_LCP_SMCF_OFF_ADDR_PHYS_BASE,
1030 HOST_CLUS_UTIL_LCP_SMCF_OFF_ADDR_PHYS_LIMIT,
1031 NI_T_SEC_RW | NI_T_ROOT_RW),
1032 INIT_APU_REGION(HOST_CLUS_UTIL_CLUS_CTRL_OFF_ADDR_PHYS_BASE,
1033 HOST_CLUS_UTIL_CLUS_CTRL_OFF_ADDR_PHYS_LIMIT,
1034 NI_T_SEC_RW | NI_T_ROOT_RW),
1035 INIT_APU_REGION(HOST_CLUS_UTIL_PPU_OFF_ADDR_PHYS_BASE,
1036 HOST_CLUS_UTIL_PPU_OFF_ADDR_PHYS_LIMIT,
1037 NI_T_SEC_RW | NI_T_ROOT_RW),
1038 INIT_APU_REGION(HOST_CLUS_UTIL_AMU_OFF_ADDR_PHYS_BASE,
1039 HOST_CLUS_UTIL_AMU_OFF_ADDR_PHYS_LIMIT,
1040 NI_T_N_SEC_RW | NI_T_SEC_RW | NI_T_ROOT_RW),
1041 INIT_APU_REGION(HOST_CLUS_UTIL_RAS_OFF_ADDR_PHYS_BASE,
1042 HOST_CLUS_UTIL_MPMM_OFF_ADDR_PHYS_LIMIT,
1043 NI_T_SEC_RW | NI_T_ROOT_RW),
1044 };
1045
1046 /* Requester side LCP AXIS APU to check access permission targeting the SCP */
1047 static const struct ni_tower_apu_reg_cfg_info lcp_axis_apu[] = {
1048 INIT_APU_REGION(HOST_AP_SHARED_SRAM_PHYS_BASE,
1049 HOST_AP_MEM_EXP_3_PHYS_LIMIT,
1050 NI_T_ALL_PERM),
1051 };
1052
1053 /*
1054 * Configure Programmable System Address Map (PSAM) to setup the memory map and
1055 * its target ID for each requester in the System Control NI-Tower for nodes
1056 * under AON domain.
1057 */
program_sysctrl_psam_aon(uint32_t chip_id)1058 static int32_t program_sysctrl_psam_aon(uint32_t chip_id)
1059 {
1060 enum ni_tower_err err;
1061
1062 /* Populates all address maps into a table array to enable desired PSAMs */
1063 const struct ni_tower_psam_cfgs psam_table[] = {
1064 {
1065 .component = &sysctrl_rse_main_asni,
1066 .nh_region_count = ARRAY_SIZE(rse_main_axis_0_psam),
1067 .regions = rse_main_axis_0_psam,
1068 .add_chip_addr_offset = true,
1069 },
1070 {
1071 .component = &sysctrl_rse_main_asni,
1072 .nh_region_count = ARRAY_SIZE(rse_main_axis_1_psam),
1073 .regions = rse_main_axis_1_psam,
1074 .add_chip_addr_offset = false,
1075 },
1076 {
1077 .component = &sysctrl_rse_main_asni,
1078 .nh_region_count = MHU_SEND_FRAME_SIZE,
1079 .regions = rse_main_axis_psam_mhu_send_frame[chip_id],
1080 },
1081 {
1082 .component = &sysctrl_scp_asni,
1083 .nh_region_count = ARRAY_SIZE(scp_axis_0_psam),
1084 .regions = scp_axis_0_psam,
1085 .add_chip_addr_offset = true,
1086 },
1087 {
1088 .component = &sysctrl_scp_asni,
1089 .nh_region_count = ARRAY_SIZE(scp_axis_1_psam),
1090 .regions = scp_axis_1_psam,
1091 .add_chip_addr_offset = false,
1092 },
1093 {
1094 .component = &sysctrl_scp_asni,
1095 .nh_region_count = MHU_SEND_FRAME_SIZE,
1096 .regions = scp_axis_psam_mhu_send_frame[chip_id],
1097 },
1098 {
1099 .component = &sysctrl_mcp_asni,
1100 .nh_region_count = ARRAY_SIZE(mcp_axis_psam),
1101 .regions = mcp_axis_psam,
1102 .add_chip_addr_offset = true,
1103 },
1104 {
1105 .component = &sysctrl_mcp_asni,
1106 .nh_region_count = MHU_SEND_FRAME_SIZE,
1107 .regions = mcp_axis_psam_mhu_send_frame[chip_id],
1108 },
1109 {
1110 .component = &sysctrl_rse_scp_asni,
1111 .nh_region_count = ARRAY_SIZE(rse_scp_axis_psam),
1112 .regions = rse_scp_axis_psam,
1113 .add_chip_addr_offset = false,
1114 },
1115 };
1116
1117 err = ni_tower_program_psam_table(&SYSCTRL_NI_TOWER_DEV, psam_table,
1118 ARRAY_SIZE(psam_table));
1119 if (err != NI_TOWER_SUCCESS) {
1120 return -1;
1121 }
1122
1123 return 0;
1124 }
1125
1126 /*
1127 * Configure Access Protection Unit (APU) to setup access permission for each
1128 * memory region based on its target in System Control NI-Tower for nodes
1129 * under AON domain.
1130 */
program_sysctrl_apu_aon(void)1131 static int32_t program_sysctrl_apu_aon(void)
1132 {
1133 enum ni_tower_err err;
1134
1135 /*
1136 * Populates all APU entry into a table array to confgiure and enable
1137 * desired APUs
1138 */
1139 const struct ni_tower_apu_cfgs apu_table[] = {
1140 {
1141 .component = &sysctrl_mcp_asni,
1142 .region_count = ARRAY_SIZE(mcp_axis_apu),
1143 .regions = mcp_axis_apu,
1144 .add_chip_addr_offset = false,
1145 },
1146 {
1147 .component = &sysctrl_rsm_amni,
1148 .region_count = ARRAY_SIZE(rsm_axim_apu),
1149 .regions = rsm_axim_apu,
1150 .add_chip_addr_offset = true,
1151 },
1152 {
1153 .component = &sysctrl_rsm_pmni,
1154 .region_count = ARRAY_SIZE(rsm_apbm_apu),
1155 .regions = rsm_apbm_apu,
1156 .add_chip_addr_offset = true,
1157 },
1158 {
1159 .component = &sysctrl_rse_scp_amni,
1160 .region_count = ARRAY_SIZE(rse_scp_axim_apu),
1161 .regions = rse_scp_axim_apu,
1162 .add_chip_addr_offset = false,
1163 },
1164 {
1165 .component = &sysctrl_rse_mcp_amni,
1166 .region_count = ARRAY_SIZE(rse_mcp_axim_apu),
1167 .regions = rse_mcp_axim_apu,
1168 .add_chip_addr_offset = false,
1169 },
1170 };
1171
1172 err = ni_tower_program_apu_table(&SYSCTRL_NI_TOWER_DEV, apu_table,
1173 ARRAY_SIZE(apu_table));
1174 if (err != NI_TOWER_SUCCESS) {
1175 return -1;
1176 }
1177
1178 return 0;
1179 }
1180
1181 /*
1182 * Configure Programmable System Address Map (PSAM) to setup the memory map and
1183 * its target ID for each requester in the System Control NI-Tower for nodes
1184 * under SYSTOP domain.
1185 */
program_sysctrl_psam_systop(void)1186 static int32_t program_sysctrl_psam_systop(void)
1187 {
1188 enum ni_tower_err err;
1189
1190 /* Populates all address maps into a table array to enable desired PSAMs */
1191 const struct ni_tower_psam_cfgs psam_table[] = {
1192 {
1193 .component = &sysctrl_app_asni,
1194 .nh_region_count = ARRAY_SIZE(app_axis_psam),
1195 .regions = app_axis_psam,
1196 .add_chip_addr_offset = false,
1197 },
1198 {
1199 .component = &sysctrl_lcp_asni,
1200 .nh_region_count = ARRAY_SIZE(lcp_axis_psam),
1201 .regions = lcp_axis_psam,
1202 .add_chip_addr_offset = false,
1203 },
1204 };
1205
1206 err = ni_tower_program_psam_table(&SYSCTRL_NI_TOWER_DEV, psam_table,
1207 ARRAY_SIZE(psam_table));
1208 if (err != NI_TOWER_SUCCESS) {
1209 return -1;
1210 }
1211
1212 return 0;
1213 }
1214
1215 /*
1216 * Configure Access Protection Unit (APU) to setup access permission for each
1217 * memory region based on its target in System Control NI-Tower for nodes
1218 * under SYSTOP domain.
1219 */
program_sysctrl_apu_systop(void)1220 static int32_t program_sysctrl_apu_systop(void)
1221 {
1222 enum ni_tower_err err;
1223
1224 /*
1225 * Populates all APU entry into a table array to configure and enable
1226 * desired APUs
1227 */
1228 const struct ni_tower_apu_cfgs apu_table[] = {
1229 {
1230 .component = &sysctrl_app_asni,
1231 .region_count = ARRAY_SIZE(app_axis_apu),
1232 .regions = app_axis_apu,
1233 .add_chip_addr_offset = false,
1234 },
1235 {
1236 .component = &sysctrl_app_amni,
1237 .region_count = ARRAY_SIZE(app_axim_apu),
1238 .regions = app_axim_apu,
1239 .add_chip_addr_offset = false,
1240 },
1241 {
1242 .component = &sysctrl_lcp_amni,
1243 .region_count = ARRAY_SIZE(lcp_axim_apu),
1244 .regions = lcp_axim_apu,
1245 .add_chip_addr_offset = false,
1246 },
1247 {
1248 .component = &sysctrl_lcp_asni,
1249 .region_count = ARRAY_SIZE(lcp_axis_apu),
1250 .regions = lcp_axis_apu,
1251 .add_chip_addr_offset = false,
1252 },
1253 };
1254
1255 err = ni_tower_program_apu_table(&SYSCTRL_NI_TOWER_DEV, apu_table,
1256 ARRAY_SIZE(apu_table));
1257 if (err != NI_TOWER_SUCCESS) {
1258 return -1;
1259 }
1260
1261 return 0;
1262 }
1263
program_sysctrl_ni_tower_aon(uint32_t chip_id)1264 int32_t program_sysctrl_ni_tower_aon(uint32_t chip_id)
1265 {
1266 if (chip_id >= RSE_MAX_SUPPORTED_CHIPS) {
1267 return -1;
1268 }
1269
1270 if (program_sysctrl_psam_aon(chip_id) != 0) {
1271 return -1;
1272 }
1273
1274 if (program_sysctrl_apu_aon() != 0) {
1275 return -1;
1276 }
1277
1278 return 0;
1279 }
1280
program_sysctrl_ni_tower_systop(void)1281 int32_t program_sysctrl_ni_tower_systop(void)
1282 {
1283 if (program_sysctrl_psam_systop() != 0) {
1284 return -1;
1285 }
1286
1287 if (program_sysctrl_apu_systop() != 0) {
1288 return -1;
1289 }
1290
1291 return 0;
1292 }
1293
