1 /* 2 * Copyright (c) 2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef __RSE_EXPANSION_REGS_H__ 9 #define __RSE_EXPANSION_REGS_H__ 10 11 #include "tfm_hal_device_header.h" 12 13 #include <stdint.h> 14 15 __PACKED_STRUCT rse_integ_t { 16 __IOM uint32_t rsecoreclk_ctrl; /* 0x000 */ 17 __IOM uint32_t rsecoreclk_div; /* 0x004 */ 18 const uint32_t reserved0[2]; 19 __IOM uint32_t rse_integration; /* 0x010*/ 20 __IOM uint32_t atu_ap; /* 0x014 */ 21 const uint32_t reserved1[1005]; 22 __IM uint32_t pidr4; /* 0xFD0 */ 23 const uint32_t reserved2[3]; 24 __IM uint32_t pidr0; /* 0xFE0 */ 25 __IM uint32_t pidr1; /* 0xFE4 */ 26 __IM uint32_t pidr2; /* 0xFE8 */ 27 __IM uint32_t pidr3; /* 0xFEC */ 28 __IM uint32_t cidr0; /* 0xFF0 */ 29 __IM uint32_t cidr1; /* 0xFF4 */ 30 __IM uint32_t cidr2; /* 0xFF8 */ 31 __IM uint32_t cidr3; /* 0xFFC */ 32 }; 33 34 /* Field definitions for RSECORECLK_CTRL register */ 35 #define RSE_INTEG_CLKCTRL_SEL_POS (0U) 36 #define RSE_INTEG_CLKCTRL_SEL_MSK (0xFFUL << RSE_INTEG_CLKCTRL_SEL_POS) 37 #define RSE_INTEG_CLKCTRL_SEL_REF (0x1UL << RSE_INTEG_CLKCTRL_SEL_POS) 38 #define RSE_INTEG_CLKCTRL_SEL_SPLL (0x2UL << RSE_INTEG_CLKCTRL_SEL_POS) 39 #define RSE_INTEG_CLKCTRL_SEL_CUR_POS (8U) 40 #define RSE_INTEG_CLKCTRL_SEL_CUR_MSK (0xFFUL << RSE_INTEG_CLKCTRL_SEL_CUR_POS) 41 #define RSE_INTEG_CLKCTRL_SEL_CUR_REF (0x1UL << RSE_INTEG_CLKCTRL_SEL_CUR_POS) 42 #define RSE_INTEG_CLKCTRL_SEL_CUR_SPLL (0x2UL << RSE_INTEG_CLKCTRL_SEL_CUR_POS) 43 44 /* Field definitions for RSECORECLK_DIV register */ 45 #define RSE_INTEG_CLKDIV_DIV_POS (0U) 46 #define RSE_INTEG_CLKDIV_DIV_MSK (0xFUL << RSE_INTEG_CLKDIV_DIV_POS) 47 #define RSE_INTEG_CLKDIV_DIV_CUR_POS (16U) 48 #define RSE_INTEG_CLKDIV_DIV_CUR_MSK (0x4UL << RSE_INTEG_CLKDIV_DIV_CUR_POS) 49 50 /* Field definitions for RSE_INTEGRATION register */ 51 #define RSE_INTEG_INTEG_SCP_RESET_POS (0U) 52 #define RSE_INTEG_INTEG_SCP_RESET_MSK (0x1UL << RSE_INTEG_INTEG_SCP_RESET_POS) 53 #define RSE_INTEG_INTEG_SCP_RESET RSE_INTEG_INTEG_SCP_RESET_MSK 54 #define RSE_INTEG_INTEG_MCP_RESET_POS (1U) 55 #define RSE_INTEG_INTEG_MCP_RESET_MSK (0x1UL << RSE_INTEG_INTEG_MCP_RESET_POS) 56 #define RSE_INTEG_INTEG_MCP_RESET RSE_INTEG_INTEG_MCP_RESET_MSK 57 #define RSE_INTEG_INTEG_SCP_RE_CLR_POS (3U) 58 #define RSE_INTEG_INTEG_SCP_RE_CLR_MSK (0x1UL << RSE_INTEG_INTEG_SCP_RE_CLR_POS) 59 #define RSE_INTEG_INTEG_SCP_RE_CLR RSE_INTEG_INTEG_SCP_RE_CLR_MSK 60 #define RSE_INTEG_INTEG_MCP_RE_CLR_POS (4U) 61 #define RSE_INTEG_INTEG_MCP_RE_CLR_MSK (0x1UL << RSE_INTEG_INTEG_MCP_RE_CLR_POS) 62 #define RSE_INTEG_INTEG_CHIP_ID_POS (8U) 63 #define RSE_INTEG_INTEG_CHIP_ID_MSK (0xFUL << RSE_INTEG_INTEG_CHIP_ID_POS) 64 #define RSE_INTEG_INTEG_MCHIP_POS (16U) 65 #define RSE_INTEG_INTEG_MCHIP_MSK (0x1UL << RSE_INTEG_INTEG_MCHIP_POS) 66 #define RSE_INTEG_INTEG_MCHIP RSE_INTEG_INTEG_MCHIP_MSK 67 #define RSE_INTEG_INTEG_SCP_SLEEP_POS (17U) 68 #define RSE_INTEG_INTEG_SCP_SLEEP_MSK (0x1UL << RSE_INTEG_INTEG_SCP_SLEEP_POS) 69 #define RSE_INTEG_INTEG_SCP_SLEEP RSE_INTEG_INTEG_SCP_SLEEP_MSK 70 #define RSE_INTEG_INTEG_MCP_SLEEP_POS (18U) 71 #define RSE_INTEG_INTEG_MCP_SLEEP_MSK (0x1UL << RSE_INTEG_INTEG_MCP_SLEEP_POS) 72 #define RSE_INTEG_INTEG_MCP_SLEEP RSE_INTEG_INTEG_MCP_SLEEP_MSK 73 74 /* Field definitions for ATU_AP register */ 75 #define RSE_INTEG_ATU_AP_SCP_ATU_POS (0U) 76 #define RSE_INTEG_ATU_AP_SCP_ATU_MSK (0x1UL << RSE_INTEG_ATU_AP_SCP_ATU_POS) 77 #define RSE_INTEG_ATU_AP_SCP_ATU RSE_INTEG_ATU_AP_SCP_ATU_MSK 78 #define RSE_INTEG_ATU_AP_MCP_ATU_POS (1U) 79 #define RSE_INTEG_ATU_AP_MCP_ATU_MSK (0x1UL << RSE_INTEG_ATU_AP_MCP_ATU_POS) 80 #define RSE_INTEG_ATU_AP_MCP_ATU RSE_INTEG_ATU_AP_MCP_ATU_MSK 81 82 #endif /* __RSE_EXPANSION_REGS_H__ */ 83
