1 /*
2  * Copyright (c) 2019-2024, Arm Limited. All rights reserved.
3  * Copyright (c) 2020-2023 Cypress Semiconductor Corporation (an Infineon company)
4  * or an affiliate of Cypress Semiconductor Corporation. All rights reserved.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  *
8  */
9 
10 #ifndef __TFM_PERIPHERALS_DEF_H__
11 #define __TFM_PERIPHERALS_DEF_H__
12 
13 #include "platform_irq.h"
14 #include "common_target_cfg.h"
15 
16 #ifdef __cplusplus
17 extern "C" {
18 #endif
19 
20 /*
21  * Quantized default IRQ priority, the value is:
22  * (Number of configurable priority) / 4: (1UL << __NVIC_PRIO_BITS) / 4
23  */
24 #define DEFAULT_IRQ_PRIORITY    (1UL << (__NVIC_PRIO_BITS - 2))
25 
26 #define TFM_TIMER0_IRQ           (TIMER0_IRQn)
27 #define TFM_DMA0_COMBINED_S_IRQ  (DMA_Combined_S_IRQn)
28 
29 extern struct platform_data_t tfm_peripheral_std_uart;
30 extern struct platform_data_t tfm_peripheral_timer0;
31 extern struct platform_data_t tfm_peripheral_dma0_ch0;
32 
33 #define TFM_PERIPHERAL_STD_UART  (&tfm_peripheral_std_uart)
34 #define TFM_PERIPHERAL_TIMER0    (&tfm_peripheral_timer0)
35 #define TFM_PERIPHERAL_DMA0_CH0  (&tfm_peripheral_dma0_ch0)
36 
37 /* AP to RSE MHU receiver interrupt */
38 #define MAILBOX_IRQ   CMU_MHU0_Receiver_IRQn    /* AP_MONITOR  */
39 #define MAILBOX_IRQ_1 CMU_MHU1_Receiver_IRQn    /* AP_NS */
40 
41 /* Append RSE-specific static MPU regions to the standard ones in
42  * tfm_hal_isolation_v8m.c.
43  */
44 #define PLATFORM_STATIC_MPU_REGIONS \
45     /* Keep ROM as no-execute, and prevent unpriv from accessing */ \
46     { \
47         ARM_MPU_RBAR(ROM_BASE_S, \
48                      ARM_MPU_SH_NON, \
49                      ARM_MPU_READ_ONLY, \
50                      ARM_MPU_PRIVILEGED, \
51                      ARM_MPU_EXECUTE_NEVER), \
52         ARM_MPU_RLAR_PXN(ROM_BASE_S + ROM_SIZE - 1, \
53                          ARM_MPU_PRIVILEGE_EXECUTE_NEVER, \
54                          0), \
55     }, \
56     /* Mark ITCM as privileged, read-only, execute-ok */ \
57     { \
58         ARM_MPU_RBAR(ITCM_BASE_NS, \
59                      ARM_MPU_SH_NON, \
60                      ARM_MPU_READ_ONLY, \
61                      ARM_MPU_PRIVILEGED, \
62                      ARM_MPU_EXECUTE_OK), \
63         ARM_MPU_RLAR_PXN(ITCM_BASE_NS + ITCM_SIZE - 1, \
64                          ARM_MPU_PRIVILEGE_EXECUTE_OK, \
65                          0), \
66     }, \
67     { \
68         ARM_MPU_RBAR(ITCM_BASE_S, \
69                      ARM_MPU_SH_NON, \
70                      ARM_MPU_READ_ONLY, \
71                      ARM_MPU_PRIVILEGED, \
72                      ARM_MPU_EXECUTE_OK), \
73         ARM_MPU_RLAR_PXN(ITCM_BASE_S + ITCM_SIZE - 1, \
74                          ARM_MPU_PRIVILEGE_EXECUTE_OK, \
75                          0), \
76     }, \
77     /* Mark DTCM as privileged, read-write, execute-never */ \
78     { \
79         ARM_MPU_RBAR(DTCM_BASE_NS, \
80                      ARM_MPU_SH_NON, \
81                      ARM_MPU_READ_WRITE, \
82                      ARM_MPU_PRIVILEGED, \
83                      ARM_MPU_EXECUTE_NEVER), \
84         ARM_MPU_RLAR_PXN(DTCM_BASE_NS + DTCM_SIZE - 1, \
85                          ARM_MPU_PRIVILEGE_EXECUTE_NEVER, \
86                          0), \
87     }, \
88     { \
89         ARM_MPU_RBAR(DTCM_BASE_S, \
90                      ARM_MPU_SH_NON, \
91                      ARM_MPU_READ_WRITE, \
92                      ARM_MPU_PRIVILEGED, \
93                      ARM_MPU_EXECUTE_NEVER), \
94         ARM_MPU_RLAR_PXN(DTCM_BASE_S + DTCM_SIZE - 1, \
95                          ARM_MPU_PRIVILEGE_EXECUTE_NEVER, \
96                          0), \
97     },
98 
99 #ifdef __cplusplus
100 }
101 #endif
102 
103 #endif /* __TFM_PERIPHERALS_DEF_H__ */
104