1 /*
2 * Copyright (c) 2019-2023 Arm Limited. All rights reserved.
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #include "common_target_cfg.h"
18 #include "Driver_MPC.h"
19 #include "Driver_PPC.h"
20 #include "device_definition.h"
21 #include "platform_description.h"
22 #include "region_defs.h"
23 #include "mpu_armv8m_drv.h"
24 #include "tfm_plat_defs.h"
25 #include "region.h"
26
27 /* Debug configuration flags */
28 #define SPNIDEN_SEL_STATUS (0x01u << 7)
29 #define SPNIDEN_STATUS (0x01u << 6)
30 #define SPIDEN_SEL_STATUS (0x01u << 5)
31 #define SPIDEN_STATUS (0x01u << 4)
32 #define NIDEN_SEL_STATUS (0x01u << 3)
33 #define NIDEN_STATUS (0x01u << 2)
34 #define DBGEN_SEL_STATUS (0x01u << 1)
35 #define DBGEN_STATUS (0x01u << 0)
36
37 #define All_SEL_STATUS (SPNIDEN_SEL_STATUS | SPIDEN_SEL_STATUS | \
38 NIDEN_SEL_STATUS | DBGEN_SEL_STATUS)
39
40 static struct mpu_armv8m_dev_t dev_mpu = { MPU_BASE };
41
42 /* Allows software, via SAU, to define the code region as a NSC */
43 #define NSCCFG_CODENSC 1
44
45 extern const struct memory_region_limits memory_regions;
46
47 /* Import MPC drivers */
48 extern ARM_DRIVER_MPC Driver_QSPI_MPC;
49 extern ARM_DRIVER_MPC Driver_ISRAM0_MPC;
50 extern ARM_DRIVER_MPC Driver_ISRAM1_MPC;
51 extern ARM_DRIVER_MPC Driver_ISRAM2_MPC;
52 extern ARM_DRIVER_MPC Driver_ISRAM3_MPC;
53
54 /* Import PPC drivers */
55 extern ARM_DRIVER_PPC Driver_AHB_PPCEXP0;
56 extern ARM_DRIVER_PPC Driver_APB_PPC0;
57 extern ARM_DRIVER_PPC Driver_APB_PPC1;
58 extern ARM_DRIVER_PPC Driver_APB_PPCEXP0;
59 extern ARM_DRIVER_PPC Driver_APB_PPCEXP1;
60 extern ARM_DRIVER_PPC Driver_APB_PPCEXP2;
61
62 /* Define Peripherals NS address range for the platform */
63 #define PERIPHERALS_BASE_NS_START (0x40000000)
64 #define PERIPHERALS_BASE_NS_END (0x4FFFFFFF)
65
66 /* Enable system reset request for CPU 0 */
67 #define ENABLE_CPU0_SYSTEM_RESET_REQUEST (1U << 4U)
68
69 /* To write into AIRCR register, 0x5FA value must be write to the VECTKEY field,
70 * otherwise the processor ignores the write.
71 */
72 #define SCB_AIRCR_WRITE_MASK ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos))
73
74 struct platform_data_t tfm_peripheral_std_uart = {
75 UART1_BASE_S,
76 UART1_BASE_S + 0xFFF,
77 PPC_SP_APB_PPC_EXP2,
78 CMSDK_UART1_APB_PPC_POS
79 };
80
81 static ARM_DRIVER_PPC *const ppc_bank_drivers[] = {
82 0, /* AHB PPC0 */
83 0, /* Reserved */
84 0, /* Reserved */
85 0, /* Reserved */
86 &Driver_AHB_PPCEXP0, /* AHB PPCEXP0 */
87 0, /* AHB PPCEXP1 */
88 0, /* AHB PPCEXP2 */
89 0, /* AHB PPCEXP3 */
90 &Driver_APB_PPC0, /* APB PPC0 */
91 &Driver_APB_PPC1, /* APB PPC1 */
92 0, /* Reserved */
93 0, /* Reserved */
94 &Driver_APB_PPCEXP0, /* APB PPCEXP0 */
95 &Driver_APB_PPCEXP1, /* APB PPCEXP1 */
96 &Driver_APB_PPCEXP2, /* APB PPCEXP2 */
97 };
98
99 #define PPC_BANK_COUNT (sizeof(ppc_bank_drivers)/sizeof(ppc_bank_drivers[0]))
100
101 struct platform_data_t tfm_peripheral_timer0 = {
102 CMSDK_TIMER0_BASE_S,
103 CMSDK_TIMER1_BASE_S - 1,
104 PPC_SP_APB_PPC0,
105 CMSDK_TIMER0_APB_PPC_POS
106 };
107
enable_fault_handlers(void)108 enum tfm_plat_err_t enable_fault_handlers(void)
109 {
110 /* Explicitly set secure fault priority to the highest */
111 NVIC_SetPriority(SecureFault_IRQn, 0);
112
113 /* Enables BUS, MEM, USG and Secure faults */
114 SCB->SHCSR |= (SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk |
115 SCB_SHCSR_MEMFAULTENA_Msk | SCB_SHCSR_SECUREFAULTENA_Msk);
116 return TFM_PLAT_ERR_SUCCESS;
117 }
118
system_reset_cfg(void)119 enum tfm_plat_err_t system_reset_cfg(void)
120 {
121 struct sysctrl_t *sysctrl = (struct sysctrl_t *)CMSDK_SYSCTRL_BASE_S;
122 uint32_t reg_value = SCB->AIRCR;
123
124 /* Enable system reset request for CPU 0, to be triggered via
125 * NVIC_SystemReset function.
126 */
127 sysctrl->resetmask |= ENABLE_CPU0_SYSTEM_RESET_REQUEST;
128
129 /* Clear SCB_AIRCR_VECTKEY value */
130 reg_value &= ~(uint32_t)(SCB_AIRCR_VECTKEY_Msk);
131
132 /* Enable system reset request only to the secure world */
133 reg_value |= (uint32_t)(SCB_AIRCR_WRITE_MASK | SCB_AIRCR_SYSRESETREQS_Msk);
134
135 SCB->AIRCR = reg_value;
136
137 return TFM_PLAT_ERR_SUCCESS;
138 }
139
init_debug(void)140 enum tfm_plat_err_t init_debug(void)
141 {
142 volatile struct sysctrl_t *sys_ctrl =
143 (struct sysctrl_t *)CMSDK_SYSCTRL_BASE_S;
144
145 #if defined(DAUTH_NONE)
146 /* Set all the debug enable selector bits to 1 */
147 sys_ctrl->secdbgset = All_SEL_STATUS;
148 /* Set all the debug enable bits to 0 */
149 sys_ctrl->secdbgclr =
150 DBGEN_STATUS | NIDEN_STATUS | SPIDEN_STATUS | SPNIDEN_STATUS;
151 #elif defined(DAUTH_NS_ONLY)
152 /* Set all the debug enable selector bits to 1 */
153 sys_ctrl->secdbgset = All_SEL_STATUS;
154 /* Set the debug enable bits to 1 for NS, and 0 for S mode */
155 sys_ctrl->secdbgset = DBGEN_STATUS | NIDEN_STATUS;
156 sys_ctrl->secdbgclr = SPIDEN_STATUS | SPNIDEN_STATUS;
157 #elif defined(DAUTH_FULL)
158 /* Set all the debug enable selector bits to 1 */
159 sys_ctrl->secdbgset = All_SEL_STATUS;
160 /* Set all the debug enable bits to 1 */
161 sys_ctrl->secdbgset =
162 DBGEN_STATUS | NIDEN_STATUS | SPIDEN_STATUS | SPNIDEN_STATUS;
163 #else
164
165 #if !defined(DAUTH_CHIP_DEFAULT)
166 #error "No debug authentication setting is provided."
167 #endif
168
169 /* Set all the debug enable selector bits to 0 */
170 sys_ctrl->secdbgclr = All_SEL_STATUS;
171
172 /* No need to set any enable bits because the value depends on
173 * input signals.
174 */
175 #endif
176 return TFM_PLAT_ERR_SUCCESS;
177 }
178
179 /*--------------------- NVIC interrupt NS/S configuration --------------------*/
nvic_interrupt_target_state_cfg(void)180 enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void)
181 {
182 uint8_t i;
183
184 /* Target every interrupt to NS; unimplemented interrupts will be WI */
185 for (i = 0; i < (sizeof(NVIC->ITNS) / sizeof(NVIC->ITNS[0])); i++) {
186 NVIC->ITNS[i] = 0xFFFFFFFF;
187 }
188
189 /* Make sure that MPC and PPC are targeted to S state */
190 NVIC_ClearTargetState(MPC_IRQn);
191 NVIC_ClearTargetState(PPC_IRQn);
192
193 return TFM_PLAT_ERR_SUCCESS;
194 }
195
196 /*----------------- NVIC interrupt enabling for S peripherals ----------------*/
nvic_interrupt_enable(void)197 enum tfm_plat_err_t nvic_interrupt_enable(void)
198 {
199 int32_t ret = ARM_DRIVER_OK;
200 /* MPC interrupt enabling */
201 ret = Driver_QSPI_MPC.EnableInterrupt();
202 if (ret != ARM_DRIVER_OK) {
203 return TFM_PLAT_ERR_SYSTEM_ERR;
204 }
205 ret = Driver_ISRAM2_MPC.EnableInterrupt();
206 if (ret != ARM_DRIVER_OK) {
207 return TFM_PLAT_ERR_SYSTEM_ERR;
208 }
209 ret = Driver_ISRAM3_MPC.EnableInterrupt();
210 if (ret != ARM_DRIVER_OK) {
211 return TFM_PLAT_ERR_SYSTEM_ERR;
212 }
213 NVIC_EnableIRQ(MPC_IRQn);
214
215 /* PPC interrupt enabling */
216 /* Clear pending PPC interrupts */
217 /* In the PPC configuration function, we have used the Non-Secure
218 * Privilege Control Block to grant unprivilged NS access to some
219 * peripherals used by NS. That triggers a PPC0 exception as that
220 * register is meant for NS privileged access only. Clear it here
221 */
222 Driver_APB_PPC0.ClearInterrupt();
223
224 /* Enable PPC interrupts for APB PPC */
225 ret = Driver_APB_PPC0.EnableInterrupt();
226 if (ret != ARM_DRIVER_OK) {
227 return TFM_PLAT_ERR_SYSTEM_ERR;
228 }
229 ret = Driver_APB_PPC1.EnableInterrupt();
230 if (ret != ARM_DRIVER_OK) {
231 return TFM_PLAT_ERR_SYSTEM_ERR;
232 }
233 ret = Driver_APB_PPCEXP0.EnableInterrupt();
234 if (ret != ARM_DRIVER_OK) {
235 return TFM_PLAT_ERR_SYSTEM_ERR;
236 }
237 ret = Driver_APB_PPCEXP1.EnableInterrupt();
238 if (ret != ARM_DRIVER_OK) {
239 return TFM_PLAT_ERR_SYSTEM_ERR;
240 }
241 ret = Driver_APB_PPCEXP2.EnableInterrupt();
242 if (ret != ARM_DRIVER_OK) {
243 return TFM_PLAT_ERR_SYSTEM_ERR;
244 }
245
246 NVIC_EnableIRQ(PPC_IRQn);
247
248 return (enum tfm_plat_err_t) ARM_DRIVER_OK;
249 }
250
251 /*------------------- SAU/IDAU configuration functions -----------------------*/
sau_and_idau_cfg(void)252 void sau_and_idau_cfg(void)
253 {
254 struct spctrl_def *spctrl = CMSDK_SPCTRL;
255
256 /* Ensure all memory accesses are completed */
257 __DMB();
258
259 /* Enables SAU */
260 TZ_SAU_Enable();
261
262 /* Configures SAU regions to be non-secure */
263 SAU->RNR = 0U;
264 SAU->RBAR = (memory_regions.non_secure_partition_base
265 & SAU_RBAR_BADDR_Msk);
266 SAU->RLAR = (memory_regions.non_secure_partition_limit
267 & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk;
268
269 SAU->RNR = 1U;
270 SAU->RBAR = (NS_DATA_START & SAU_RBAR_BADDR_Msk);
271 SAU->RLAR = (NS_DATA_LIMIT & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk;
272
273 /* Configures veneers region to be non-secure callable */
274 SAU->RNR = 2U;
275 SAU->RBAR = (memory_regions.veneer_base & SAU_RBAR_BADDR_Msk);
276 SAU->RLAR = (memory_regions.veneer_limit & SAU_RLAR_LADDR_Msk)
277 | SAU_RLAR_ENABLE_Msk | SAU_RLAR_NSC_Msk;
278
279 /* Configure the peripherals space */
280 SAU->RNR = 3U;
281 SAU->RBAR = (PERIPHERALS_BASE_NS_START & SAU_RBAR_BADDR_Msk);
282 SAU->RLAR = (PERIPHERALS_BASE_NS_END & SAU_RLAR_LADDR_Msk)
283 | SAU_RLAR_ENABLE_Msk;
284 #ifdef BL2
285 /* Secondary image partition */
286 SAU->RNR = 4U;
287 /* TODO */
288 SAU->RBAR = (memory_regions.secondary_partition_base
289 & SAU_RBAR_BADDR_Msk);
290 SAU->RLAR = (memory_regions.secondary_partition_limit
291 & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk;
292 #endif /* BL2 */
293
294 /* Allows SAU to define the code region as a NSC */
295 spctrl->nsccfg |= NSCCFG_CODENSC;
296
297 /* Ensure the write is completed and flush pipeline */
298 __DSB();
299 __ISB();
300 }
301
302 /*------------------- Memory configuration functions -------------------------*/
mpc_init_cfg(void)303 enum tfm_plat_err_t mpc_init_cfg(void)
304 {
305 int32_t ret = ARM_DRIVER_OK;
306
307 ret = Driver_QSPI_MPC.Initialize();
308 if (ret != ARM_DRIVER_OK) {
309 return ret;
310 }
311
312 ret = Driver_QSPI_MPC.ConfigRegion(
313 memory_regions.non_secure_partition_base,
314 memory_regions.non_secure_partition_limit,
315 ARM_MPC_ATTR_NONSECURE);
316 if (ret != ARM_DRIVER_OK) {
317 return ret;
318 }
319 #ifdef BL2
320 ret = Driver_QSPI_MPC.ConfigRegion(
321 memory_regions.secondary_partition_base,
322 memory_regions.secondary_partition_limit,
323 ARM_MPC_ATTR_NONSECURE);
324 if (ret != ARM_DRIVER_OK) {
325 return ret;
326 }
327 #endif /* BL2 */
328
329 /* SPE uses the first 96kB (3 ISRAM banks) for data */
330 ret = Driver_ISRAM0_MPC.Initialize();
331 if (ret != ARM_DRIVER_OK) {
332 return ret;
333 }
334
335 ret = Driver_ISRAM0_MPC.ConfigRegion(
336 MPC_ISRAM0_RANGE_BASE_S,
337 MPC_ISRAM0_RANGE_LIMIT_S,
338 ARM_MPC_ATTR_SECURE);
339 if (ret != ARM_DRIVER_OK) {
340 return ret;
341 }
342
343 ret = Driver_ISRAM1_MPC.Initialize();
344 if (ret != ARM_DRIVER_OK) {
345 return ret;
346 }
347
348 ret = Driver_ISRAM1_MPC.ConfigRegion(
349 MPC_ISRAM1_RANGE_BASE_S,
350 MPC_ISRAM1_RANGE_LIMIT_S,
351 ARM_MPC_ATTR_SECURE);
352 if (ret != ARM_DRIVER_OK) {
353 return ret;
354 }
355
356 ret = Driver_ISRAM2_MPC.Initialize();
357 if (ret != ARM_DRIVER_OK) {
358 return ret;
359 }
360
361 ret = Driver_ISRAM2_MPC.ConfigRegion(
362 MPC_ISRAM2_RANGE_BASE_S,
363 MPC_ISRAM2_RANGE_LIMIT_S,
364 ARM_MPC_ATTR_SECURE);
365 if (ret != ARM_DRIVER_OK) {
366 return ret;
367 }
368
369 /* NSPE use the last 32KB (ISRAM 3) */
370 ret = Driver_ISRAM3_MPC.Initialize();
371 if (ret != ARM_DRIVER_OK) {
372 return ret;
373 }
374
375 ret = Driver_ISRAM3_MPC.ConfigRegion(
376 MPC_ISRAM3_RANGE_BASE_NS,
377 MPC_ISRAM3_RANGE_LIMIT_NS,
378 ARM_MPC_ATTR_NONSECURE);
379 if (ret != ARM_DRIVER_OK) {
380 return ret;
381 }
382
383 /* Lock down the MPC configuration */
384 ret = Driver_QSPI_MPC.LockDown();
385 if (ret != ARM_DRIVER_OK) {
386 return ret;
387 }
388
389 ret = Driver_ISRAM0_MPC.LockDown();
390 if (ret != ARM_DRIVER_OK) {
391 return ret;
392 }
393
394 ret = Driver_ISRAM1_MPC.LockDown();
395 if (ret != ARM_DRIVER_OK) {
396 return ret;
397 }
398
399 ret = Driver_ISRAM2_MPC.LockDown();
400 if (ret != ARM_DRIVER_OK) {
401 return ret;
402 }
403
404 ret = Driver_ISRAM3_MPC.LockDown();
405 if (ret != ARM_DRIVER_OK) {
406 return ret;
407 }
408
409 /* Add barriers to assure the MPC configuration is done before continue
410 * the execution.
411 */
412 __DSB();
413 __ISB();
414
415 return TFM_PLAT_ERR_SUCCESS;
416 }
417
mpc_revert_non_secure_to_secure_cfg(void)418 void mpc_revert_non_secure_to_secure_cfg(void)
419 {
420 Driver_ISRAM3_MPC.ConfigRegion(MPC_ISRAM3_RANGE_BASE_S,
421 MPC_ISRAM3_RANGE_LIMIT_S,
422 ARM_MPC_ATTR_SECURE);
423
424 Driver_QSPI_MPC.ConfigRegion(MPC_QSPI_RANGE_BASE_S,
425 MPC_QSPI_RANGE_LIMIT_S,
426 ARM_MPC_ATTR_SECURE);
427
428 /* Add barriers to assure the MPC configuration is done before continue
429 * the execution.
430 */
431 __DSB();
432 __ISB();
433 }
434
mpc_clear_irq(void)435 void mpc_clear_irq(void)
436 {
437 Driver_QSPI_MPC.ClearInterrupt();
438 Driver_ISRAM0_MPC.ClearInterrupt();
439 Driver_ISRAM1_MPC.ClearInterrupt();
440 Driver_ISRAM2_MPC.ClearInterrupt();
441 Driver_ISRAM3_MPC.ClearInterrupt();
442 }
443
444 /*------------------- PPC configuration functions -------------------------*/
ppc_init_cfg(void)445 enum tfm_plat_err_t ppc_init_cfg(void)
446 {
447 struct spctrl_def *spctrl = CMSDK_SPCTRL;
448 int32_t ret = ARM_DRIVER_OK;
449
450 /* Grant non-secure access to peripherals in the PPC0
451 * (timer0 and 1, dualtimer, watchdog, mhu 0 and 1)
452 */
453 ret = Driver_APB_PPC0.Initialize();
454 if (ret != ARM_DRIVER_OK) {
455 return ret;
456 }
457
458 ret = Driver_APB_PPC0.ConfigPeriph(CMSDK_TIMER0_APB_PPC_POS,
459 ARM_PPC_NONSECURE_ONLY,
460 ARM_PPC_PRIV_ONLY);
461 if (ret != ARM_DRIVER_OK) {
462 return ret;
463 }
464 ret = Driver_APB_PPC0.ConfigPeriph(CMSDK_TIMER1_APB_PPC_POS,
465 ARM_PPC_NONSECURE_ONLY,
466 ARM_PPC_PRIV_ONLY);
467 if (ret != ARM_DRIVER_OK) {
468 return ret;
469 }
470 ret = Driver_APB_PPC0.ConfigPeriph(CMSDK_DTIMER_APB_PPC_POS,
471 ARM_PPC_NONSECURE_ONLY,
472 ARM_PPC_PRIV_ONLY);
473 if (ret != ARM_DRIVER_OK) {
474 return ret;
475 }
476 ret = Driver_APB_PPC0.ConfigPeriph(CMSDK_MHU0_APB_PPC_POS,
477 ARM_PPC_NONSECURE_ONLY,
478 ARM_PPC_PRIV_ONLY);
479 if (ret != ARM_DRIVER_OK) {
480 return ret;
481 }
482 ret = Driver_APB_PPC0.ConfigPeriph(CMSDK_MHU0_APB_PPC_POS,
483 ARM_PPC_NONSECURE_ONLY,
484 ARM_PPC_PRIV_ONLY);
485
486 ret = Driver_APB_PPC1.Initialize();
487 if (ret != ARM_DRIVER_OK) {
488 return ret;
489 }
490
491 /* No peripherals are configured on APB PPC EXP0 but device needs to be
492 * initialialized so that the interrupt can be enabled later.
493 */
494 ret = Driver_APB_PPCEXP0.Initialize();
495 if (ret != ARM_DRIVER_OK) {
496 return ret;
497 }
498
499 /* Grant non-secure access for APB peripherals on EXP1 */
500 ret = Driver_APB_PPCEXP1.Initialize();
501 if (ret != ARM_DRIVER_OK) {
502 return ret;
503 }
504 ret = Driver_APB_PPCEXP1.ConfigPeriph(CMSDK_I2C0_APB_PPC_POS,
505 ARM_PPC_NONSECURE_ONLY,
506 ARM_PPC_PRIV_ONLY);
507 if (ret != ARM_DRIVER_OK) {
508 return ret;
509 }
510 ret = Driver_APB_PPCEXP1.ConfigPeriph(CMSDK_I2C1_APB_PPC_POS,
511 ARM_PPC_NONSECURE_ONLY,
512 ARM_PPC_PRIV_ONLY);
513 if (ret != ARM_DRIVER_OK) {
514 return ret;
515 }
516 ret = Driver_APB_PPCEXP1.ConfigPeriph(CMSDK_SPI0_APB_PPC_POS,
517 ARM_PPC_NONSECURE_ONLY,
518 ARM_PPC_PRIV_ONLY);
519 if (ret != ARM_DRIVER_OK) {
520 return ret;
521 }
522 ret = Driver_APB_PPCEXP1.ConfigPeriph(CMSDK_SPI1_APB_PPC_POS,
523 ARM_PPC_NONSECURE_ONLY,
524 ARM_PPC_PRIV_ONLY);
525 if (ret != ARM_DRIVER_OK) {
526 return ret;
527 }
528 ret = Driver_APB_PPCEXP1.ConfigPeriph(CMSDK_SPI2_APB_PPC_POS,
529 ARM_PPC_NONSECURE_ONLY,
530 ARM_PPC_PRIV_ONLY);
531 if (ret != ARM_DRIVER_OK) {
532 return ret;
533 }
534 ret = Driver_APB_PPCEXP1.ConfigPeriph(CMSDK_I2C2_APB_PPC_POS,
535 ARM_PPC_NONSECURE_ONLY,
536 ARM_PPC_PRIV_ONLY);
537 if (ret != ARM_DRIVER_OK) {
538 return ret;
539 }
540 ret = Driver_APB_PPCEXP1.ConfigPeriph(CMSDK_I2C3_APB_PPC_POS,
541 ARM_PPC_NONSECURE_ONLY,
542 ARM_PPC_PRIV_ONLY);
543 if (ret != ARM_DRIVER_OK) {
544 return ret;
545 }
546 ret = Driver_APB_PPCEXP1.ConfigPeriph(CMSDK_I2C4_APB_PPC_POS,
547 ARM_PPC_NONSECURE_ONLY,
548 ARM_PPC_PRIV_ONLY);
549 if (ret != ARM_DRIVER_OK) {
550 return ret;
551 }
552
553 /* Grant non-secure access for APB peripherals on EXP2 */
554 ret = Driver_APB_PPCEXP2.Initialize();
555 if (ret != ARM_DRIVER_OK) {
556 return ret;
557 }
558 ret = Driver_APB_PPCEXP2.ConfigPeriph(CMSDK_FPGA_SCC_PPC_POS,
559 ARM_PPC_NONSECURE_ONLY,
560 ARM_PPC_PRIV_ONLY);
561 if (ret != ARM_DRIVER_OK) {
562 return ret;
563 }
564 ret = Driver_APB_PPCEXP2.ConfigPeriph(CMSDK_FPGA_AUDIO_PPC_POS,
565 ARM_PPC_NONSECURE_ONLY,
566 ARM_PPC_PRIV_ONLY);
567 if (ret != ARM_DRIVER_OK) {
568 return ret;
569 }
570 ret = Driver_APB_PPCEXP2.ConfigPeriph(CMSDK_FPGA_IO_PPC_POS,
571 ARM_PPC_NONSECURE_ONLY,
572 ARM_PPC_PRIV_AND_NONPRIV);
573 if (ret != ARM_DRIVER_OK) {
574 return ret;
575 }
576 ret = Driver_APB_PPCEXP2.ConfigPeriph(CMSDK_UART0_APB_PPC_POS,
577 ARM_PPC_NONSECURE_ONLY,
578 ARM_PPC_PRIV_ONLY);
579 if (ret != ARM_DRIVER_OK) {
580 return ret;
581 }
582 ret = Driver_APB_PPCEXP2.ConfigPeriph(CMSDK_UART1_APB_PPC_POS,
583 ARM_PPC_NONSECURE_ONLY,
584 ARM_PPC_PRIV_ONLY);
585 if (ret != ARM_DRIVER_OK) {
586 return ret;
587 }
588 ret = Driver_APB_PPCEXP2.ConfigPeriph(CMSDK_UART2_APB_PPC_POS,
589 ARM_PPC_NONSECURE_ONLY,
590 ARM_PPC_PRIV_ONLY);
591 if (ret != ARM_DRIVER_OK) {
592 return ret;
593 }
594 ret = Driver_APB_PPCEXP2.ConfigPeriph(CMSDK_UART3_APB_PPC_POS,
595 ARM_PPC_NONSECURE_ONLY,
596 ARM_PPC_PRIV_ONLY);
597 if (ret != ARM_DRIVER_OK) {
598 return ret;
599 }
600 ret = Driver_APB_PPCEXP2.ConfigPeriph(CMSDK_UART4_APB_PPC_POS,
601 ARM_PPC_NONSECURE_ONLY,
602 ARM_PPC_PRIV_ONLY);
603 if (ret != ARM_DRIVER_OK) {
604 return ret;
605 }
606 ret = Driver_APB_PPCEXP2.ConfigPeriph(CMSDK_UART5_APB_PPC_POS,
607 ARM_PPC_NONSECURE_ONLY,
608 ARM_PPC_PRIV_ONLY);
609 if (ret != ARM_DRIVER_OK) {
610 return ret;
611 }
612 ret = Driver_APB_PPCEXP2.ConfigPeriph(CMSDK_CLCD_APB_PPC_POS,
613 ARM_PPC_NONSECURE_ONLY,
614 ARM_PPC_PRIV_ONLY);
615 if (ret != ARM_DRIVER_OK) {
616 return ret;
617 }
618 ret = Driver_APB_PPCEXP2.ConfigPeriph(CMSDK_RTC_APB_PPC_POS,
619 ARM_PPC_NONSECURE_ONLY,
620 ARM_PPC_PRIV_ONLY);
621 if (ret != ARM_DRIVER_OK) {
622 return ret;
623 }
624
625 /*
626 * Grant non-secure access to all peripherals on AHB EXP0:
627 * Make sure that all possible peripherals are enabled by default
628 */
629 ret = Driver_AHB_PPCEXP0.Initialize();
630 if (ret != ARM_DRIVER_OK) {
631 return ret;
632 }
633 ret = Driver_AHB_PPCEXP0.ConfigPeriph(CMSDK_GPIO0_PPC_POS,
634 ARM_PPC_NONSECURE_ONLY,
635 ARM_PPC_PRIV_ONLY);
636 if (ret != ARM_DRIVER_OK) {
637 return ret;
638 }
639 ret = Driver_AHB_PPCEXP0.ConfigPeriph(CMSDK_GPIO1_PPC_POS,
640 ARM_PPC_NONSECURE_ONLY,
641 ARM_PPC_PRIV_ONLY);
642 if (ret != ARM_DRIVER_OK) {
643 return ret;
644 }
645 ret = Driver_AHB_PPCEXP0.ConfigPeriph(CMSDK_GPIO2_PPC_POS,
646 ARM_PPC_NONSECURE_ONLY,
647 ARM_PPC_PRIV_ONLY);
648 if (ret != ARM_DRIVER_OK) {
649 return ret;
650 }
651 ret = Driver_AHB_PPCEXP0.ConfigPeriph(CMSDK_GPIO3_PPC_POS,
652 ARM_PPC_NONSECURE_ONLY,
653 ARM_PPC_PRIV_ONLY);
654 if (ret != ARM_DRIVER_OK) {
655 return ret;
656 }
657 ret = Driver_AHB_PPCEXP0.ConfigPeriph(CMSDK_USB_ETHERNET_PPC_POS,
658 ARM_PPC_NONSECURE_ONLY,
659 ARM_PPC_PRIV_ONLY);
660 if (ret != ARM_DRIVER_OK) {
661 return ret;
662 }
663 ret = Driver_AHB_PPCEXP0.ConfigPeriph(CMSDK_USER0_PPC_POS,
664 ARM_PPC_NONSECURE_ONLY,
665 ARM_PPC_PRIV_ONLY);
666 if (ret != ARM_DRIVER_OK) {
667 return ret;
668 }
669 ret = Driver_AHB_PPCEXP0.ConfigPeriph(CMSDK_USER1_PPC_POS,
670 ARM_PPC_NONSECURE_ONLY,
671 ARM_PPC_PRIV_ONLY);
672 if (ret != ARM_DRIVER_OK) {
673 return ret;
674 }
675 ret = Driver_AHB_PPCEXP0.ConfigPeriph(CMSDK_USER2_PPC_POS,
676 ARM_PPC_NONSECURE_ONLY,
677 ARM_PPC_PRIV_ONLY);
678 if (ret != ARM_DRIVER_OK) {
679 return ret;
680 }
681
682 /*
683 * Configure the response to a security violation as a
684 * bus error instead of RAZ/WI
685 */
686 spctrl->secrespcfg |= CMSDK_SECRESPCFG_BUS_ERR_MASK;
687
688 return TFM_PLAT_ERR_SUCCESS;
689 }
690
ppc_configure_to_secure(ppc_bank_t bank,uint32_t pos)691 void ppc_configure_to_secure(ppc_bank_t bank, uint32_t pos)
692 {
693 ARM_DRIVER_PPC *ppc_driver;
694
695 if (bank >= PPC_BANK_COUNT) {
696 return;
697 }
698
699 ppc_driver = ppc_bank_drivers[bank];
700 if (ppc_driver) {
701 ppc_driver->ConfigPeriph(pos, ARM_PPC_SECURE_ONLY,
702 ARM_PPC_PRIV_ONLY);
703 }
704 }
705
ppc_en_secure_unpriv(ppc_bank_t bank,uint32_t pos)706 void ppc_en_secure_unpriv(ppc_bank_t bank, uint32_t pos)
707 {
708 ARM_DRIVER_PPC *ppc_driver;
709
710 if (bank >= PPC_BANK_COUNT) {
711 return;
712 }
713
714 ppc_driver = ppc_bank_drivers[bank];
715 if (ppc_driver) {
716 ppc_driver->ConfigPeriph(pos, ARM_PPC_SECURE_ONLY,
717 ARM_PPC_PRIV_AND_NONPRIV);
718 }
719 }
720
ppc_clr_secure_unpriv(ppc_bank_t bank,uint32_t pos)721 void ppc_clr_secure_unpriv(ppc_bank_t bank, uint32_t pos)
722 {
723 ppc_configure_to_secure(bank, pos);
724 }
725
ppc_clear_irq(void)726 void ppc_clear_irq(void)
727 {
728 Driver_AHB_PPCEXP0.ClearInterrupt();
729 Driver_APB_PPC0.ClearInterrupt();
730 Driver_APB_PPC1.ClearInterrupt();
731 Driver_APB_PPCEXP0.ClearInterrupt();
732 Driver_APB_PPCEXP1.ClearInterrupt();
733 Driver_APB_PPCEXP2.ClearInterrupt();
734 }
735
