1 /* 2 * Copyright (c) 2019-2023 Arm Limited. All rights reserved. 3 * 4 * Licensed under the Apache License Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing software 11 * distributed under the License is distributed on an "AS IS" BASIS 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 /** 18 * \file device_definition.c 19 * \brief This file defines exports the structures based on the peripheral 20 * definitions from device_cfg.h. 21 * This file is meant to be used as a helper for baremetal 22 * applications and/or as an example of how to configure the generic 23 * driver structures. 24 */ 25 26 #include "device_definition.h" 27 #include "platform_base_address.h" 28 #include "tfm_plat_defs.h" 29 30 /* UART CMSDK driver structures */ 31 #ifdef UART0_CMSDK_S 32 static const struct uart_cmsdk_dev_cfg_t UART0_CMSDK_DEV_CFG_S = { 33 .base = UART0_BASE_S, 34 .default_baudrate = DEFAULT_UART_BAUDRATE 35 }; 36 static struct uart_cmsdk_dev_data_t UART0_CMSDK_DEV_DATA_S = { 37 .state = 0, 38 .system_clk = 0, 39 .baudrate = 0 40 }; 41 struct uart_cmsdk_dev_t ARM_UART0_DEV_S = { 42 &(UART0_CMSDK_DEV_CFG_S), 43 &(UART0_CMSDK_DEV_DATA_S) 44 }; 45 #endif 46 #ifdef UART0_CMSDK_NS 47 static const struct uart_cmsdk_dev_cfg_t UART0_CMSDK_DEV_CFG_NS = { 48 .base = UART0_BASE_NS, 49 .default_baudrate = DEFAULT_UART_BAUDRATE 50 }; 51 static struct uart_cmsdk_dev_data_t UART0_CMSDK_DEV_DATA_NS = { 52 .state = 0, 53 .system_clk = 0, 54 .baudrate = 0 55 }; 56 struct uart_cmsdk_dev_t ARM_UART0_DEV_NS = { 57 &(UART0_CMSDK_DEV_CFG_NS), 58 &(UART0_CMSDK_DEV_DATA_NS) 59 }; 60 #endif 61 62 #ifdef UART1_CMSDK_S 63 static const struct uart_cmsdk_dev_cfg_t UART1_CMSDK_DEV_CFG_S = { 64 .base = UART1_BASE_S, 65 .default_baudrate = DEFAULT_UART_BAUDRATE 66 }; 67 static struct uart_cmsdk_dev_data_t UART1_CMSDK_DEV_DATA_S = { 68 .state = 0, 69 .system_clk = 0, 70 .baudrate = 0 71 }; 72 struct uart_cmsdk_dev_t ARM_UART1_DEV_S = { 73 &(UART1_CMSDK_DEV_CFG_S), 74 &(UART1_CMSDK_DEV_DATA_S) 75 }; 76 #endif 77 #ifdef UART1_CMSDK_NS 78 static const struct uart_cmsdk_dev_cfg_t UART1_CMSDK_DEV_CFG_NS = { 79 .base = UART1_BASE_NS, 80 .default_baudrate = DEFAULT_UART_BAUDRATE 81 }; 82 static struct uart_cmsdk_dev_data_t UART1_CMSDK_DEV_DATA_NS = { 83 .state = 0, 84 .system_clk = 0, 85 .baudrate = 0 86 }; 87 struct uart_cmsdk_dev_t ARM_UART1_DEV_NS = { 88 &(UART1_CMSDK_DEV_CFG_NS), 89 &(UART1_CMSDK_DEV_DATA_NS) 90 }; 91 #endif 92 93 #ifdef UART2_CMSDK_S 94 static const struct uart_cmsdk_dev_cfg_t UART2_CMSDK_DEV_CFG_S = { 95 .base = UART2_BASE_S, 96 .default_baudrate = DEFAULT_UART_BAUDRATE 97 }; 98 static struct uart_cmsdk_dev_data_t UART2_CMSDK_DEV_DATA_S = { 99 .state = 0, 100 .system_clk = 0, 101 .baudrate = 0 102 }; 103 struct uart_cmsdk_dev_t ARM_UART2_DEV_S = { 104 &(UART2_CMSDK_DEV_CFG_S), 105 &(UART2_CMSDK_DEV_DATA_S) 106 }; 107 #endif 108 #ifdef UART2_CMSDK_NS 109 static const struct uart_cmsdk_dev_cfg_t UART2_CMSDK_DEV_CFG_NS = { 110 .base = UART2_BASE_NS, 111 .default_baudrate = DEFAULT_UART_BAUDRATE 112 }; 113 static struct uart_cmsdk_dev_data_t UART2_CMSDK_DEV_DATA_NS = { 114 .state = 0, 115 .system_clk = 0, 116 .baudrate = 0 117 }; 118 struct uart_cmsdk_dev_t ARM_UART2_DEV_NS = { 119 &(UART2_CMSDK_DEV_CFG_NS), 120 &(UART2_CMSDK_DEV_DATA_NS) 121 }; 122 #endif 123 124 #ifdef UART3_CMSDK_S 125 static const struct uart_cmsdk_dev_cfg_t UART3_CMSDK_DEV_CFG_S = { 126 .base = UART3_BASE_S, 127 .default_baudrate = DEFAULT_UART_BAUDRATE 128 }; 129 static struct uart_cmsdk_dev_data_t UART3_CMSDK_DEV_DATA_S = { 130 .state = 0, 131 .system_clk = 0, 132 .baudrate = 0 133 }; 134 struct uart_cmsdk_dev_t ARM_UART3_DEV_S = { 135 &(UART3_CMSDK_DEV_CFG_S), 136 &(UART3_CMSDK_DEV_DATA_S) 137 }; 138 #endif 139 #ifdef UART3_CMSDK_NS 140 static const struct uart_cmsdk_dev_cfg_t UART3_CMSDK_DEV_CFG_NS = { 141 .base = UART3_BASE_NS, 142 .default_baudrate = DEFAULT_UART_BAUDRATE 143 }; 144 static struct uart_cmsdk_dev_data_t UART3_CMSDK_DEV_DATA_NS = { 145 .state = 0, 146 .system_clk = 0, 147 .baudrate = 0 148 }; 149 struct uart_cmsdk_dev_t ARM_UART3_DEV_NS = { 150 &(UART3_CMSDK_DEV_CFG_NS), 151 &(UART3_CMSDK_DEV_DATA_NS) 152 }; 153 #endif 154 155 #ifdef UART4_CMSDK_S 156 static const struct uart_cmsdk_dev_cfg_t UART4_CMSDK_DEV_CFG_S = { 157 .base = UART4_BASE_S, 158 .default_baudrate = DEFAULT_UART_BAUDRATE 159 }; 160 static struct uart_cmsdk_dev_data_t UART4_CMSDK_DEV_DATA_S = { 161 .state = 0, 162 .system_clk = 0, 163 .baudrate = 0 164 }; 165 struct uart_cmsdk_dev_t ARM_UART4_DEV_S = { 166 &(UART4_CMSDK_DEV_CFG_S), 167 &(UART4_CMSDK_DEV_DATA_S) 168 }; 169 #endif 170 #ifdef UART4_CMSDK_NS 171 static const struct uart_cmsdk_dev_cfg_t UART4_CMSDK_DEV_CFG_NS = { 172 .base = UART4_BASE_NS, 173 .default_baudrate = DEFAULT_UART_BAUDRATE 174 }; 175 static struct uart_cmsdk_dev_data_t UART4_CMSDK_DEV_DATA_NS = { 176 .state = 0, 177 .system_clk = 0, 178 .baudrate = 0 179 }; 180 struct uart_cmsdk_dev_t ARM_UART4_DEV_NS = { 181 &(UART4_CMSDK_DEV_CFG_NS), 182 &(UART4_CMSDK_DEV_DATA_NS) 183 }; 184 #endif 185 186 #ifdef UART5_CMSDK_S 187 static const struct uart_cmsdk_dev_cfg_t UART5_CMSDK_DEV_CFG_S = { 188 .base = UART5_BASE_S, 189 .default_baudrate = DEFAULT_UART_BAUDRATE 190 }; 191 static struct uart_cmsdk_dev_data_t UART5_CMSDK_DEV_DATA_S = { 192 .state = 0, 193 .system_clk = 0, 194 .baudrate = 0 195 }; 196 struct uart_cmsdk_dev_t ARM_UART5_DEV_S = { 197 &(UART5_CMSDK_DEV_CFG_S), 198 &(UART5_CMSDK_DEV_DATA_S) 199 }; 200 #endif 201 #ifdef UART5_CMSDK_NS 202 static const struct uart_cmsdk_dev_cfg_t UART5_CMSDK_DEV_CFG_NS = { 203 .base = UART5_BASE_NS, 204 .default_baudrate = DEFAULT_UART_BAUDRATE 205 }; 206 static struct uart_cmsdk_dev_data_t UART5_CMSDK_DEV_DATA_NS = { 207 .state = 0, 208 .system_clk = 0, 209 .baudrate = 0 210 }; 211 struct uart_cmsdk_dev_t ARM_UART5_DEV_NS = { 212 &(UART5_CMSDK_DEV_CFG_NS), 213 &(UART5_CMSDK_DEV_DATA_NS) 214 }; 215 #endif 216 217 /* ARM PPC SIE 200 driver structures */ 218 #ifdef AHB_PPC0_S 219 static struct ppc_sse200_dev_cfg_t AHB_PPC0_DEV_CFG_S = { 220 .spctrl_base = CMSDK_SPCTRL_BASE_S, 221 .nspctrl_base = CMSDK_NSPCTRL_BASE_NS 222 }; 223 static struct ppc_sse200_dev_data_t AHB_PPC0_DEV_DATA_S = { 224 .p_ns_ppc = 0, 225 .p_sp_ppc = 0, 226 .p_nsp_ppc = 0, 227 .int_bit_mask = 0, 228 .state = 0 229 }; 230 struct ppc_sse200_dev_t AHB_PPC0_DEV_S = { 231 &AHB_PPC0_DEV_CFG_S, 232 &AHB_PPC0_DEV_DATA_S 233 }; 234 #endif 235 236 #ifdef AHB_PPCEXP0_S 237 static struct ppc_sse200_dev_cfg_t AHB_PPCEXP0_DEV_CFG_S = { 238 .spctrl_base = CMSDK_SPCTRL_BASE_S, 239 .nspctrl_base = CMSDK_NSPCTRL_BASE_NS 240 }; 241 static struct ppc_sse200_dev_data_t AHB_PPCEXP0_DEV_DATA_S = { 242 .p_ns_ppc = 0, 243 .p_sp_ppc = 0, 244 .p_nsp_ppc = 0, 245 .int_bit_mask = 0, 246 .state = 0 247 }; 248 struct ppc_sse200_dev_t AHB_PPCEXP0_DEV_S = { 249 &AHB_PPCEXP0_DEV_CFG_S, 250 &AHB_PPCEXP0_DEV_DATA_S 251 }; 252 #endif 253 254 #ifdef APB_PPC0_S 255 static struct ppc_sse200_dev_cfg_t APB_PPC0_DEV_CFG_S = { 256 .spctrl_base = CMSDK_SPCTRL_BASE_S, 257 .nspctrl_base = CMSDK_NSPCTRL_BASE_NS 258 }; 259 static struct ppc_sse200_dev_data_t APB_PPC0_DEV_DATA_S = { 260 .p_ns_ppc = 0, 261 .p_sp_ppc = 0, 262 .p_nsp_ppc = 0, 263 .int_bit_mask = 0, 264 .state = 0 265 }; 266 struct ppc_sse200_dev_t APB_PPC0_DEV_S = { 267 &APB_PPC0_DEV_CFG_S, 268 &APB_PPC0_DEV_DATA_S 269 }; 270 #endif 271 272 #ifdef APB_PPC1_S 273 static struct ppc_sse200_dev_cfg_t APB_PPC1_DEV_CFG_S = { 274 .spctrl_base = CMSDK_SPCTRL_BASE_S, 275 .nspctrl_base = CMSDK_NSPCTRL_BASE_NS 276 }; 277 static struct ppc_sse200_dev_data_t APB_PPC1_DEV_DATA_S = { 278 .p_ns_ppc = 0, 279 .p_sp_ppc = 0, 280 .p_nsp_ppc = 0, 281 .int_bit_mask = 0, 282 .state = 0 283 }; 284 struct ppc_sse200_dev_t APB_PPC1_DEV_S = { 285 &APB_PPC1_DEV_CFG_S, 286 &APB_PPC1_DEV_DATA_S 287 }; 288 #endif 289 290 #ifdef APB_PPCEXP0_S 291 static struct ppc_sse200_dev_cfg_t APB_PPCEXP0_DEV_CFG_S = { 292 .spctrl_base = CMSDK_SPCTRL_BASE_S, 293 .nspctrl_base = CMSDK_NSPCTRL_BASE_NS 294 }; 295 static struct ppc_sse200_dev_data_t APB_PPCEXP0_DEV_DATA_S = { 296 .p_ns_ppc = 0, 297 .p_sp_ppc = 0, 298 .p_nsp_ppc = 0, 299 .int_bit_mask = 0, 300 .state = 0 301 }; 302 struct ppc_sse200_dev_t APB_PPCEXP0_DEV_S = { 303 &APB_PPCEXP0_DEV_CFG_S, 304 &APB_PPCEXP0_DEV_DATA_S 305 }; 306 #endif 307 308 #ifdef APB_PPCEXP1_S 309 static struct ppc_sse200_dev_cfg_t APB_PPCEXP1_DEV_CFG = { 310 .spctrl_base = CMSDK_SPCTRL_BASE_S, 311 .nspctrl_base = CMSDK_NSPCTRL_BASE_NS 312 }; 313 static struct ppc_sse200_dev_data_t APB_PPCEXP1_DEV_DATA_S = { 314 .p_ns_ppc = 0, 315 .p_sp_ppc = 0, 316 .p_nsp_ppc = 0, 317 .int_bit_mask = 0, 318 .state = 0 319 }; 320 struct ppc_sse200_dev_t APB_PPCEXP1_DEV_S = { 321 &APB_PPCEXP1_DEV_CFG, 322 &APB_PPCEXP1_DEV_DATA_S 323 }; 324 #endif 325 326 #ifdef APB_PPCEXP2_S 327 static struct ppc_sse200_dev_cfg_t APB_PPCEXP2_DEV_CFG = { 328 .spctrl_base = CMSDK_SPCTRL_BASE_S, 329 .nspctrl_base = CMSDK_NSPCTRL_BASE_NS 330 }; 331 static struct ppc_sse200_dev_data_t APB_PPCEXP2_DEV_DATA_S = { 332 .p_ns_ppc = 0, 333 .p_sp_ppc = 0, 334 .p_nsp_ppc = 0, 335 .int_bit_mask = 0, 336 .state = 0 337 }; 338 struct ppc_sse200_dev_t APB_PPCEXP2_DEV_S = { 339 &APB_PPCEXP2_DEV_CFG, 340 &APB_PPCEXP2_DEV_DATA_S 341 }; 342 #endif 343 344 /* CMSDK Timer driver structures */ 345 #ifdef CMSDK_TIMER0_S 346 static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER0_DEV_CFG_S 347 #ifdef TFM_PARTITION_SLIH_TEST 348 TFM_LINK_SET_RO_IN_PARTITION_SECTION("TFM_SP_SLIH_TEST", "APP-ROT") 349 #endif 350 = { 351 .base = CMSDK_TIMER0_BASE_S 352 }; 353 static struct timer_cmsdk_dev_data_t CMSDK_TIMER0_DEV_DATA_S 354 #ifdef TFM_PARTITION_SLIH_TEST 355 TFM_LINK_SET_RW_IN_PARTITION_SECTION("TFM_SP_SLIH_TEST", "APP-ROT") 356 #endif 357 = { 358 .is_initialized = 0 359 }; 360 struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_S 361 #ifdef TFM_PARTITION_SLIH_TEST 362 TFM_LINK_SET_RW_IN_PARTITION_SECTION("TFM_SP_SLIH_TEST", "APP-ROT") 363 #endif 364 = { 365 &(CMSDK_TIMER0_DEV_CFG_S), 366 &(CMSDK_TIMER0_DEV_DATA_S) 367 }; 368 #endif 369 #ifdef CMSDK_TIMER0_NS 370 static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER0_DEV_CFG_NS = { 371 .base = CMSDK_TIMER0_BASE_NS 372 }; 373 static struct timer_cmsdk_dev_data_t CMSDK_TIMER0_DEV_DATA_NS = { 374 .is_initialized = 0 375 }; 376 struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_NS = { 377 &(CMSDK_TIMER0_DEV_CFG_NS), 378 &(CMSDK_TIMER0_DEV_DATA_NS) 379 }; 380 #endif 381 382 #ifdef CMSDK_TIMER1_S 383 static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER1_DEV_CFG_S = { 384 .base = CMSDK_TIMER1_BASE_S 385 }; 386 static struct timer_cmsdk_dev_data_t CMSDK_TIMER1_DEV_DATA_S = { 387 .is_initialized = 0 388 }; 389 struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_S = { 390 &(CMSDK_TIMER1_DEV_CFG_S), 391 &(CMSDK_TIMER1_DEV_DATA_S) 392 }; 393 #endif 394 #ifdef CMSDK_TIMER1_NS 395 static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER1_DEV_CFG_NS = { 396 .base = CMSDK_TIMER1_BASE_NS 397 }; 398 static struct timer_cmsdk_dev_data_t CMSDK_TIMER1_DEV_DATA_NS = { 399 .is_initialized = 0 400 }; 401 struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_NS = { 402 &(CMSDK_TIMER1_DEV_CFG_NS), 403 &(CMSDK_TIMER1_DEV_DATA_NS) 404 }; 405 #endif 406 407 /* ARM MPC SSE 200 driver structures */ 408 #ifdef MPC_ISRAM0_S 409 static const struct mpc_sie_memory_range_t MPC_ISRAM0_RANGE_S = { 410 .base = MPC_ISRAM0_RANGE_BASE_S, 411 .limit = MPC_ISRAM0_RANGE_LIMIT_S, 412 .range_offset = 0, 413 .attr = MPC_SIE_SEC_ATTR_SECURE 414 }; 415 416 static const struct mpc_sie_memory_range_t MPC_ISRAM0_RANGE_NS = { 417 .base = MPC_ISRAM0_RANGE_BASE_NS, 418 .limit = MPC_ISRAM0_RANGE_LIMIT_NS, 419 .range_offset = 0, 420 .attr = MPC_SIE_SEC_ATTR_NONSECURE 421 }; 422 423 #define MPC_ISRAM0_RANGE_LIST_LEN 2u 424 static const struct mpc_sie_memory_range_t* 425 MPC_ISRAM0_RANGE_LIST[MPC_ISRAM0_RANGE_LIST_LEN] = { 426 &MPC_ISRAM0_RANGE_S, 427 &MPC_ISRAM0_RANGE_NS 428 }; 429 430 static struct mpc_sie_dev_cfg_t MPC_ISRAM0_DEV_CFG_S = { 431 .base = MPC_ISRAM0_BASE_S, 432 .range_list = MPC_ISRAM0_RANGE_LIST, 433 .nbr_of_ranges = MPC_ISRAM0_RANGE_LIST_LEN}; 434 static struct mpc_sie_dev_data_t MPC_ISRAM0_DEV_DATA_S = { 435 .is_initialized = false}; 436 437 struct mpc_sie_dev_t MPC_ISRAM0_DEV_S = { 438 &(MPC_ISRAM0_DEV_CFG_S), 439 &(MPC_ISRAM0_DEV_DATA_S) 440 }; 441 #endif 442 443 #ifdef MPC_ISRAM1_S 444 static const struct mpc_sie_memory_range_t MPC_ISRAM1_RANGE_S = { 445 .base = MPC_ISRAM1_RANGE_BASE_S, 446 .limit = MPC_ISRAM1_RANGE_LIMIT_S, 447 .range_offset = 0, 448 .attr = MPC_SIE_SEC_ATTR_SECURE 449 }; 450 451 static const struct mpc_sie_memory_range_t MPC_ISRAM1_RANGE_NS = { 452 .base = MPC_ISRAM1_RANGE_BASE_NS, 453 .limit = MPC_ISRAM1_RANGE_LIMIT_NS, 454 .range_offset = 0, 455 .attr = MPC_SIE_SEC_ATTR_NONSECURE 456 }; 457 458 #define MPC_ISRAM1_RANGE_LIST_LEN 2u 459 static const struct mpc_sie_memory_range_t* 460 MPC_ISRAM1_RANGE_LIST[MPC_ISRAM1_RANGE_LIST_LEN] = { 461 &MPC_ISRAM1_RANGE_S, 462 &MPC_ISRAM1_RANGE_NS 463 }; 464 465 static struct mpc_sie_dev_cfg_t MPC_ISRAM1_DEV_CFG_S = { 466 .base = MPC_ISRAM1_BASE_S, 467 .range_list = MPC_ISRAM1_RANGE_LIST, 468 .nbr_of_ranges = MPC_ISRAM1_RANGE_LIST_LEN}; 469 static struct mpc_sie_dev_data_t MPC_ISRAM1_DEV_DATA_S = { 470 .is_initialized = false}; 471 472 struct mpc_sie_dev_t MPC_ISRAM1_DEV_S = { 473 &(MPC_ISRAM1_DEV_CFG_S), 474 &(MPC_ISRAM1_DEV_DATA_S) 475 }; 476 #endif 477 478 #ifdef MPC_ISRAM2_S 479 static const struct mpc_sie_memory_range_t MPC_ISRAM2_RANGE_S = { 480 .base = MPC_ISRAM2_RANGE_BASE_S, 481 .limit = MPC_ISRAM2_RANGE_LIMIT_S, 482 .range_offset = 0, 483 .attr = MPC_SIE_SEC_ATTR_SECURE 484 }; 485 486 static const struct mpc_sie_memory_range_t MPC_ISRAM2_RANGE_NS = { 487 .base = MPC_ISRAM2_RANGE_BASE_NS, 488 .limit = MPC_ISRAM2_RANGE_LIMIT_NS, 489 .range_offset = 0, 490 .attr = MPC_SIE_SEC_ATTR_NONSECURE 491 }; 492 493 #define MPC_ISRAM2_RANGE_LIST_LEN 2u 494 static const struct mpc_sie_memory_range_t* 495 MPC_ISRAM2_RANGE_LIST[MPC_ISRAM2_RANGE_LIST_LEN] = { 496 &MPC_ISRAM2_RANGE_S, 497 &MPC_ISRAM2_RANGE_NS 498 }; 499 500 static struct mpc_sie_dev_cfg_t MPC_ISRAM2_DEV_CFG_S = { 501 .base = MPC_ISRAM2_BASE_S, 502 .range_list = MPC_ISRAM2_RANGE_LIST, 503 .nbr_of_ranges = MPC_ISRAM2_RANGE_LIST_LEN}; 504 static struct mpc_sie_dev_data_t MPC_ISRAM2_DEV_DATA_S = { 505 .is_initialized = false}; 506 507 struct mpc_sie_dev_t MPC_ISRAM2_DEV_S = { 508 &(MPC_ISRAM2_DEV_CFG_S), 509 &(MPC_ISRAM2_DEV_DATA_S) 510 }; 511 #endif 512 513 #ifdef MPC_ISRAM3_S 514 static const struct mpc_sie_memory_range_t MPC_ISRAM3_RANGE_S = { 515 .base = MPC_ISRAM3_RANGE_BASE_S, 516 .limit = MPC_ISRAM3_RANGE_LIMIT_S, 517 .range_offset = 0, 518 .attr = MPC_SIE_SEC_ATTR_SECURE 519 }; 520 521 static const struct mpc_sie_memory_range_t MPC_ISRAM3_RANGE_NS = { 522 .base = MPC_ISRAM3_RANGE_BASE_NS, 523 .limit = MPC_ISRAM3_RANGE_LIMIT_NS, 524 .range_offset = 0, 525 .attr = MPC_SIE_SEC_ATTR_NONSECURE 526 }; 527 528 #define MPC_ISRAM3_RANGE_LIST_LEN 2u 529 static const struct mpc_sie_memory_range_t* 530 MPC_ISRAM3_RANGE_LIST[MPC_ISRAM3_RANGE_LIST_LEN] = { 531 &MPC_ISRAM3_RANGE_S, 532 &MPC_ISRAM3_RANGE_NS 533 }; 534 535 static struct mpc_sie_dev_cfg_t MPC_ISRAM3_DEV_CFG_S = { 536 .base = MPC_ISRAM3_BASE_S, 537 .range_list = MPC_ISRAM3_RANGE_LIST, 538 .nbr_of_ranges = MPC_ISRAM3_RANGE_LIST_LEN}; 539 static struct mpc_sie_dev_data_t MPC_ISRAM3_DEV_DATA_S = { 540 .is_initialized = false}; 541 542 struct mpc_sie_dev_t MPC_ISRAM3_DEV_S = { 543 &(MPC_ISRAM3_DEV_CFG_S), 544 &(MPC_ISRAM3_DEV_DATA_S) 545 }; 546 #endif 547 548 #ifdef MPC_DDR4_S 549 static const struct mpc_sie_memory_range_t MPC_DDR4_RANGE_S = { 550 .base = MPC_DDR4_RANGE_BASE_S, 551 .limit = MPC_DDR4_RANGE_LIMIT_S, 552 .range_offset = 0, 553 .attr = MPC_SIE_SEC_ATTR_SECURE 554 }; 555 556 static const struct mpc_sie_memory_range_t MPC_DDR4_RANGE_NS = { 557 .base = MPC_DDR4_RANGE_BASE_NS, 558 .limit = MPC_DDR4_RANGE_LIMIT_NS, 559 .range_offset = 0, 560 .attr = MPC_SIE_SEC_ATTR_NONSECURE 561 }; 562 563 #define MPC_DDR4_RANGE_LIST_LEN 2u 564 static const struct mpc_sie_memory_range_t* 565 MPC_DDR4_RANGE_LIST[MPC_DDR4_RANGE_LIST_LEN] = { 566 &MPC_DDR4_RANGE_S, 567 &MPC_DDR4_RANGE_NS 568 }; 569 570 static struct mpc_sie_dev_cfg_t MPC_DDR4_DEV_CFG_S = { 571 .base = MPC_DDR4_BASE_S, 572 .range_list = MPC_DDR4_RANGE_LIST, 573 .nbr_of_ranges = MPC_DDR4_RANGE_LIST_LEN}; 574 static struct mpc_sie_dev_data_t MPC_DDR4_DEV_DATA_S = { 575 .is_initialized = false}; 576 577 struct mpc_sie_dev_t MPC_DDR4_DEV_S = { 578 &(MPC_DDR4_DEV_CFG_S), 579 &(MPC_DDR4_DEV_DATA_S) 580 }; 581 #endif 582 583 #ifdef MPC_QSPI_S 584 static const struct mpc_sie_memory_range_t MPC_QSPI_RANGE_S = { 585 .base = MPC_QSPI_RANGE_BASE_S, 586 .limit = MPC_QSPI_RANGE_LIMIT_S, 587 .range_offset = 0, 588 .attr = MPC_SIE_SEC_ATTR_SECURE 589 }; 590 591 static const struct mpc_sie_memory_range_t MPC_QSPI_RANGE_NS = { 592 .base = MPC_QSPI_RANGE_BASE_NS, 593 .limit = MPC_QSPI_RANGE_LIMIT_NS, 594 .range_offset = 0, 595 .attr = MPC_SIE_SEC_ATTR_NONSECURE 596 }; 597 598 #define MPC_QSPI_RANGE_LIST_LEN 2u 599 static const struct mpc_sie_memory_range_t* 600 MPC_QSPI_RANGE_LIST[MPC_QSPI_RANGE_LIST_LEN] = { 601 &MPC_QSPI_RANGE_S, 602 &MPC_QSPI_RANGE_NS 603 }; 604 605 static struct mpc_sie_dev_cfg_t MPC_QSPI_DEV_CFG_S = { 606 .base = MPC_QSPI_BASE_S, 607 .range_list = MPC_QSPI_RANGE_LIST, 608 .nbr_of_ranges = MPC_QSPI_RANGE_LIST_LEN}; 609 static struct mpc_sie_dev_data_t MPC_QSPI_DEV_DATA_S = { 610 .is_initialized = false}; 611 612 struct mpc_sie_dev_t MPC_QSPI_DEV_S = { 613 &(MPC_QSPI_DEV_CFG_S), 614 &(MPC_QSPI_DEV_DATA_S) 615 }; 616 #endif 617 618 #ifdef MPS3_IO_S 619 static struct arm_mps3_io_dev_cfg_t MPS3_IO_DEV_CFG_S = { 620 .base = MPS3_IO_FPGAIO_BASE_S 621 }; 622 struct arm_mps3_io_dev_t MPS3_IO_DEV_S = { 623 .cfg = &(MPS3_IO_DEV_CFG_S) 624 }; 625 #endif 626 627 #ifdef MPS3_IO_NS 628 static struct arm_mps3_io_dev_cfg_t MPS3_IO_DEV_CFG_NS = { 629 .base = MPS3_IO_FPGAIO_BASE_NS 630 }; 631 struct arm_mps3_io_dev_t MPS3_IO_DEV_NS = { 632 .cfg = &(MPS3_IO_DEV_CFG_NS) 633 }; 634 #endif 635
