1 /* 2 * Copyright (c) 2017-2021 Arm Limited 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __TARGET_CFG_H__ 18 #define __TARGET_CFG_H__ 19 20 #include "uart_stdout.h" 21 #include "tfm_peripherals_def.h" 22 #include "tfm_plat_defs.h" 23 #include "arm_uart_drv.h" 24 #include "fih.h" 25 26 #define TFM_DRIVER_STDIO Driver_USART0 27 #define NS_DRIVER_STDIO Driver_USART0 28 29 /** 30 * \brief Defines the word offsets of Slave Peripheral Protection Controller 31 * Registers 32 */ 33 enum ppc_bank_e 34 { 35 PPC_SP_DO_NOT_CONFIGURE = -1, 36 PPC_SP_AHB_PPC0 = 0, 37 PPC_SP_RES0, 38 PPC_SP_RES1, 39 PPC_SP_RES2, 40 PPC_SP_AHB_PPC_EXP0, 41 PPC_SP_AHB_PPC_EXP1, 42 PPC_SP_AHB_PPC_EXP2, 43 PPC_SP_AHB_PPC_EXP3, 44 PPC_SP_APB_PPC0, 45 PPC_SP_APB_PPC1, 46 PPC_SP_RES3, 47 PPC_SP_RES4, 48 PPC_SP_APB_PPC_EXP0, 49 PPC_SP_APB_PPC_EXP1, 50 PPC_SP_APB_PPC_EXP2, 51 PPC_SP_APB_PPC_EXP3, 52 }; 53 54 /** 55 * \brief Store the addresses of memory regions 56 */ 57 struct memory_region_limits { 58 uint32_t non_secure_code_start; 59 uint32_t non_secure_partition_base; 60 uint32_t non_secure_partition_limit; 61 uint32_t veneer_base; 62 uint32_t veneer_limit; 63 #ifdef BL2 64 uint32_t secondary_partition_base; 65 uint32_t secondary_partition_limit; 66 #endif /* BL2 */ 67 }; 68 69 /** 70 * \brief Holds the data necessary to do isolation for a specific peripheral. 71 */ 72 struct platform_data_t 73 { 74 uint32_t periph_start; 75 uint32_t periph_limit; 76 enum ppc_bank_e periph_ppc_bank; 77 int16_t periph_ppc_loc; 78 }; 79 80 /** 81 * \brief Configures the Memory Protection Controller. 82 * 83 * \return Returns error code. 84 */ 85 FIH_RET_TYPE(int32_t) mpc_init_cfg(void); 86 87 /** 88 * \brief Configures the Peripheral Protection Controller. 89 */ 90 FIH_RET_TYPE(int32_t) ppc_init_cfg(void); 91 92 /** 93 * \brief Restict access to peripheral to secure 94 */ 95 FIH_RET_TYPE(int32_t) ppc_configure_to_secure(enum ppc_bank_e bank, uint16_t loc); 96 97 /** 98 * \brief Allow non-secure access to peripheral 99 */ 100 void ppc_configure_to_non_secure(enum ppc_bank_e bank, uint16_t loc); 101 102 /** 103 * \brief Enable secure unprivileged access to peripheral 104 */ 105 FIH_RET_TYPE(int32_t) ppc_en_secure_unpriv(enum ppc_bank_e bank, uint16_t pos); 106 107 /** 108 * \brief Clear secure unprivileged access to peripheral 109 */ 110 FIH_RET_TYPE(int32_t) ppc_clr_secure_unpriv(enum ppc_bank_e bank, uint16_t pos); 111 112 /** 113 * \brief Clears PPC interrupt. 114 */ 115 void ppc_clear_irq(void); 116 117 /** 118 * \brief Configures SAU and IDAU. 119 */ 120 FIH_RET_TYPE(int32_t) sau_and_idau_cfg(void); 121 122 /** 123 * \brief Enables the fault handlers and sets priorities. 124 * 125 * \return Returns values as specified by the \ref tfm_plat_err_t 126 */ 127 enum tfm_plat_err_t enable_fault_handlers(void); 128 129 /** 130 * \brief Configures the system reset request properties 131 * 132 * \return Returns values as specified by the \ref tfm_plat_err_t 133 */ 134 enum tfm_plat_err_t system_reset_cfg(void); 135 136 /** 137 * \brief Configures the system debug properties. 138 * 139 * \return Returns values as specified by the \ref tfm_plat_err_t 140 */ 141 FIH_RET_TYPE(enum tfm_plat_err_t) init_debug(void); 142 143 /** 144 * \brief Configures all external interrupts to target the 145 * NS state, apart for the ones associated to secure 146 * peripherals (plus MPC and PPC) 147 * 148 * \return Returns values as specified by the \ref tfm_plat_err_t 149 */ 150 enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void); 151 152 /** 153 * \brief This function enable the interrupts associated 154 * to the secure peripherals (plus the isolation boundary violation 155 * interrupts) 156 * 157 * \return Returns values as specified by the \ref tfm_plat_err_t 158 */ 159 enum tfm_plat_err_t nvic_interrupt_enable(void); 160 161 /* Function for FIH to verify that SAU & IDAU are correctly configured. */ 162 fih_int fih_verify_sau_and_idau_cfg(void); 163 164 /* Function for FIH to verify that MPC is correctly configured. */ 165 fih_int fih_verify_mpc_cfg(void); 166 167 /* Function for FIH to verify that PPC is correctly configured. */ 168 fih_int fih_verify_ppc_cfg(void); 169 170 #endif /* __TARGET_CFG_H__ */ 171
