1 /* 2 * Copyright (c) 2016-2018 ARM Limited 3 * 4 * Licensed under the Apache License Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing software 11 * distributed under the License is distributed on an "AS IS" BASIS 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 /** 18 * \file platform_retarget.h 19 * \brief This file defines all the peripheral base addresses for MPS2/AN519 platform. 20 */ 21 22 #ifndef __ARM_LTD_AN519_RETARGET_H__ 23 #define __ARM_LTD_AN519_RETARGET_H__ 24 25 #include "platform_regs.h" /* Platform registers */ 26 #include "platform_irq.h" /* IRQ numbers */ 27 #include "platform_retarget_pins.h" /* Platform pin names */ 28 29 /* ======= Defines peripherals memory map addresses ======= */ 30 /* Non-secure memory map addresses */ 31 #define CMSDK_TIMER0_BASE_NS 0x40000000 32 #define CMSDK_TIMER1_BASE_NS 0x40001000 33 #define APB_DUALTIMER_BASE_NS 0x40002000 34 #define S32K_TIMER_BASE_NS 0x4002F000 35 #define S32K_WATCHDOG_BASE_NS 0x4002E000 36 #define APB_WATCHDOG_BASE_NS 0x40081000 37 #define GPIO0_BASE_NS 0x40100000 38 #define GPIO1_BASE_NS 0x40101000 39 #define GPIO2_BASE_NS 0x40102000 40 #define GPIO3_BASE_NS 0x40103000 41 #define UART0_BASE_NS 0x40200000 42 #define UART1_BASE_NS 0x40201000 43 #define UART2_BASE_NS 0x40202000 44 #define UART3_BASE_NS 0x40203000 45 #define UART4_BASE_NS 0x40204000 46 #define I2C0_SBCON_BASE_NS 0x40207000 /* Touchscreen I2C Base Address */ 47 #define I2C1_SBCON_BASE_NS 0x40208000 /* Audio I2C Base Address */ 48 #define I2C2_SBCON_BASE_NS 0x4020C000 /* Shield 0 SBCon Base Address */ 49 #define I2C3_SBCON_BASE_NS 0x4020D000 /* Shield 1 SBCon Base Address */ 50 #define SSP0_BASE_NS 0x40206000 /* CLCD SSP PL022 Base Address */ 51 #define SSP1_BASE_NS 0x40205000 /* User SSP PL022 Base Address */ 52 #define SSP2_BASE_NS 0x40209000 /* ADC SPI PL022 Base Address */ 53 #define SSP3_BASE_NS 0x4020A000 /* Shield 0 SPI PL022 Base Address */ 54 #define SSP4_BASE_NS 0x4020B000 /* Shield 1 SPI PL022 Base Address */ 55 #define MPS2_IO_SCC_BASE_NS 0x40300000 56 #define MPS2_IO_FPGAIO_BASE_NS 0x40302000 57 58 /* Secure memory map addresses */ 59 #define CMSDK_TIMER0_BASE_S 0x50000000 60 #define CMSDK_TIMER1_BASE_S 0x50001000 61 #define APB_DUALTIMER_BASE_S 0x50002000 62 #define S32K_TIMER_BASE_S 0x5002F000 63 #define S32K_WATCHDOG_BASE_S 0x5002E000 64 #define APB_WATCHDOG_BASE_S 0x50081000 65 #define GPIO0_BASE_S 0x50100000 66 #define GPIO1_BASE_S 0x50101000 67 #define GPIO2_BASE_S 0x50102000 68 #define GPIO3_BASE_S 0x50103000 69 #define UART0_BASE_S 0x50200000 70 #define UART1_BASE_S 0x50201000 71 #define UART2_BASE_S 0x50202000 72 #define UART3_BASE_S 0x50203000 73 #define UART4_BASE_S 0x50204000 74 #define I2C0_SBCON_BASE_S 0x50207000 75 #define I2C1_SBCON_BASE_S 0x50208000 76 #define I2C2_SBCON_BASE_S 0x5020C000 77 #define I2C3_SBCON_BASE_S 0x5020D000 78 #define SSP0_BASE_S 0x50206000 79 #define SSP1_BASE_S 0x50205000 80 #define SSP2_BASE_S 0x50209000 81 #define SSP3_BASE_S 0x5020A000 82 #define SSP4_BASE_S 0x5020B000 83 #define MPS2_IO_SCC_BASE_S 0x50300000 84 #define MPS2_IO_FPGAIO_BASE_S 0x50302000 85 #define MPC_ISRAM0_BASE_S 0x50083000 86 #define MPC_CODE_SRAM1_BASE_S 0x58007000 87 #define MPC_CODE_SRAM2_BASE_S 0x58008000 88 #define MPC_CODE_SRAM3_BASE_S 0x58009000 89 90 /* SRAM MPC ranges and limits */ 91 /* Internal memory */ 92 #define MPC_ISRAM0_RANGE_BASE_NS 0x20000000 93 #define MPC_ISRAM0_RANGE_LIMIT_NS 0x20007FFF 94 #define MPC_ISRAM0_RANGE_BASE_S 0x30000000 95 #define MPC_ISRAM0_RANGE_LIMIT_S 0x30007FFF 96 97 /* External SSRAM memory */ 98 #define MPC_CODE_SRAM1_RANGE_BASE_NS 0x00000000 99 #define MPC_CODE_SRAM1_RANGE_LIMIT_NS 0x003FFFFF 100 #define MPC_CODE_SRAM1_RANGE_BASE_S 0x10000000 101 #define MPC_CODE_SRAM1_RANGE_LIMIT_S 0x103FFFFF 102 103 #define MPC_CODE_SRAM2_RANGE_BASE_NS 0x28000000 104 #define MPC_CODE_SRAM2_RANGE_LIMIT_NS 0x281FFFFF 105 #define MPC_CODE_SRAM2_RANGE_BASE_S 0x38000000 106 #define MPC_CODE_SRAM2_RANGE_LIMIT_S 0x381FFFFF 107 108 #define MPC_CODE_SRAM3_RANGE_BASE_NS 0x28200000 109 #define MPC_CODE_SRAM3_RANGE_LIMIT_NS 0x283FFFFF 110 #define MPC_CODE_SRAM3_RANGE_BASE_S 0x38200000 111 #define MPC_CODE_SRAM3_RANGE_LIMIT_S 0x383FFFFF 112 113 /* Flash memory emulated over external SSRAM memory */ 114 #define FLASH0_BASE_S 0x10000000 115 #define FLASH0_BASE_NS 0x00000000 116 #define FLASH0_SIZE 0x00400000 /* 4 MB */ 117 #define FLASH0_SECTOR_SIZE 0x00001000 /* 4 kB */ 118 #define FLASH0_PAGE_SIZE 0x00001000 /* 4 kB */ 119 #define FLASH0_PROGRAM_UNIT 0x1 /* Minimum write size */ 120 121 #endif /* __ARM_LTD_AN519_RETARGET_H__ */ 122
