1/*
2 * Copyright (c) 2017-2023 Arm Limited. All rights reserved.
3 * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company)
4 * or an affiliate of Cypress Semiconductor Corporation. All rights reserved.
5 *
6 * Licensed under the Apache License, Version 2.0 (the "License");
7 * you may not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 *     http://www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an "AS IS" BASIS,
14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19/***********{{utilities.donotedit_warning}}***********/
20
21/*
22 * Customized region name prefix abbreviation:
23 *  LR : A Load region.
24 *  ER : A typical execution region.
25 *  PT : An empty execution region used as position-tag/address-alignment.
26 *
27 * No applying customzied prefixes on linker/system reserved/intentional
28 * names, such as 'ARM_LIB_STACK'.
29 */
30
31#include "region_defs.h"
32
33/* Include file with definitions for section alignments.
34 * Note: it should be included after region_defs.h to let platform define
35 * default values if needed. */
36#include "tfm_s_linker_alignments.h"
37
38LR_CODE S_CODE_START S_CODE_SIZE {
39    PT_RO_START +0 ALIGN TFM_LINKER_PT_RO_ALIGNMENT EMPTY 0x0 {
40        /* Position tag: code + RO-data */
41    }
42
43    /**** This initial section contains mainly the SPM code and RO-data */
44    ER_VECTORS +0 ALIGN 4 S_CODE_VECTOR_TABLE_SIZE {
45        *.o (RESET +First)
46    }
47#ifdef CONFIG_TFM_USE_TRUSTZONE
48    ER_VECTORS_FILL +0 EMPTY (S_CODE_VECTOR_TABLE_SIZE - ImageLength(ER_VECTORS)) {
49    }
50
51    /*
52     * Place the CMSE Veneers (containing the SG instruction) in a separate
53     * 32 bytes aligned region so that the SAU can be programmed to
54     * just set this region as Non-Secure Callable.
55     */
56    ER_VENEER +0 FIXED ALIGN TFM_LINKER_VENEERS_ALIGNMENT {
57        *(Veneer$$CMSE)
58    }
59    /*
60     * The Limit of the VENEER_ALIGN region should be at least 32 bytes aligned
61     * so that the SAU can set this region as Non-Secure Callable.
62     */
63    VENEER_ALIGN +0 ALIGN TFM_LINKER_VENEERS_ALIGNMENT EMPTY 0x0 {
64    }
65#endif
66
67    ER_TFM_CODE +0 {
68        *startup*(.text*)
69        *libplatform_s* (+RO)
70        *libtfm_spm* (+RO)
71    }
72
73    /**** Section for holding partition RO load data */
74    /*
75     * Sort the partition info by priority to guarantee the initing order.
76     * The first loaded partition will be inited at last in SFN model.
77     */
78    TFM_SP_LOAD_LIST +0 ALIGN 4 {
79        *(.part_load_priority_00)
80        *(.part_load_priority_01)
81        *(.part_load_priority_02)
82        *(.part_load_priority_03)
83    }
84
85    /**** PSA RoT CODE + RO-data starts here */
86{% for partition in partitions %}
87    {% if partition.manifest.type == 'PSA-ROT' %}
88    ER_{{partition.manifest.name}}_RO +0 ALIGN TFM_LINKER_PSA_ROT_LINKER_CODE_ALIGNMENT {
89    {% if partition.attr.linker_pattern.library_list %}
90        {% for pattern in partition.attr.linker_pattern.library_list %}
91        {{pattern}} (+RO-CODE, +RO-DATA)
92        {% endfor %}
93    {% endif %}
94    {% if partition.attr.linker_pattern.object_list %}
95        {% for pattern in partition.attr.linker_pattern.object_list %}
96        {{pattern}} (+RO-CODE, +RO-DATA)
97        {% endfor %}
98    {% endif %}
99        *({{partition.manifest.name}}_PSA-ROT_ATTR_FN)
100    }
101
102    {% endif %}
103{% endfor %}
104    /**** PSA RoT CODE + RO-data ends here */
105
106    /**** APPLICATION RoT CODE + RO-data starts here */
107{% for partition in partitions %}
108    {% if partition.manifest.type == 'APPLICATION-ROT' %}
109    ER_{{partition.manifest.name}}_RO +0 ALIGN TFM_LINKER_APP_ROT_LINKER_CODE_ALIGNMENT {
110    {% if partition.attr.linker_pattern.library_list %}
111        {% for pattern in partition.attr.linker_pattern.library_list %}
112        {{pattern}} (+RO-CODE, +RO-DATA)
113        {% endfor %}
114    {% endif %}
115    {% if partition.attr.linker_pattern.object_list %}
116        {% for pattern in partition.attr.linker_pattern.object_list %}
117        {{pattern}} (+RO-CODE, +RO-DATA)
118        {% endfor %}
119    {% endif %}
120        *({{partition.manifest.name}}_APP-ROT_ATTR_FN)
121    }
122
123    {% endif %}
124{% endfor %}
125    /**** APPLICATION RoT CODE + RO-data ends here */
126
127    /**** Unprivileged Secure code + RO-data starts here */
128    TFM_UNPRIV_CODE_START +0 ALIGN TFM_LINKER_UNPRIV_CODE_ALIGNMENT {
129        * (+RO)
130    }
131
132    /*
133     * This empty, zero long execution region is here to mark the end address
134     * of TFM unprivileged code.
135     */
136    TFM_UNPRIV_CODE_END +0 ALIGN TFM_LINKER_UNPRIV_CODE_ALIGNMENT EMPTY 0x0 {
137    }
138
139    PT_RO_END +0 ALIGN TFM_LINKER_PT_RO_ALIGNMENT EMPTY 0x0 {
140        /* Position tag */
141    }
142
143    /**** Base address of secure data area */
144    PT_SECURE_DATA_START S_DATA_START EMPTY 0x0 {
145        /* Position tag */
146    }
147
148    PT_PRIV_RWZI_START +0 ALIGN TFM_LINKER_PT_PRIV_RWZI_ALIGNMENT EMPTY 0x0 {
149        /* Position tag */
150    }
151
152    /* Shared area between BL2 and runtime to exchange data */
153    TFM_SHARED_DATA +0 ALIGN TFM_LINKER_BL2_SHARED_DATA_ALIGNMENT OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE {
154    }
155
156    /* MSP */
157    ARM_LIB_STACK +0 ALIGN TFM_LINKER_MSP_STACK_ALIGNMENT OVERLAY EMPTY S_MSP_STACK_SIZE - 0x8 {
158    }
159
160    STACKSEAL +0 EMPTY 0x8 {
161    }
162
163    ER_TFM_DATA +0 {
164        * (+RW +ZI)
165    }
166
167    /**** The runtime partition placed order is same as load partition */
168    ER_PART_RT_POOL +0 ALIGN 4 {
169        *(.bss.part_runtime_priority_00)
170        *(.bss.part_runtime_priority_01)
171        *(.bss.part_runtime_priority_02)
172        *(.bss.part_runtime_priority_03)
173    }
174
175    /**** The runtime service placed order is same as load partition */
176    ER_SERV_RT_POOL +0 ALIGN 4 {
177        *(.bss.serv_runtime_priority_00)
178        *(.bss.serv_runtime_priority_01)
179        *(.bss.serv_runtime_priority_02)
180        *(.bss.serv_runtime_priority_03)
181    }
182
183    /**** PSA RoT RWZI starts here */
184{% for partition in partitions %}
185    {% if partition.manifest.type == 'PSA-ROT' %}
186
187    PT_{{partition.manifest.name}}_PRIVATE_DATA_START +0 ALIGN TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT {
188        /* Position tag */
189    }
190
191    ER_{{partition.manifest.name}}_RWZI +0 ALIGN TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT {
192    {% if partition.attr.linker_pattern.library_list %}
193        {% for pattern in partition.attr.linker_pattern.library_list %}
194        {{pattern}} (+RW +ZI)
195        {% endfor %}
196    {% endif %}
197    {% if partition.attr.linker_pattern.object_list %}
198        {% for pattern in partition.attr.linker_pattern.object_list %}
199        {{pattern}} (+RW +ZI)
200        {% endfor %}
201    {% endif %}
202        *({{partition.manifest.name}}_PSA-ROT_ATTR_RW)
203        *({{partition.manifest.name}}_PSA-ROT_ATTR_ZI)
204    }
205
206    PT_{{partition.manifest.name}}_PRIVATE_DATA_END +0 ALIGN TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT {
207        /* Position tag */
208    }
209
210    {% endif %}
211{% endfor %}
212
213    /**** PSA RoT RWZI ends here */
214    PT_PRIV_RWZI_END +0 ALIGN TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT EMPTY 0x0 {
215        /* Position tag */
216    }
217
218{% for partition in partitions %}
219    {% if partition.manifest.type == 'APPLICATION-ROT' %}
220
221    PT_{{partition.manifest.name}}_PRIVATE_DATA_START +0 ALIGN TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT {
222        /* Position tag */
223    }
224
225    ER_{{partition.manifest.name}}_RWZI +0 ALIGN TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT {
226    {% if partition.attr.linker_pattern.library_list %}
227        {% for pattern in partition.attr.linker_pattern.library_list %}
228        {{pattern}} (+RW +ZI)
229        {% endfor %}
230    {% endif %}
231    {% if partition.attr.linker_pattern.object_list %}
232        {% for pattern in partition.attr.linker_pattern.object_list %}
233        {{pattern}} (+RW +ZI)
234        {% endfor %}
235    {% endif %}
236        *({{partition.manifest.name}}_APP-ROT_ATTR_RW)
237        *({{partition.manifest.name}}_APP-ROT_ATTR_ZI)
238    }
239
240    PT_{{partition.manifest.name}}_PRIVATE_DATA_END +0 ALIGN TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT {
241        /* Position tag */
242    }
243
244    {% endif %}
245{% endfor %}
246
247#if defined(CONFIG_TFM_PARTITION_META)
248    TFM_SP_META_PTR +0 ALIGN TFM_LINKER_SP_META_PTR_ALIGNMENT {
249        *(.bss.SP_META_PTR_SPRTL_INST)
250    }
251    /*
252     * This empty, zero long execution region is here to mark the end address
253     * of TFM partition metadata pointer region.
254     */
255    TFM_SP_META_PTR_END +0 ALIGN TFM_LINKER_SP_META_PTR_ALIGNMENT EMPTY 0x0 {
256    }
257#endif
258
259#ifdef RAM_VECTORS_SUPPORT
260    ER_RAM_VECTORS +0 ALIGN TFM_LINKER_RAM_VECTORS_ALIGNMENT UNINIT {
261        * (RESET_RAM)
262    }
263#endif
264
265    PT_SRAM_WATERMARK +0 EMPTY 0x0 {
266        /* Position tag */
267    }
268
269    /* Make sure that the sections allocated in the SRAM does not exceed the
270     * size of the SRAM available.
271     */
272    ScatterAssert(ImageLimit(PT_SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE)
273
274#if defined(S_RAM_CODE_START)
275    /* Flash drivers code that gets copied from Flash */
276    ER_CODE_SRAM S_RAM_CODE_START ALIGN 4 {
277        *libflash_drivers* (+RO)
278        * (.ramfunc)
279    }
280
281    /* This empty, zero long execution region is here to mark the limit
282     * address of the last execution region that is allocated in CODE_SRAM.
283     */
284    ER_CODE_SRAM_WATERMARK +0 EMPTY 0x0 {
285    }
286
287    /* Make sure that the sections allocated in the CODE_SRAM does not exceed
288     * the size of the SRAM available.
289     */
290    ScatterAssert(ImageLimit(ER_CODE_SRAM_WATERMARK) <=
291                  S_RAM_CODE_START + S_RAM_CODE_SIZE)
292#endif
293}
294
295LR_NS_PARTITION NS_PARTITION_START {
296    /* Reserved place for NS application.
297     * No code will be placed here, just address of this region is used in the
298     * secure code to configure certain HW components. This generates an empty
299     * execution region description warning during linking.
300     */
301    ER_NS_PARTITION NS_PARTITION_START UNINIT NS_PARTITION_SIZE {
302    }
303}
304
305#ifdef BL2
306LR_SECONDARY_PARTITION SECONDARY_PARTITION_START {
307    /* Reserved place for new image in case of firmware upgrade.
308     * No code will be placed here, just address of this region is used in the
309     * secure code to configure certain HW components. This generates an empty
310     * execution region description warning during linking.
311     */
312    ER_SECONDARY_PARTITION SECONDARY_PARTITION_START \
313        UNINIT SECONDARY_PARTITION_SIZE {
314    }
315}
316#endif /* BL2 */
317