1/*
2 * Copyright (c) 2017-2023 Arm Limited. All rights reserved.
3 * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company)
4 * or an affiliate of Cypress Semiconductor Corporation. All rights reserved.
5 *
6 * Licensed under the Apache License, Version 2.0 (the "License");
7 * you may not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 *     http://www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an "AS IS" BASIS,
14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19#include "region_defs.h"
20
21/* Include file with definitions for section alignments.
22 * Note: it should be included after region_defs.h to let platform define
23 * default values if needed. */
24#include "tfm_s_linker_alignments.h"
25
26LR_CODE S_CODE_START S_CODE_SIZE {
27    PT_RO_START +0 ALIGN TFM_LINKER_PT_RO_ALIGNMENT EMPTY 0x0 {
28        /* Position tag: code + RO-data */
29    }
30
31    /****  This initial section contains common code for secure binary */
32    ER_VECTORS S_CODE_START S_CODE_VECTOR_TABLE_SIZE {
33        *.o (RESET +First)
34    }
35#ifdef CONFIG_TFM_USE_TRUSTZONE
36    ER_VECTORS_FILL +0 EMPTY (S_CODE_VECTOR_TABLE_SIZE - ImageLength(ER_VECTORS)) {
37    }
38    /*
39     * Place the CMSE Veneers (containing the SG instruction) in a separate
40     * 32 bytes aligned region so that the SAU can be programmed to
41     * just set this region as Non-Secure Callable.
42     */
43    ER_VENEER +0 FIXED ALIGN TFM_LINKER_VENEERS_ALIGNMENT {
44        *(Veneer$$CMSE)
45    }
46    /*
47     * The Limit of the VENEER_ALIGN region should be at least 32 bytes aligned
48     * so that the SAU can set this region as Non-Secure Callable.
49     */
50    VENEER_ALIGN +0 ALIGN TFM_LINKER_VENEERS_ALIGNMENT EMPTY 0x0 {
51    }
52#endif
53
54    ER_TFM_CODE +0 {
55        *startup*(.text*)
56        *libplatform_s* (.text*, .rodata*)
57        *libtfm_spm* (+RO)
58    }
59
60    /**** Unprivileged Secure code start here */
61    TFM_UNPRIV_CODE_START +0 ALIGN TFM_LINKER_UNPRIV_CODE_ALIGNMENT {
62        * (+RO)
63    }
64
65    /*
66     * This empty, zero long execution region is here to mark the end address
67     * of TFM unprivileged code.
68     */
69    TFM_UNPRIV_CODE_END +0 ALIGN TFM_LINKER_UNPRIV_CODE_ALIGNMENT EMPTY 0x0 {
70    }
71
72    /**** Section for holding partition RO load data */
73    /*
74     * Sort the partition info by priority to guarantee the initing order.
75     * The first loaded partition will be inited at last in SFN model.
76     */
77    TFM_SP_LOAD_LIST +0 ALIGN 4 {
78        *(.part_load_priority_00)
79        *(.part_load_priority_01)
80        *(.part_load_priority_02)
81        *(.part_load_priority_03)
82    }
83
84    /**** PSA RoT RO part (CODE + RODATA) start here */
85    /*
86     * This empty, zero long execution region is here to mark the start address
87     * of PSA RoT code.
88     */
89    TFM_PSA_CODE_START +0 ALIGN TFM_LINKER_PSA_ROT_LINKER_CODE_ALIGNMENT EMPTY 0x0 {
90    }
91
92    TFM_PSA_ROT_LINKER +0 ALIGN TFM_LINKER_PSA_ROT_LINKER_CODE_ALIGNMENT {
93        *tfm_psa_rot_partition* (+RO-CODE, +RO-DATA)
94        *libplatform_s* (TFM_*_PSA-ROT_ATTR_FN)
95        *.o (TFM_*_PSA-ROT_ATTR_FN)
96    }
97
98    /*
99     * This empty, zero long execution region is here to mark the end address
100     * of PSA RoT code.
101     */
102    TFM_PSA_CODE_END +0 ALIGN TFM_LINKER_PSA_ROT_LINKER_CODE_ALIGNMENT EMPTY 0x0 {
103    }
104
105    /**** APPLICATION RoT RO part (CODE + RODATA) start here */
106    /*
107     * This empty, zero long execution region is here to mark the start address
108     * of APP RoT code.
109     */
110    TFM_APP_CODE_START +0 ALIGN TFM_LINKER_APP_ROT_LINKER_CODE_ALIGNMENT EMPTY 0x0 {
111    }
112
113    TFM_APP_ROT_LINKER +0 ALIGN TFM_LINKER_APP_ROT_LINKER_CODE_ALIGNMENT {
114        *tfm_app_rot_partition* (+RO-CODE, +RO-DATA)
115        *libplatform_s* (TFM_*_APP-ROT_ATTR_FN)
116        *.o (TFM_*_APP-ROT_ATTR_FN)
117    }
118
119    /*
120     * This empty, zero long execution region is here to mark the end address
121     * of APP RoT code.
122     */
123    TFM_APP_CODE_END +0 ALIGN TFM_LINKER_APP_ROT_LINKER_CODE_ALIGNMENT EMPTY 0x0 {
124    }
125
126#if defined(S_RAM_CODE_START)
127    /* Flash drivers code that gets copied from Flash */
128    ER_CODE_SRAM S_RAM_CODE_START ALIGN 4 {
129        *libflash_drivers* (+RO)
130        * (.ramfunc)
131    }
132
133    /* This empty, zero long execution region is here to mark the limit
134     * address of the last execution region that is allocated in CODE_SRAM.
135     */
136    ER_CODE_SRAM_WATERMARK +0 EMPTY 0x0 {
137    }
138
139    /* Make sure that the sections allocated in the CODE_SRAM does not exceed
140     * the size of the SRAM available.
141     */
142    ScatterAssert(ImageLimit(ER_CODE_SRAM_WATERMARK) <=
143                  S_RAM_CODE_START + S_RAM_CODE_SIZE)
144#endif
145
146    PT_RO_END +0 ALIGN TFM_LINKER_PT_RO_ALIGNMENT EMPTY 0x0 {
147        /* Position tag */
148    }
149
150    /**** Base address of secure data area */
151    TFM_SECURE_DATA_START S_DATA_START {
152    }
153
154    /*
155     * MPU on Armv6-M/v7-M core in multi-core topology may require more strict
156     * alignment that MPU region base address must align with the MPU region
157     * size.
158     * As a result, on Armv6-M/v7-M cores, to save memory resource and MPU
159     * regions, unprivileged data sections and privileged data sections are
160     * separated and gathered in unprivileged/privileged data area respectively.
161     * Keep BL2 shared data and MSP stack at the beginning of the secure data
162     * area on Armv8-M cores, while move the two areas to the beginning of
163     * privileged data region on Armv6-M/v7-M cores.
164     */
165#if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__) || \
166    defined(__ARM_ARCH_8_1M_MAIN__)
167#ifdef CODE_SHARING
168    /* The code sharing between bootloader and runtime requires to share the
169     * global variables.
170     */
171    TFM_SHARED_SYMBOLS +0 ALIGN TFM_LINKER_SHARED_SYMBOLS_ALIGNMENT EMPTY SHARED_SYMBOL_AREA_SIZE {
172    }
173#endif
174
175    /* Shared area between BL2 and runtime to exchange data */
176    TFM_SHARED_DATA +0 ALIGN TFM_LINKER_BL2_SHARED_DATA_ALIGNMENT OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE {
177    }
178
179    /* MSP */
180    ARM_LIB_STACK +0 ALIGN TFM_LINKER_MSP_STACK_ALIGNMENT OVERLAY EMPTY S_MSP_STACK_SIZE - 0x8 {
181    }
182
183    STACKSEAL +0 EMPTY 0x8 {
184    }
185
186#endif /* defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__) || \
187        * defined(__ARM_ARCH_8_1M_MAIN__) */
188
189#if defined(CONFIG_TFM_PARTITION_META)
190    TFM_SP_META_PTR +0 ALIGN TFM_LINKER_SP_META_PTR_ALIGNMENT {
191        *(.bss.SP_META_PTR_SPRTL_INST)
192    }
193    /*
194     * This empty, zero long execution region is here to mark the end address
195     * of TFM partition metadata pointer region.
196     */
197    TFM_SP_META_PTR_END +0 ALIGN TFM_LINKER_SP_META_PTR_ALIGNMENT EMPTY 0x0 {
198    }
199#endif
200
201    /**** APP RoT DATA start here */
202    /*
203     * This empty, zero long execution region is here to mark the start address
204     * of APP RoT RW and Stack.
205     */
206    TFM_APP_RW_STACK_START +0 ALIGN TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT EMPTY 0x0 {
207    }
208
209    TFM_APP_ROT_LINKER_DATA +0 ALIGN TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT {
210        *tfm_app_rot_partition* (+RW +ZI)
211        *.o(TFM_*_APP-ROT_ATTR_RW)
212        *.o(TFM_*_APP-ROT_ATTR_ZI)
213    }
214
215    /*
216     * This empty, zero long execution region is here to mark the end address
217     * of APP RoT RW and Stack.
218     */
219    TFM_APP_RW_STACK_END +0 ALIGN TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT EMPTY 0x0 {
220    }
221
222#if defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_7M__) || \
223    defined(__ARM_ARCH_7EM__)
224#ifdef S_DATA_PRIV_START
225    /**** Privileged data area base address specified by Armv6-M/v7-M platform */
226    TFM_SECURE_PRIV_DATA_BOUNDARY S_DATA_PRIV_START {
227    }
228#endif
229
230    /*
231     * Move BL2 shared area and MSP stack to the beginning of privileged data
232     * area on Armv6-M/v7-M platforms.
233     */
234    /* Shared area between BL2 and runtime to exchange data */
235    TFM_SHARED_DATA +0 ALIGN TFM_LINKER_BL2_SHARED_DATA_ALIGNMENT OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE {
236    }
237
238    /* MSP */
239    ARM_LIB_STACK +0 ALIGN TFM_LINKER_MSP_STACK_ALIGNMENT OVERLAY EMPTY S_MSP_STACK_SIZE {
240    }
241#endif /* defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_7M__) || \
242        * defined(__ARM_ARCH_7EM__) */
243
244    ER_TFM_DATA +0 {
245        * (+RW +ZI)
246    }
247
248    /**** The runtime partition placed order is same as load partition */
249    ER_PART_RT_POOL +0 ALIGN 4 {
250        *(.bss.part_runtime_priority_00)
251        *(.bss.part_runtime_priority_01)
252        *(.bss.part_runtime_priority_02)
253        *(.bss.part_runtime_priority_03)
254    }
255
256    /**** The runtime service placed order is same as load partition */
257    ER_SERV_RT_POOL +0 ALIGN 4 {
258        *(.bss.serv_runtime_priority_00)
259        *(.bss.serv_runtime_priority_01)
260        *(.bss.serv_runtime_priority_02)
261        *(.bss.serv_runtime_priority_03)
262    }
263
264    /**** PSA RoT DATA start here */
265    /*
266     * This empty, zero long execution region is here to mark the start address
267     * of PSA RoT RW and Stack.
268     */
269    TFM_PSA_RW_STACK_START +0 ALIGN TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT EMPTY 0x0 {
270    }
271
272    TFM_PSA_ROT_LINKER_DATA +0 ALIGN TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT {
273        *tfm_psa_rot_partition* (+RW +ZI)
274        *.o(TFM_*_PSA-ROT_ATTR_RW)
275        *.o(TFM_*_PSA-ROT_ATTR_ZI)
276    }
277
278    /*
279     * This empty, zero long execution region is here to mark the end address
280     * of PSA RoT RW and Stack.
281     */
282    TFM_PSA_RW_STACK_END +0 ALIGN TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT EMPTY 0x0 {
283    }
284
285#ifdef RAM_VECTORS_SUPPORT
286    ER_RAM_VECTORS +0 ALIGN TFM_LINKER_RAM_VECTORS_ALIGNMENT UNINIT {
287        * (RESET_RAM)
288    }
289#endif
290
291    /* This empty, zero long execution region is here to mark the limit address
292     * of the last execution region that is allocated in SRAM.
293     */
294    SRAM_WATERMARK +0 EMPTY 0x0 {
295    }
296
297    /* Make sure that the sections allocated in the SRAM does not exceed the
298     * size of the SRAM available.
299     */
300    ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE)
301}
302
303LR_NS_PARTITION NS_PARTITION_START {
304    /* Reserved place for NS application.
305     * No code will be placed here, just address of this region is used in the
306     * secure code to configure certain HW components. This generates an empty
307     * execution region description warning during linking.
308     */
309    ER_NS_PARTITION NS_PARTITION_START UNINIT NS_PARTITION_SIZE {
310    }
311}
312
313#ifdef BL2
314LR_SECONDARY_PARTITION SECONDARY_PARTITION_START {
315    /* Reserved place for new image in case of firmware upgrade.
316     * No code will be placed here, just address of this region is used in the
317     * secure code to configure certain HW components. This generates an empty
318     * execution region description warning during linking.
319     */
320    ER_SECONDARY_PARTITION SECONDARY_PARTITION_START \
321        UNINIT SECONDARY_PARTITION_SIZE {
322    }
323}
324#endif /* BL2 */
325