1 /*
2  * Copyright (c) 2001-2019, Arm Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include "cc_pal_barrier.h"
8 
9 /* taken from arch/arm/include/asm/barrier.h */
10 
11 
12 
13 #if defined(__arm64__)
14 /* This is memmory barrier for ARM64*/
15 
16 #define dsb(opt)        asm volatile("dsb " #opt : : : "memory")
17 
18 #elif defined(__arm__)
19 /* This is memmory barrier for ARM*/
20 
21 #define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
22 
23 #else
24 #error This is a place holder for platform specific memory barrier implementation
25 #define dsb()
26 #endif
27 /* This is a plac holder for L2 cache sync function*/
28 #define CC_PAL_L2_CACHE_SYNC() do { } while (0)
29 
30 #if defined(__arm64__)
31 #define mb()            dsb(sy)
32 #define rmb()           dsb(ld)
33 #define wmb()           dsb(st)
34 #else
35 #define mb()            do { dsb(); CC_PAL_L2_CACHE_SYNC(); } while (0)
36 #define rmb()           dsb()
37 #define wmb()           mb()
38 #endif
39 
40 
41 
CC_PalWmb(void)42 void CC_PalWmb(void)
43 {
44     wmb();
45 }
46 
CC_PalRmb(void)47 void CC_PalRmb(void)
48 {
49     rmb();
50 }
51 
52 
53 
54 
55