1 /*
2  * Copyright (c) 2018-2020 Arm Limited
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  *     http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
17 #ifndef __STM32L5XX_CFG_H__
18 #define __STM32L5XX_CFG_H__
19 
20 #include "uart_stdout.h"
21 #include "tfm_peripherals_def.h"
22 
23 #define TFM_DRIVER_STDIO    Driver_USART0
24 #define NS_DRIVER_STDIO     Driver_USART0
25 
26 /**
27  * \brief Store the addresses of memory regions
28  */
29 struct memory_region_limits {
30     uint32_t non_secure_code_start;
31     uint32_t non_secure_partition_base;
32     uint32_t non_secure_partition_limit;
33     uint32_t veneer_base;
34     uint32_t veneer_limit;
35 };
36 
37 /**
38  * \brief Holds the data necessary to do isolation for a specific peripheral.
39  */
40 struct platform_data_t
41 {
42     uint32_t periph_start;
43     uint32_t periph_limit;
44     int16_t periph_ppc_bank;
45     int16_t periph_ppc_loc;
46 };
47 
48 /**
49  * \brief Configures the Memory Protection Controller.
50  */
51 void gtzc_init_cfg(void);
52 
53 
54 /**
55  * \brief pin mux configuration for non secure access
56  * */
57 void pinmux_init_cfg(void);
58 
59 
60 /**
61  * \brief Configures SAU and IDAU.
62  */
63 void sau_and_idau_cfg(void);
64 
65 /**
66  * \brief Enable Fault handling.
67  */
68 enum tfm_plat_err_t enable_fault_handlers(void);
69 
70 /**
71  * \brief Set NVIC interrupt target state to NS.
72  */
73 enum tfm_plat_err_t nvic_interrupt_target_state_cfg();
74 
75 #endif /* __STM32L5XX_CFG_H__ */
76