1 /**************************************************************************//**
2 * @file clk.c
3 * @version V3.00
4 * @brief M2354 series Clock Controller (CLK) driver source file
5 *
6 * @copyright SPDX-License-Identifier: Apache-2.0
7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
8 *****************************************************************************/
9 #include "NuMicro.h"
10 /** @addtogroup Standard_Driver Standard Driver
11 @{
12 */
13
14 /** @addtogroup CLK_Driver CLK Driver
15 @{
16 */
17
18
19 /** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions
20 @{
21 */
22
23
24 /**
25 * @brief Disable frequency output function
26 * @param None
27 * @return None
28 * @details This function disable frequency output function.
29 */
CLK_DisableCKO(void)30 void CLK_DisableCKO(void)
31 {
32 /* Disable CKO clock source */
33 CLK->APBCLK0 &= (~CLK_APBCLK0_CLKOCKEN_Msk);
34 }
35
36
37 /**
38 * @brief This function enable frequency divider module clock.
39 * enable frequency divider clock function and configure frequency divider.
40 * @param[in] u32ClkSrc is frequency divider function clock source. Including :
41 * - \ref CLK_CLKSEL1_CLKOSEL_HXT
42 * - \ref CLK_CLKSEL1_CLKOSEL_LXT
43 * - \ref CLK_CLKSEL1_CLKOSEL_HCLK
44 * - \ref CLK_CLKSEL1_CLKOSEL_HIRC
45 * @param[in] u32ClkDiv is divider output frequency selection.
46 * @param[in] u32ClkDivBy1En is frequency divided by one enable.
47 * @return None
48 *
49 * @details Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv.
50 * The formula is:
51 * CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1)
52 * This function is just used to set CKO clock.
53 * User must enable I/O for CKO clock output pin by themselves.
54 */
CLK_EnableCKO(uint32_t u32ClkSrc,uint32_t u32ClkDiv,uint32_t u32ClkDivBy1En)55 void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
56 {
57 /* CKO = clock source / 2^(u32ClkDiv + 1) */
58 CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | u32ClkDiv | (u32ClkDivBy1En << CLK_CLKOCTL_DIV1EN_Pos);
59
60 /* Enable CKO clock source */
61 CLK->APBCLK0 |= CLK_APBCLK0_CLKOCKEN_Msk;
62
63 /* Select CKO clock source */
64 CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_CLKOSEL_Msk)) | (u32ClkSrc);
65
66 }
67
68 /**
69 * @brief Enter to Power-down mode
70 * @param None
71 * @return None
72 * @details This function is used to let system enter to Power-down mode. \n
73 * The register write-protection function should be disabled before using this function.
74 */
CLK_PowerDown(void)75 void CLK_PowerDown(void)
76 {
77 volatile uint32_t u32SysTickTICKINT = 0; /* Backup Systick interrupt enable bit */
78
79 /* Set the processor uses deep sleep as its low power mode */
80 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
81
82 /* Set system Power-down enabled */
83 CLK->PWRCTL |= CLK_PWRCTL_PDEN_Msk;
84
85 /* Backup systick interrupt setting */
86 u32SysTickTICKINT = SysTick->CTRL & SysTick_CTRL_TICKINT_Msk;
87
88 /* Disable systick interrupt */
89 SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
90
91 /* Chip enter Power-down mode after CPU run WFI instruction */
92 __WFI();
93
94 /* Restore systick interrupt setting */
95 if(u32SysTickTICKINT) SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
96 }
97
98
99 /**
100 * @brief Enter to Idle mode
101 * @param None
102 * @return None
103 * @details This function let system enter to Idle mode. \n
104 * The register write-protection function should be disabled before using this function.
105 */
CLK_Idle(void)106 void CLK_Idle(void)
107 {
108 /* Set the processor uses sleep as its low power mode */
109 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
110
111 /* Set chip in idle mode because of WFI command */
112 CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk;
113
114 /* Chip enter idle mode after CPU run WFI instruction */
115 __WFI();
116 }
117
118
119 /**
120 * @brief Get external high speed crystal clock frequency
121 * @param None
122 * @return External high frequency crystal frequency
123 * @details This function get external high frequency crystal frequency. The frequency unit is Hz.
124 */
125 __NONSECURE_ENTRY_WEAK
CLK_GetHXTFreq(void)126 uint32_t CLK_GetHXTFreq(void)
127 {
128 uint32_t u32Freq = 0UL;
129 uint32_t u32HXTEN = CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk;
130
131 if(u32HXTEN)
132 {
133 u32Freq = __HXT;
134 }
135 else
136 {
137 u32Freq = 0UL;
138 }
139
140 return u32Freq;
141 }
142
143 /**
144 * @brief Get external low speed crystal clock frequency
145 * @param None
146 * @return External low speed crystal clock frequency
147 * @details This function get external low frequency crystal frequency. The frequency unit is Hz.
148 */
149
150 __NONSECURE_ENTRY_WEAK
CLK_GetLXTFreq(void)151 uint32_t CLK_GetLXTFreq(void)
152 {
153 uint32_t u32Freq = 0UL;
154 uint32_t u32LXTEN = CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk;
155
156 if(u32LXTEN)
157 {
158 u32Freq = __LXT;
159 }
160 else
161 {
162 u32Freq = 0UL;
163 }
164
165 return u32Freq;
166 }
167
168 /**
169 * @brief Get HCLK frequency
170 * @param None
171 * @return HCLK frequency
172 * @details This function get HCLK frequency. The frequency unit is Hz.
173 */
174
175 __NONSECURE_ENTRY_WEAK
CLK_GetHCLKFreq(void)176 uint32_t CLK_GetHCLKFreq(void)
177 {
178 SystemCoreClockUpdate();
179 return SystemCoreClock;
180 }
181
182 /**
183 * @brief Get PCLK0 frequency
184 * @param None
185 * @return PCLK0 frequency
186 * @details This function get PCLK0 frequency. The frequency unit is Hz.
187 */
188
189 __NONSECURE_ENTRY_WEAK
CLK_GetPCLK0Freq(void)190 uint32_t CLK_GetPCLK0Freq(void)
191 {
192 SystemCoreClockUpdate();
193 return (SystemCoreClock);
194 }
195
196 /**
197 * @brief Get PCLK1 frequency
198 * @param None
199 * @return PCLK1 frequency
200 * @details This function get PCLK1 frequency. The frequency unit is Hz.
201 */
202
203 __NONSECURE_ENTRY_WEAK
CLK_GetPCLK1Freq(void)204 uint32_t CLK_GetPCLK1Freq(void)
205 {
206 SystemCoreClockUpdate();
207 return (SystemCoreClock);
208 }
209
210 /**
211 * @brief Get CPU frequency
212 * @param None
213 * @return CPU frequency
214 * @details This function get CPU frequency. The frequency unit is Hz.
215 */
216
217 __NONSECURE_ENTRY_WEAK
CLK_GetCPUFreq(void)218 uint32_t CLK_GetCPUFreq(void)
219 {
220 uint32_t u32Freq, u32HclkSrc, u32HclkDiv;
221 uint32_t au32ClkTbl[] = {__HXT, __LXT, 0UL, __LIRC, 0UL, __HIRC48, __MIRC, __HIRC};
222 uint32_t u32PllReg, u32FIN, u32NF, u32NR, u32NO;
223 uint8_t au8NoTbl[4] = {1U, 2U, 2U, 4U};
224 uint32_t u32RTCCKEN = CLK->APBCLK0 & CLK_APBCLK0_RTCCKEN_Msk;
225
226 /* Update PLL Clock */
227 u32PllReg = CLK->PLLCTL;
228
229 if(u32PllReg & CLK_PLLCTL_PD_Msk)
230 {
231 PllClock = 0UL; /* PLL is in power down mode */
232 }
233 else /* PLL is in normal mode */
234 {
235
236 /* PLL source clock */
237 if(u32PllReg & CLK_PLLCTL_PLLSRC_Msk)
238 {
239 u32FIN = __HIRC; /* PLL source clock from HIRC */
240 }
241 else
242 {
243 u32FIN = __HXT; /* PLL source clock from HXT */
244 }
245
246 /* Calculate PLL frequency */
247 if(u32PllReg & CLK_PLLCTL_BP_Msk)
248 {
249 PllClock = u32FIN; /* PLL is in bypass mode */
250 }
251 else
252 {
253 /* PLL is output enabled in normal work mode */
254 u32NO = au8NoTbl[((u32PllReg & CLK_PLLCTL_OUTDIV_Msk) >> CLK_PLLCTL_OUTDIV_Pos)];
255 u32NF = ((u32PllReg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2UL;
256 u32NR = ((u32PllReg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos) + 1UL;
257
258 /* u32FIN is shifted 2 bits to avoid overflow */
259 PllClock = (((u32FIN >> 2) * (u32NF << 1)) / (u32NR * u32NO) << 2);
260 }
261 }
262
263 /* HCLK clock source */
264 u32HclkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
265
266 if(u32HclkSrc == CLK_CLKSEL0_HCLKSEL_LXT)
267 {
268
269 if(u32RTCCKEN == 0UL)
270 {
271 CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk; /* Enable RTC clock to get LXT clock source */
272 }
273
274 if(RTC->LXTCTL & RTC_LXTCTL_C32KSEL_Msk)
275 {
276 u32Freq = __LIRC32; /* LXT clock source is LIRC32 */
277 }
278 else
279 {
280 u32Freq = __LXT; /* LXT clock source is external LXT */
281 }
282
283 if(u32RTCCKEN == 0UL)
284 {
285 CLK->APBCLK0 &= (~CLK_APBCLK0_RTCCKEN_Msk); /* Disable RTC clock if it is disabled before */
286 }
287
288 }
289 else if(u32HclkSrc == CLK_CLKSEL0_HCLKSEL_PLL)
290 {
291 u32Freq = PllClock;/* Use PLL clock */
292 }
293 else
294 {
295 u32Freq = au32ClkTbl[u32HclkSrc]; /* Use the clock sources directly */
296 }
297
298 /* HCLK clock source divider */
299 u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1UL;
300
301 /* Update System Core Clock */
302 SystemCoreClock = u32Freq / u32HclkDiv;
303
304 /* Update Cycles per micro second */
305 CyclesPerUs = (SystemCoreClock + 500000UL) / 1000000UL;
306
307 return SystemCoreClock;
308 }
309
310 /**
311 * @brief Set HCLK frequency
312 * @param[in] u32Hclk is HCLK frequency.
313 * The range of u32Hclk is 24 MHz ~ 96 MHz.
314 * @return HCLK frequency
315 * @details This function is used to set HCLK frequency by using PLL. \n
316 * Power level is also set according to HCLK frequency. The frequency unit is Hz. \n
317 * The register write-protection function should be disabled before using this function.
318 */
CLK_SetCoreClock(uint32_t u32Hclk)319 uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
320 {
321 uint32_t u32HIRCSTB;
322
323 /* Read HIRC clock source stable flag */
324 u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
325
326 /* Check HCLK frequency range */
327 if(u32Hclk > FREQ_96MHZ)
328 {
329 u32Hclk = FREQ_96MHZ;
330 }
331 else if(u32Hclk < FREQ_24MHZ)
332 {
333 u32Hclk = FREQ_24MHZ;
334 }
335
336 /* Switch HCLK clock source to HIRC clock for safe */
337 CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
338 CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
339 CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_Msk;
340 CLK->CLKDIV0 &= (~CLK_CLKDIV0_HCLKDIV_Msk);
341
342 /* Configure PLL setting if HXT clock is stable */
343 if(CLK->STATUS & CLK_STATUS_HXTSTB_Msk)
344 {
345 u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HXT, u32Hclk);
346 }
347 /* Configure PLL setting if HXT clock is not stable */
348 else
349 {
350 u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HIRC, u32Hclk);
351
352 /* Read HIRC clock source stable flag */
353 u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
354 }
355
356 /* Select HCLK clock source to PLL,
357 select HCLK clock source divider as 1,
358 adjust power level and update system core clock
359 */
360 CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(1UL));
361
362 /* Disable HIRC if HIRC is disabled before setting core clock */
363 if(u32HIRCSTB == 0UL)
364 {
365 CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
366 }
367
368 /* Return actually HCLK frequency is PLL frequency divide 1 */
369 return u32Hclk;
370 }
371
372
373 /**
374 * @brief Set HCLK clock source and HCLK clock divider
375 * @param[in] u32ClkSrc is HCLK clock source. Including :
376 * - \ref CLK_CLKSEL0_HCLKSEL_HXT
377 * - \ref CLK_CLKSEL0_HCLKSEL_LXT
378 * - \ref CLK_CLKSEL0_HCLKSEL_PLL
379 * - \ref CLK_CLKSEL0_HCLKSEL_LIRC
380 * - \ref CLK_CLKSEL0_HCLKSEL_HIRC48
381 * - \ref CLK_CLKSEL0_HCLKSEL_MIRC
382 * - \ref CLK_CLKSEL0_HCLKSEL_HIRC
383 * @param[in] u32ClkDiv is HCLK clock divider. Including :
384 * - \ref CLK_CLKDIV0_HCLK(x)
385 * @return None
386 * @details This function set HCLK clock source and HCLK clock divider. \n
387 * Power level and flash access cycle are also set according to HCLK operation frequency. \n
388 * The register write-protection function should be disabled before using this function.
389 */
CLK_SetHCLK(uint32_t u32ClkSrc,uint32_t u32ClkDiv)390 void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
391 {
392 uint32_t u32HIRCSTB;
393
394 /* Read HIRC clock source stable flag */
395 u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
396
397 /* Switch to HIRC for safe. Avoid HCLK too high when applying new divider. */
398 CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
399 CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
400 CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_Msk;
401
402 /* Switch to power level 0 for safe */
403 while(SYS->PLCTL & SYS_PLCTL_WRBUSY_Msk);
404 SYS->PLCTL = (SYS->PLCTL & (~SYS_PLCTL_PLSEL_Msk)) | SYS_PLCTL_PLSEL_PL0;
405 while(SYS->PLSTS & SYS_PLSTS_PLCBUSY_Msk);
406
407 /* Set Flash Access Cycle to 4 for safe */
408 FMC->CYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | (4);
409
410 /* Apply new Divider */
411 CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | u32ClkDiv;
412
413 /* Switch HCLK to new HCLK source */
414 CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | u32ClkSrc;
415
416 /* Update System Core Clock */
417 SystemCoreClockUpdate();
418
419 /* Set power level according to new HCLK source */
420 while(SYS->PLCTL & SYS_PLCTL_WRBUSY_Msk);
421 if((SystemCoreClock > FREQ_48MHZ) && SystemCoreClock <= FREQ_84MHZ)
422 {
423 SYS->PLCTL = (SYS->PLCTL & (~SYS_PLCTL_PLSEL_Msk)) | SYS_PLCTL_PLSEL_PL1;
424 }
425 else if((SystemCoreClock > FREQ_4MHZ) && SystemCoreClock <= FREQ_48MHZ)
426 {
427 SYS->PLCTL = (SYS->PLCTL & (~SYS_PLCTL_PLSEL_Msk)) | SYS_PLCTL_PLSEL_PL2;
428 }
429 if(SystemCoreClock <= FREQ_4MHZ)
430 {
431 SYS->PLCTL = (SYS->PLCTL & (~SYS_PLCTL_PLSEL_Msk)) | SYS_PLCTL_PLSEL_PL3;
432 }
433 while(SYS->PLSTS & SYS_PLSTS_PLCBUSY_Msk);
434
435 /* Set Flash Access Cycle */
436 if((SystemCoreClock >= FREQ_50MHZ) && SystemCoreClock < FREQ_75MHZ)
437 {
438 FMC->CYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | (3);
439 }
440 else if((SystemCoreClock >= FREQ_25MHZ) && SystemCoreClock < FREQ_50MHZ)
441 {
442 FMC->CYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | (2);
443 }
444 if(SystemCoreClock < FREQ_25MHZ)
445 {
446 FMC->CYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | (1);
447 }
448
449 /* Disable HIRC if HIRC is disabled before switching HCLK source */
450 if(u32HIRCSTB == 0UL)
451 {
452 CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
453 }
454 }
455 /**
456 * @brief This function set selected module clock source and module clock divider
457 * @param[in] u32ModuleIdx is module index.
458 * @param[in] u32ClkSrc is module clock source.
459 * @param[in] u32ClkDiv is module clock divider.
460 * @return None
461 * @details Valid parameter combinations listed in following table:
462 *
463 * |Module index |Clock source |Divider |
464 * | :---------------- | :------------------------------------ | :----------------------- |
465 * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HXT |\ref CLK_CLKDIV0_SDH0(x) |
466 * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_PLL |\ref CLK_CLKDIV0_SDH0(x) |
467 * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HCLK |\ref CLK_CLKDIV0_SDH0(x) |
468 * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HIRC |\ref CLK_CLKDIV0_SDH0(x) |
469 * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LXT | x |
470 * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 | x |
471 * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LIRC | x |
472 * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 | x |
473 * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_LIRC | x |
474 * |\ref LCD_MODULE |\ref CLK_CLKSEL1_LCDSEL_LIRC | x |
475 * |\ref LCD_MODULE |\ref CLK_CLKSEL1_LCDSEL_LXT | x |
476 * |\ref LCDCP_MODULE |\ref CLK_CLKSEL1_LCDCPSEL_MIRC1P2M | x |
477 * |\ref LCDCP_MODULE |\ref CLK_CLKSEL1_LCDCPSEL_MIRC | x |
478 * |\ref EWDT_MODULE |\ref CLK_CLKSEL1_EWDTSEL_LXT | x |
479 * |\ref EWDT_MODULE |\ref CLK_CLKSEL1_EWDTSEL_HCLK_DIV2048 | x |
480 * |\ref EWDT_MODULE |\ref CLK_CLKSEL1_EWDTSEL_LIRC | x |
481 * |\ref EWWDT_MODULE |\ref CLK_CLKSEL1_EWWDTSEL_HCLK_DIV2048 | x |
482 * |\ref EWWDT_MODULE |\ref CLK_CLKSEL1_EWWDTSEL_LIRC | x |
483 * |\ref EADC_MODULE | x |\ref CLK_CLKDIV0_EADC(x) |
484 * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HXT | x |
485 * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LXT | x |
486 * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_PCLK0 | x |
487 * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_EXT_TRG | x |
488 * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LIRC | x |
489 * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HIRC | x |
490 * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HXT | x |
491 * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LXT | x |
492 * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_PCLK0 | x |
493 * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_EXT_TRG | x |
494 * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LIRC | x |
495 * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HIRC | x |
496 * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HXT | x |
497 * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LXT | x |
498 * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_PCLK1 | x |
499 * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_EXT_TRG | x |
500 * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LIRC | x |
501 * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HIRC | x |
502 * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HXT | x |
503 * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LXT | x |
504 * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_PCLK1 | x |
505 * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_EXT_TRG | x |
506 * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LIRC | x |
507 * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HIRC | x |
508 * |\ref TMR4_MODULE |\ref CLK_CLKSEL3_TMR4SEL_HXT | x |
509 * |\ref TMR4_MODULE |\ref CLK_CLKSEL3_TMR4SEL_LXT | x |
510 * |\ref TMR4_MODULE |\ref CLK_CLKSEL3_TMR4SEL_PCLK0 | x |
511 * |\ref TMR4_MODULE |\ref CLK_CLKSEL3_TMR4SEL_EXT_TRG | x |
512 * |\ref TMR4_MODULE |\ref CLK_CLKSEL3_TMR4SEL_MIRC | x |
513 * |\ref TMR4_MODULE |\ref CLK_CLKSEL3_TMR4SEL_LIRC | x |
514 * |\ref TMR4_MODULE |\ref CLK_CLKSEL3_TMR4SEL_HIRC | x |
515 * |\ref TMR5_MODULE |\ref CLK_CLKSEL3_TMR5SEL_HXT | x |
516 * |\ref TMR5_MODULE |\ref CLK_CLKSEL3_TMR5SEL_LXT | x |
517 * |\ref TMR5_MODULE |\ref CLK_CLKSEL3_TMR5SEL_PCLK0 | x |
518 * |\ref TMR5_MODULE |\ref CLK_CLKSEL3_TMR5SEL_EXT_TRG | x |
519 * |\ref TMR5_MODULE |\ref CLK_CLKSEL3_TMR5SEL_MIRC | x |
520 * |\ref TMR5_MODULE |\ref CLK_CLKSEL3_TMR5SEL_LIRC | x |
521 * |\ref TMR5_MODULE |\ref CLK_CLKSEL3_TMR5SEL_HIRC | x |
522 * |\ref UART0_MODULE |\ref CLK_CLKSEL2_UART0SEL_HXT |\ref CLK_CLKDIV0_UART0(x) |
523 * |\ref UART0_MODULE |\ref CLK_CLKSEL2_UART0SEL_PLL |\ref CLK_CLKDIV0_UART0(x) |
524 * |\ref UART0_MODULE |\ref CLK_CLKSEL2_UART0SEL_LXT |\ref CLK_CLKDIV0_UART0(x) |
525 * |\ref UART0_MODULE |\ref CLK_CLKSEL2_UART0SEL_HIRC |\ref CLK_CLKDIV0_UART0(x) |
526 * |\ref UART0_MODULE |\ref CLK_CLKSEL2_UART0SEL_PCLK0 |\ref CLK_CLKDIV0_UART0(x) |
527 * |\ref UART1_MODULE |\ref CLK_CLKSEL2_UART1SEL_HXT |\ref CLK_CLKDIV0_UART1(x) |
528 * |\ref UART1_MODULE |\ref CLK_CLKSEL2_UART1SEL_PLL |\ref CLK_CLKDIV0_UART1(x) |
529 * |\ref UART1_MODULE |\ref CLK_CLKSEL2_UART1SEL_LXT |\ref CLK_CLKDIV0_UART1(x) |
530 * |\ref UART1_MODULE |\ref CLK_CLKSEL2_UART1SEL_HIRC |\ref CLK_CLKDIV0_UART1(x) |
531 * |\ref UART1_MODULE |\ref CLK_CLKSEL2_UART1SEL_PCLK1 |\ref CLK_CLKDIV0_UART1(x) |
532 * |\ref UART2_MODULE |\ref CLK_CLKSEL2_UART2SEL_HXT |\ref CLK_CLKDIV4_UART2(x) |
533 * |\ref UART2_MODULE |\ref CLK_CLKSEL2_UART2SEL_PLL |\ref CLK_CLKDIV4_UART2(x) |
534 * |\ref UART2_MODULE |\ref CLK_CLKSEL2_UART2SEL_LXT |\ref CLK_CLKDIV4_UART2(x) |
535 * |\ref UART2_MODULE |\ref CLK_CLKSEL2_UART2SEL_HIRC |\ref CLK_CLKDIV4_UART2(x) |
536 * |\ref UART2_MODULE |\ref CLK_CLKSEL2_UART2SEL_PCLK0 |\ref CLK_CLKDIV4_UART2(x) |
537 * |\ref UART3_MODULE |\ref CLK_CLKSEL2_UART3SEL_HXT |\ref CLK_CLKDIV4_UART3(x) |
538 * |\ref UART3_MODULE |\ref CLK_CLKSEL2_UART3SEL_PLL |\ref CLK_CLKDIV4_UART3(x) |
539 * |\ref UART3_MODULE |\ref CLK_CLKSEL2_UART3SEL_LXT |\ref CLK_CLKDIV4_UART3(x) |
540 * |\ref UART3_MODULE |\ref CLK_CLKSEL2_UART3SEL_HIRC |\ref CLK_CLKDIV4_UART3(x) |
541 * |\ref UART3_MODULE |\ref CLK_CLKSEL2_UART3SEL_PCLK1 |\ref CLK_CLKDIV4_UART3(x) |
542 * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_HXT |\ref CLK_CLKDIV4_UART4(x) |
543 * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_PLL |\ref CLK_CLKDIV4_UART4(x) |
544 * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_LXT |\ref CLK_CLKDIV4_UART4(x) |
545 * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_HIRC |\ref CLK_CLKDIV4_UART4(x) |
546 * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_PCLK0 |\ref CLK_CLKDIV4_UART4(x) |
547 * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_HXT |\ref CLK_CLKDIV4_UART5(x) |
548 * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_PLL |\ref CLK_CLKDIV4_UART5(x) |
549 * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_LXT |\ref CLK_CLKDIV4_UART5(x) |
550 * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_HIRC |\ref CLK_CLKDIV4_UART5(x) |
551 * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_PCLK1 |\ref CLK_CLKDIV4_UART5(x) |
552 * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HXT | x |
553 * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_LXT | x |
554 * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HCLK | x |
555 * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HIRC | x |
556 * |\ref RTC_MODULE |\ref RTC_LXTCTL_RTCCKSEL_LXT | x |
557 * |\ref RTC_MODULE |\ref RTC_LXTCTL_RTCCKSEL_LIRC | x |
558 * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HXT | x |
559 * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_PLL | x |
560 * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_PCLK0 | x |
561 * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HIRC | x |
562 * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_HXT | x |
563 * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_PLL | x |
564 * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_PCLK0 | x |
565 * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_HIRC | x |
566 * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HXT | x |
567 * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PLL | x |
568 * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PCLK1 | x |
569 * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HIRC | x |
570 * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HXT | x |
571 * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PLL | x |
572 * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PCLK0 | x |
573 * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HIRC | x |
574 * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_HXT | x |
575 * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_PLL | x |
576 * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_PCLK1 | x |
577 * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_HIRC | x |
578 * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_HXT | x |
579 * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_PLL | x |
580 * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_PCLK0 | x |
581 * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_HIRC | x |
582 * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HXT |\ref CLK_CLKDIV1_SC0(x) |
583 * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PLL |\ref CLK_CLKDIV1_SC0(x) |
584 * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PCLK0 |\ref CLK_CLKDIV1_SC0(x) |
585 * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HIRC |\ref CLK_CLKDIV1_SC0(x) |
586 * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HXT |\ref CLK_CLKDIV1_SC1(x) |
587 * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PLL |\ref CLK_CLKDIV1_SC1(x) |
588 * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PCLK1 |\ref CLK_CLKDIV1_SC1(x) |
589 * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HIRC |\ref CLK_CLKDIV1_SC1(x) |
590 * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HXT |\ref CLK_CLKDIV1_SC2(x) |
591 * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PLL |\ref CLK_CLKDIV1_SC2(x) |
592 * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PCLK0 |\ref CLK_CLKDIV1_SC2(x) |
593 * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HIRC |\ref CLK_CLKDIV1_SC2(x) |
594 * |\ref USBH_MODULE |\ref CLK_CLKSEL0_USBSEL_HIRC48 |\ref CLK_CLKDIV0_USB(x) |
595 * |\ref USBH_MODULE |\ref CLK_CLKSEL0_USBSEL_PLL |\ref CLK_CLKDIV0_USB(x) |
596 * |\ref OTG_MODULE |\ref CLK_CLKSEL0_USBSEL_HIRC48 |\ref CLK_CLKDIV0_USB(x) |
597 * |\ref OTG_MODULE |\ref CLK_CLKSEL0_USBSEL_PLL |\ref CLK_CLKDIV0_USB(x) |
598 * |\ref USBD_MODULE |\ref CLK_CLKSEL0_USBSEL_HIRC48 |\ref CLK_CLKDIV0_USB(x) |
599 * |\ref USBD_MODULE |\ref CLK_CLKSEL0_USBSEL_PLL |\ref CLK_CLKDIV0_USB(x) |
600 */
CLK_SetModuleClock(uint32_t u32ModuleIdx,uint32_t u32ClkSrc,uint32_t u32ClkDiv)601 void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
602 {
603 uint32_t u32Sel = 0UL, u32Div = 0UL;
604 uint32_t au32SelTbl[4] = {0x0UL, 0x4UL, 0x8UL, 0xCUL};
605 uint32_t au32DivTbl[4] = {0x0UL, 0x4UL, 0x8UL, 0x10UL};
606 uint32_t u32RTCCKEN = CLK->APBCLK0 & CLK_APBCLK0_RTCCKEN_Msk;
607
608 if(u32ModuleIdx == RTC_MODULE) /* RTC clock source configuration */
609 {
610 if(u32RTCCKEN == 0UL)
611 {
612 CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk; /* Enable RTC clock to get LXT clock source */
613 }
614
615 /* Select RTC clock source */
616 RTC->LXTCTL = (RTC->LXTCTL & (~RTC_LXTCTL_RTCCKSEL_Msk)) | (u32ClkSrc);
617
618 if(u32RTCCKEN == 0UL)
619 {
620 CLK->APBCLK0 &= (~CLK_APBCLK0_RTCCKEN_Msk); /* Disable RTC clock if it is disabled before */
621 }
622
623 }
624 else /* Others clock source configuration */
625 {
626 if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk)
627 {
628 /* Get clock divider control register address */
629 u32Div = (uint32_t)&CLK->CLKDIV0 + (au32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]);
630 /* Apply new divider */
631 M32(u32Div) = (M32(u32Div) & (~(MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx)))) | u32ClkDiv;
632 }
633
634 if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk)
635 {
636 /* Get clock select control register address */
637 u32Sel = (uint32_t)&CLK->CLKSEL0 + (au32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]);
638 /* Set new clock selection setting */
639 M32(u32Sel) = (M32(u32Sel) & (~(MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx)))) | u32ClkSrc;
640 }
641 }
642 }
643
644 /**
645 * @brief Set SysTick clock source
646 * @param[in] u32ClkSrc is module clock source. Including:
647 * - \ref CLK_CLKSEL0_STCLKSEL_HXT
648 * - \ref CLK_CLKSEL0_STCLKSEL_LXT
649 * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2
650 * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
651 * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
652 * @return None
653 * @details This function set SysTick clock source. \n
654 * The register write-protection function should be disabled before using this function.
655 */
CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)656 void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
657 {
658 CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
659 }
660
661 /**
662 * @brief Enable clock source
663 * @param[in] u32ClkMask is clock source mask. Including :
664 * - \ref CLK_PWRCTL_HXTEN_Msk
665 * - \ref CLK_PWRCTL_LXTEN_Msk
666 * - \ref CLK_PWRCTL_HIRCEN_Msk
667 * - \ref CLK_PWRCTL_LIRCEN_Msk
668 * - \ref CLK_PWRCTL_HIRC48EN_Msk
669 * - \ref CLK_PWRCTL_MIRC1P2MEN_Msk
670 * - \ref CLK_PWRCTL_MIRCEN_Msk
671 * @return None
672 * @details This function enable clock source. \n
673 * The register write-protection function should be disabled before using this function.
674 */
CLK_EnableXtalRC(uint32_t u32ClkMask)675 void CLK_EnableXtalRC(uint32_t u32ClkMask)
676 {
677 CLK->PWRCTL |= u32ClkMask;
678 }
679
680 /**
681 * @brief Disable clock source
682 * @param[in] u32ClkMask is clock source mask. Including :
683 * - \ref CLK_PWRCTL_HXTEN_Msk
684 * - \ref CLK_PWRCTL_LXTEN_Msk
685 * - \ref CLK_PWRCTL_HIRCEN_Msk
686 * - \ref CLK_PWRCTL_LIRCEN_Msk
687 * - \ref CLK_PWRCTL_HIRC48EN_Msk
688 * - \ref CLK_PWRCTL_MIRC1P2MEN_Msk
689 * - \ref CLK_PWRCTL_MIRCEN_Msk
690 * @return None
691 * @details This function disable clock source. \n
692 * The register write-protection function should be disabled before using this function.
693 */
CLK_DisableXtalRC(uint32_t u32ClkMask)694 void CLK_DisableXtalRC(uint32_t u32ClkMask)
695 {
696 CLK->PWRCTL &= ~u32ClkMask;
697 }
698
699 /**
700 * @brief Enable module clock
701 * @param[in] u32ModuleIdx is module index. Including :
702 * - \ref PDMA0_MODULE
703 * - \ref PDMA1_MODULE
704 * - \ref ISP_MODULE
705 * - \ref EBI_MODULE
706 * - \ref SDH0_MODULE
707 * - \ref CRC_MODULE
708 * - \ref CRPT_MODULE
709 * - \ref KS_MODULE
710 * - \ref TRACE_MODULE
711 * - \ref USBH_MODULE
712 * - \ref SRAM0_MODULE
713 * - \ref SRAM1_MODULE
714 * - \ref SRAM2_MODULE
715 * - \ref GPA_MODULE
716 * - \ref GPB_MODULE
717 * - \ref GPC_MODULE
718 * - \ref GPD_MODULE
719 * - \ref GPE_MODULE
720 * - \ref GPF_MODULE
721 * - \ref GPG_MODULE
722 * - \ref GPH_MODULE
723 * - \ref WDT_MODULE
724 * - \ref WWDT_MODULE
725 * - \ref EWDT_MODULE
726 * - \ref EWWDT_MODULE
727 * - \ref RTC_MODULE
728 * - \ref TMR0_MODULE
729 * - \ref TMR1_MODULE
730 * - \ref TMR2_MODULE
731 * - \ref TMR3_MODULE
732 * - \ref TMR4_MODULE
733 * - \ref TMR5_MODULE
734 * - \ref CLKO_MODULE
735 * - \ref ACMP01_MODULE
736 * - \ref I2C0_MODULE
737 * - \ref I2C1_MODULE
738 * - \ref I2C2_MODULE
739 * - \ref QSPI0_MODULE
740 * - \ref SPI0_MODULE
741 * - \ref SPI1_MODULE
742 * - \ref SPI2_MODULE
743 * - \ref SPI3_MODULE
744 * - \ref UART0_MODULE
745 * - \ref UART1_MODULE
746 * - \ref UART2_MODULE
747 * - \ref UART3_MODULE
748 * - \ref UART4_MODULE
749 * - \ref UART5_MODULE
750 * - \ref TAMPER_MODULE
751 * - \ref CAN0_MODULE
752 * - \ref OTG_MODULE
753 * - \ref USBD_MODULE
754 * - \ref EADC_MODULE
755 * - \ref I2S0_MODULE
756 * - \ref SC0_MODULE
757 * - \ref SC1_MODULE
758 * - \ref SC2_MODULE
759 * - \ref USCI0_MODULE
760 * - \ref USCI1_MODULE
761 * - \ref DAC_MODULE
762 * - \ref EPWM0_MODULE
763 * - \ref EPWM1_MODULE
764 * - \ref BPWM0_MODULE
765 * - \ref BPWM1_MODULE
766 * - \ref QEI0_MODULE
767 * - \ref QEI1_MODULE
768 * - \ref QEI0_MODULE
769 * - \ref LCD_MODULE
770 * - \ref LCDCP_MODULE
771 * - \ref TRNG_MODULE
772 * - \ref ECAP0_MODULE
773 * - \ref ECAP1_MODULE
774 * @return None
775 * @details This function is used to enable module clock.
776 */
CLK_EnableModuleClock(uint32_t u32ModuleIdx)777 void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
778 {
779 uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL;
780
781 u32TmpVal = (1UL << MODULE_IP_EN_Pos(u32ModuleIdx));
782 u32TmpAddr = (uint32_t)&CLK->AHBCLK;
783 u32TmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL));
784
785 *(volatile uint32_t *)u32TmpAddr |= u32TmpVal;
786 }
787
788 /**
789 * @brief Disable module clock
790 * @param[in] u32ModuleIdx is module index
791 * - \ref PDMA0_MODULE
792 * - \ref PDMA1_MODULE
793 * - \ref ISP_MODULE
794 * - \ref EBI_MODULE
795 * - \ref SDH0_MODULE
796 * - \ref CRC_MODULE
797 * - \ref CRPT_MODULE
798 * - \ref KS_MODULE
799 * - \ref TRACE_MODULE
800 * - \ref USBH_MODULE
801 * - \ref SRAM0_MODULE
802 * - \ref SRAM1_MODULE
803 * - \ref SRAM2_MODULE
804 * - \ref GPA_MODULE
805 * - \ref GPB_MODULE
806 * - \ref GPC_MODULE
807 * - \ref GPD_MODULE
808 * - \ref GPE_MODULE
809 * - \ref GPF_MODULE
810 * - \ref GPG_MODULE
811 * - \ref GPH_MODULE
812 * - \ref WDT_MODULE
813 * - \ref WWDT_MODULE
814 * - \ref EWDT_MODULE
815 * - \ref EWWDT_MODULE
816 * - \ref RTC_MODULE
817 * - \ref TMR0_MODULE
818 * - \ref TMR1_MODULE
819 * - \ref TMR2_MODULE
820 * - \ref TMR3_MODULE
821 * - \ref TMR4_MODULE
822 * - \ref TMR5_MODULE
823 * - \ref CLKO_MODULE
824 * - \ref ACMP01_MODULE
825 * - \ref I2C0_MODULE
826 * - \ref I2C1_MODULE
827 * - \ref I2C2_MODULE
828 * - \ref QSPI0_MODULE
829 * - \ref SPI0_MODULE
830 * - \ref SPI1_MODULE
831 * - \ref SPI2_MODULE
832 * - \ref SPI3_MODULE
833 * - \ref UART0_MODULE
834 * - \ref UART1_MODULE
835 * - \ref UART2_MODULE
836 * - \ref UART3_MODULE
837 * - \ref UART4_MODULE
838 * - \ref UART5_MODULE
839 * - \ref TAMPER_MODULE
840 * - \ref CAN0_MODULE
841 * - \ref OTG_MODULE
842 * - \ref USBD_MODULE
843 * - \ref EADC_MODULE
844 * - \ref I2S0_MODULE
845 * - \ref SC0_MODULE
846 * - \ref SC1_MODULE
847 * - \ref SC2_MODULE
848 * - \ref USCI0_MODULE
849 * - \ref USCI1_MODULE
850 * - \ref DAC_MODULE
851 * - \ref EPWM0_MODULE
852 * - \ref EPWM1_MODULE
853 * - \ref BPWM0_MODULE
854 * - \ref BPWM1_MODULE
855 * - \ref QEI0_MODULE
856 * - \ref QEI1_MODULE
857 * - \ref QEI0_MODULE
858 * - \ref LCD_MODULE
859 * - \ref LCDCP_MODULE
860 * - \ref TRNG_MODULE
861 * - \ref ECAP0_MODULE
862 * - \ref ECAP1_MODULE
863 * @return None
864 * @details This function is used to disable module clock.
865 */
CLK_DisableModuleClock(uint32_t u32ModuleIdx)866 void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
867 {
868 uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL;
869
870 u32TmpVal = ~(1UL << MODULE_IP_EN_Pos(u32ModuleIdx));
871 u32TmpAddr = (uint32_t)&CLK->AHBCLK;
872 u32TmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL));
873
874 *(uint32_t *)u32TmpAddr &= u32TmpVal;
875 }
876
877
878 /**
879 * @brief Set PLL frequency
880 * @param[in] u32PllClkSrc is PLL clock source. Including :
881 * - \ref CLK_PLLCTL_PLLSRC_HXT
882 * - \ref CLK_PLLCTL_PLLSRC_HIRC
883 * @param[in] u32PllFreq is PLL frequency. The range of u32PllFreq is 24 MHz ~ 200 MHz.
884 * @return PLL frequency
885 * @details This function is used to configure PLLCTL register to set specified PLL frequency. \n
886 * The register write-protection function should be disabled before using this function.
887 */
CLK_EnablePLL(uint32_t u32PllClkSrc,uint32_t u32PllFreq)888 uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
889 {
890 uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32PllClk;
891 uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR;
892
893 /* Disable PLL first to avoid unstable when setting PLL */
894 CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;
895
896 /* PLL source clock is from HXT */
897 if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT)
898 {
899 /* Enable HXT clock */
900 CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk;
901
902 /* Wait for HXT clock ready */
903 CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
904
905 /* Select PLL source clock from HXT */
906 u32PllSrcClk = __HXT;
907 }
908
909 /* PLL source clock is from HIRC */
910 else
911 {
912 /* Enable HIRC clock */
913 CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
914
915 /* Wait for HIRC clock ready */
916 CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
917
918 /* Select PLL source clock from HIRC */
919 u32PllSrcClk = __HIRC;
920 }
921
922 /* Check PLL frequency range */
923 /* Constraint 1: 24MHz < FOUT < 200MHz */
924 if((u32PllFreq <= FREQ_200MHZ) && (u32PllFreq >= FREQ_24MHZ))
925 {
926
927 /* Select "NO" according to request frequency */
928 if((u32PllFreq < FREQ_48MHZ) && (u32PllFreq >= FREQ_24MHZ))
929 {
930 u32NO = 3UL;
931 u32PllFreq = u32PllFreq << 2;
932 }
933 else if((u32PllFreq < FREQ_96MHZ) && (u32PllFreq >= FREQ_48MHZ))
934 {
935 u32NO = 1UL;
936 u32PllFreq = u32PllFreq << 1;
937 }
938 else
939 {
940 u32NO = 0UL;
941 }
942
943 /* u32NR start from 3 to avoid calculation overflow */
944 u32NR = 3UL;
945
946 /* Find best solution */
947 u32Min = (uint32_t) - 1; /* initial u32Min to max value of uint32_t (0xFFFFFFFF) */
948 u32MinNR = 0UL;
949 u32MinNF = 0UL;
950
951 for(; u32NR <= 32UL; u32NR++) /* max NR = 32 since NR = INDIV+1 and INDIV = 0~31 */
952 {
953 u32Tmp = u32PllSrcClk / u32NR; /* FREF = FIN/NR */
954 if((u32Tmp >= FREQ_2MHZ) && (u32Tmp <= FREQ_8MHZ)) /* Constraint 2: 2MHz < FREF < 8MHz. */
955 {
956 for(u32NF = 2UL; u32NF <= 513UL; u32NF++) /* NF = 2~513 since NF = FBDIV+2 and FBDIV = 0~511 */
957 {
958 u32Tmp2 = (u32Tmp * u32NF) << 1; /* FVCO = FREF*2*NF */
959 if((u32Tmp2 >= FREQ_96MHZ) && (u32Tmp2 <= FREQ_200MHZ)) /* Constraint 3: 96MHz < FVCO < 200MHz */
960 {
961 u32Tmp3 = (u32Tmp2 > u32PllFreq) ? u32Tmp2 - u32PllFreq : u32PllFreq - u32Tmp2;
962 if(u32Tmp3 < u32Min)
963 {
964 u32Min = u32Tmp3;
965 u32MinNR = u32NR;
966 u32MinNF = u32NF;
967
968 /* Break when get good results */
969 if(u32Min == 0UL)
970 {
971 break;
972 }
973 }
974 }
975 }
976 }
977 }
978
979 /* Enable and apply new PLL setting. */
980 CLK->PLLCTL = u32PllClkSrc |
981 (u32NO << CLK_PLLCTL_OUTDIV_Pos) |
982 ((u32MinNR - 1UL) << CLK_PLLCTL_INDIV_Pos) |
983 ((u32MinNF - 2UL) << CLK_PLLCTL_FBDIV_Pos);
984
985 /* Actual PLL output clock frequency. FOUT = (FIN/NR)*2*NF*(1/NO) */
986 u32PllClk = u32PllSrcClk / ((u32NO + 1UL) * u32MinNR) * (u32MinNF << 1);
987
988 }
989 else
990 {
991 /* Apply default PLL setting and return */
992 CLK->PLLCTL = u32PllClkSrc | CLK_PLLCTL_48MHz_HXT;
993
994 /* Actual PLL output clock frequency */
995 u32PllClk = FREQ_48MHZ;
996 }
997
998 /* Wait for PLL clock stable */
999 CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
1000
1001 /* Return actual PLL output clock frequency */
1002 return u32PllClk;
1003 }
1004
1005 /**
1006 * @brief Disable PLL
1007 * @param None
1008 * @return None
1009 * @details This function set PLL in Power-down mode. \n
1010 * The register write-protection function should be disabled before using this function.
1011 */
CLK_DisablePLL(void)1012 void CLK_DisablePLL(void)
1013 {
1014 CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;
1015 }
1016
1017 /**
1018 * @brief This function check selected clock source status
1019 * @param[in] u32ClkMask is selected clock source. Including :
1020 * - \ref CLK_STATUS_HXTSTB_Msk
1021 * - \ref CLK_STATUS_LXTSTB_Msk
1022 * - \ref CLK_STATUS_HIRCSTB_Msk
1023 * - \ref CLK_STATUS_LIRCSTB_Msk
1024 * - \ref CLK_STATUS_PLLSTB_Msk
1025 * - \ref CLK_STATUS_HIRC48STB_Msk
1026 * - \ref CLK_STATUS_EXTLXTSTB_Msk
1027 * - \ref CLK_STATUS_LIRC32STB_Msk
1028 * - \ref CLK_STATUS_MIRCSTB_Msk
1029 * @retval 0 clock is not stable
1030 * @retval 1 clock is stable
1031 * @details To wait for clock ready by specified clock source stable flag or timeout (~500ms)
1032 */
CLK_WaitClockReady(uint32_t u32ClkMask)1033 uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
1034 {
1035 int32_t i32TimeOutCnt = 2400000;
1036 uint32_t u32Ret = 1U;
1037
1038 while((CLK->STATUS & u32ClkMask) != u32ClkMask)
1039 {
1040 if(i32TimeOutCnt-- <= 0)
1041 {
1042 u32Ret = 0U;
1043 break;
1044 }
1045 }
1046 return u32Ret;
1047 }
1048
1049 /**
1050 * @brief Enable System Tick counter
1051 * @param[in] u32ClkSrc is System Tick clock source. Including:
1052 * - \ref CLK_CLKSEL0_STCLKSEL_HXT
1053 * - \ref CLK_CLKSEL0_STCLKSEL_LXT
1054 * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2
1055 * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
1056 * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
1057 * - \ref CLK_CLKSEL0_STCLKSEL_HCLK
1058 * @param[in] u32Count is System Tick reload value. It could be 0~0xFFFFFF.
1059 * @return None
1060 * @details This function set System Tick clock source, reload value, enable System Tick counter and interrupt. \n
1061 * The register write-protection function should be disabled before using this function.
1062 */
CLK_EnableSysTick(uint32_t u32ClkSrc,uint32_t u32Count)1063 void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
1064 {
1065 /* Set System Tick counter disabled */
1066 SysTick->CTRL = 0UL;
1067
1068 /* Set System Tick clock source */
1069 if(u32ClkSrc == CLK_CLKSEL0_STCLKSEL_HCLK)
1070 {
1071 SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
1072 }
1073 else
1074 {
1075 CLK->AHBCLK |= CLK_AHBCLK_EXSTCKEN_Msk;
1076 CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
1077 }
1078
1079 /* Set System Tick reload value */
1080 SysTick->LOAD = u32Count;
1081
1082 /* Clear System Tick current value and counter flag */
1083 SysTick->VAL = 0UL;
1084
1085 /* Set System Tick interrupt enabled and counter enabled */
1086 SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk;
1087 }
1088
1089 /**
1090 * @brief Disable System Tick counter
1091 * @param None
1092 * @return None
1093 * @details This function disable System Tick counter.
1094 */
CLK_DisableSysTick(void)1095 void CLK_DisableSysTick(void)
1096 {
1097 /* Set System Tick counter disabled */
1098 SysTick->CTRL = 0UL;
1099 }
1100
1101 /**
1102 * @brief Power-down mode selected
1103 * @param[in] u32PDMode is power down mode index. Including :
1104 * - \ref CLK_PMUCTL_PDMSEL_PD
1105 * - \ref CLK_PMUCTL_PDMSEL_LLPD
1106 * - \ref CLK_PMUCTL_PDMSEL_FWPD
1107 * - \ref CLK_PMUCTL_PDMSEL_ULLPD
1108 * - \ref CLK_PMUCTL_PDMSEL_SPD
1109 * - \ref CLK_PMUCTL_PDMSEL_DPD
1110 * @return None
1111 * @details This function is used to set power-down mode.
1112 */
CLK_SetPowerDownMode(uint32_t u32PDMode)1113 void CLK_SetPowerDownMode(uint32_t u32PDMode)
1114 {
1115 while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk);
1116 CLK->PMUCTL = (CLK->PMUCTL & (~CLK_PMUCTL_PDMSEL_Msk)) | (u32PDMode);
1117 }
1118
1119 /**
1120 * @brief Set Wake-up pin trigger type at Deep Power down mode
1121 * @param[in] u32TriggerType Wake-up pin trigger type
1122 * - \ref CLK_DPDWKPIN_RISING
1123 * - \ref CLK_DPDWKPIN_FALLING
1124 * - \ref CLK_DPDWKPIN_BOTHEDGE
1125 * - \ref CLK_DPDWKPIN1_RISING
1126 * - \ref CLK_DPDWKPIN1_FALLING
1127 * - \ref CLK_DPDWKPIN1_BOTHEDGE
1128 * - \ref CLK_DPDWKPIN2_RISING
1129 * - \ref CLK_DPDWKPIN2_FALLING
1130 * - \ref CLK_DPDWKPIN2_BOTHEDGE
1131 * - \ref CLK_DPDWKPIN3_RISING
1132 * - \ref CLK_DPDWKPIN3_FALLING
1133 * - \ref CLK_DPDWKPIN3_BOTHEDGE
1134 * - \ref CLK_DPDWKPIN4_RISING
1135 * - \ref CLK_DPDWKPIN4_FALLING
1136 * - \ref CLK_DPDWKPIN4_BOTHEDGE
1137 * @return None
1138 * @details This function is used to enable Wake-up pin trigger type.
1139 */
1140
CLK_EnableDPDWKPin(uint32_t u32TriggerType)1141 void CLK_EnableDPDWKPin(uint32_t u32TriggerType)
1142 {
1143 uint32_t u32Pin1, u32Pin2, u32Pin3, u32Pin4;
1144
1145 u32Pin1 = (((u32TriggerType) & 0x03UL) >> CLK_PMUCTL_WKPINEN1_Pos);
1146 u32Pin2 = (((u32TriggerType) & 0x03UL) >> CLK_PMUCTL_WKPINEN2_Pos);
1147 u32Pin3 = (((u32TriggerType) & 0x03UL) >> CLK_PMUCTL_WKPINEN3_Pos);
1148 u32Pin4 = (((u32TriggerType) & 0x03UL) >> CLK_PMUCTL_WKPINEN4_Pos);
1149
1150 while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk);
1151
1152 if(u32Pin1)
1153 {
1154 CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN1_Msk)) | u32TriggerType;
1155 }
1156 else if(u32Pin2)
1157 {
1158 CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN2_Msk)) | u32TriggerType;
1159 }
1160 else if(u32Pin3)
1161 {
1162 CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN3_Msk)) | u32TriggerType;
1163 }
1164 else if(u32Pin4)
1165 {
1166 CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN4_Msk)) | u32TriggerType;
1167 }
1168 else
1169 {
1170 CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN_Msk)) | u32TriggerType;
1171 }
1172 }
1173
1174 /**
1175 * @brief Get power manager wake up source
1176 * @param[in] None
1177 * @return None
1178 * @details This function get power manager wake up source.
1179 */
1180
CLK_GetPMUWKSrc(void)1181 uint32_t CLK_GetPMUWKSrc(void)
1182 {
1183 return (CLK->PMUSTS);
1184 }
1185
1186 /**
1187 * @brief Set specified GPIO as wake up source at Standby Power-down mode
1188 * @param[in] u32Port GPIO port. It could be 0~3.
1189 * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 15.
1190 * @param[in] u32TriggerType Wake-up pin trigger type
1191 * - \ref CLK_SPDWKPIN_RISING
1192 * - \ref CLK_SPDWKPIN_FALLING
1193 * @param[in] u32DebounceEn Standby Power-down mode wake-up pin de-bounce function
1194 * - \ref CLK_SPDWKPIN_DEBOUNCEEN
1195 * - \ref CLK_SPDWKPIN_DEBOUNCEDIS
1196 * @return None
1197 * @details This function is used to set specified GPIO as wake up source at Standby Power-down mode.
1198 */
1199
CLK_EnableSPDWKPin(uint32_t u32Port,uint32_t u32Pin,uint32_t u32TriggerType,uint32_t u32DebounceEn)1200 void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn)
1201 {
1202 uint32_t u32TmpAddr = 0UL;
1203 uint32_t u32TmpVal = 0UL;
1204
1205 /* GPx Stand-by Power-down Wake-up Pin Select */
1206 u32TmpAddr = (uint32_t)&CLK->PASWKCTL;
1207 u32TmpAddr += (0x4UL * u32Port);
1208
1209 u32TmpVal = inpw((uint32_t *)u32TmpAddr);
1210 u32TmpVal = (u32TmpVal & ~(CLK_PASWKCTL_WKPSEL_Msk | CLK_PASWKCTL_PRWKEN_Msk | CLK_PASWKCTL_PFWKEN_Msk | CLK_PASWKCTL_DBEN_Msk | CLK_PASWKCTL_WKEN_Msk)) |
1211 (u32Pin << CLK_PASWKCTL_WKPSEL_Pos) | u32TriggerType | u32DebounceEn | CLK_SPDWKPIN_ENABLE;
1212 outpw((uint32_t *)u32TmpAddr, u32TmpVal);
1213 }
1214
1215 /**
1216 * @brief Get PLL clock frequency
1217 * @param None
1218 * @return PLL frequency
1219 * @details This function get PLL frequency. The frequency unit is Hz.
1220 */
1221
1222 __NONSECURE_ENTRY_WEAK
CLK_GetPLLClockFreq(void)1223 uint32_t CLK_GetPLLClockFreq(void)
1224 {
1225 uint32_t u32PllFreq = 0UL, u32PllReg;
1226 uint32_t u32FIN, u32NF, u32NR, u32NO;
1227 uint8_t au8NoTbl[4] = {1U, 2U, 2U, 4U};
1228
1229 u32PllReg = CLK->PLLCTL;
1230
1231 if(u32PllReg & CLK_PLLCTL_PD_Msk)
1232 {
1233 u32PllFreq = 0UL; /* PLL is in power down mode or fix low */
1234 }
1235 else /* PLL is in normal mode */
1236 {
1237 /* PLL source clock */
1238 if(u32PllReg & CLK_PLLCTL_PLLSRC_Msk)
1239 {
1240 u32FIN = __HIRC; /* PLL source clock from HIRC */
1241 }
1242 else
1243 {
1244 u32FIN = __HXT; /* PLL source clock from HXT */
1245 }
1246
1247 /* Calculate PLL frequency */
1248 if(u32PllReg & CLK_PLLCTL_BP_Msk)
1249 {
1250 u32PllFreq = u32FIN; /* PLL is in bypass mode */
1251 }
1252 else
1253 {
1254 /* PLL is output enabled in normal work mode */
1255 u32NO = au8NoTbl[((u32PllReg & CLK_PLLCTL_OUTDIV_Msk) >> CLK_PLLCTL_OUTDIV_Pos)];
1256 u32NF = ((u32PllReg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2UL;
1257 u32NR = ((u32PllReg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos) + 1UL;
1258
1259 /* u32FIN is shifted 2 bits to avoid overflow */
1260 u32PllFreq = (((u32FIN >> 2) * (u32NF << 1)) / (u32NR * u32NO) << 2);
1261 }
1262 }
1263
1264 return u32PllFreq;
1265 }
1266
1267 /**
1268 * @brief Get selected module clock source
1269 * @param[in] u32ModuleIdx is module index.
1270 * - \ref SDH0_MODULE
1271 * - \ref USBH_MODULE
1272 * - \ref WDT_MODULE
1273 * - \ref WWDT_MODULE
1274 * - \ref EWDT_MODULE
1275 * - \ref EWWDT_MODULE
1276 * - \ref LCD_MODULE
1277 * - \ref LCDCP_MODULE
1278 * - \ref RTC_MODULE
1279 * - \ref TMR0_MODULE
1280 * - \ref TMR1_MODULE
1281 * - \ref TMR2_MODULE
1282 * - \ref TMR3_MODULE
1283 * - \ref TMR4_MODULE
1284 * - \ref TMR5_MODULE
1285 * - \ref CLKO_MODULE
1286 * - \ref QSPI0_MODULE
1287 * - \ref SPI0_MODULE
1288 * - \ref SPI1_MODULE
1289 * - \ref SPI2_MODULE
1290 * - \ref SPI3_MODULE
1291 * - \ref UART0_MODULE
1292 * - \ref UART1_MODULE
1293 * - \ref UART2_MODULE
1294 * - \ref UART3_MODULE
1295 * - \ref UART4_MODULE
1296 * - \ref UART5_MODULE
1297 * - \ref OTG_MODULE
1298 * - \ref USBD_MODULE
1299 * - \ref I2S0_MODULE
1300 * - \ref SC0_MODULE
1301 * - \ref SC1_MODULE
1302 * - \ref SC2_MODULE
1303 * - \ref EPWM0_MODULE
1304 * - \ref EPWM1_MODULE
1305 * - \ref BPWM0_MODULE
1306 * - \ref BPWM1_MODULE
1307 * @return Selected module clock source setting
1308 * @details This function get selected module clock source.
1309 */
1310
1311 __NONSECURE_ENTRY_WEAK
CLK_GetModuleClockSource(uint32_t u32ModuleIdx)1312 uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx)
1313 {
1314 uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL;
1315 uint32_t au32SelTbl[4] = {0x0UL, 0x4UL, 0x8UL, 0xCUL};
1316 uint32_t u32RTCCKEN = CLK->APBCLK0 & CLK_APBCLK0_RTCCKEN_Msk;
1317
1318 /* Get clock source selection setting */
1319 if(u32ModuleIdx == RTC_MODULE)
1320 {
1321 if(u32RTCCKEN == 0UL)
1322 {
1323 CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk; /* Enable RTC clock to get LXT clock source */
1324 }
1325
1326 u32TmpVal = ((RTC->LXTCTL & RTC_LXTCTL_RTCCKSEL_Msk) >> RTC_LXTCTL_RTCCKSEL_Pos);
1327
1328 if(u32RTCCKEN == 0UL)
1329 {
1330 CLK->APBCLK0 &= (~CLK_APBCLK0_RTCCKEN_Msk); /* Disable RTC clock if it is disabled before */
1331 }
1332
1333 }
1334 else if(u32ModuleIdx == EPWM0_MODULE)
1335 {
1336 u32TmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk) >> CLK_CLKSEL2_EPWM0SEL_Pos);
1337 }
1338 else if(u32ModuleIdx == EPWM1_MODULE)
1339 {
1340 u32TmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk) >> CLK_CLKSEL2_EPWM1SEL_Pos);
1341 }
1342 else if(u32ModuleIdx == BPWM0_MODULE)
1343 {
1344 u32TmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk) >> CLK_CLKSEL2_BPWM0SEL_Pos);
1345 }
1346 else if(u32ModuleIdx == BPWM1_MODULE)
1347 {
1348 u32TmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk) >> CLK_CLKSEL2_BPWM1SEL_Pos);
1349 }
1350 else if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk)
1351 {
1352 /* Get clock select control register address */
1353 u32TmpAddr = (uint32_t)&CLK->CLKSEL0 + (au32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]);
1354
1355 /* Get clock source selection setting */
1356 u32TmpVal = ((inpw((uint32_t *)u32TmpAddr) & (MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx))) >> MODULE_CLKSEL_Pos(u32ModuleIdx));
1357 }
1358
1359 return u32TmpVal;
1360 }
1361
1362 /**
1363 * @brief Get selected module clock divider number
1364 * @param[in] u32ModuleIdx is module index.
1365 * - \ref SDH0_MODULE
1366 * - \ref USBH_MODULE
1367 * - \ref UART0_MODULE
1368 * - \ref UART1_MODULE
1369 * - \ref UART2_MODULE
1370 * - \ref UART3_MODULE
1371 * - \ref UART4_MODULE
1372 * - \ref UART5_MODULE
1373 * - \ref OTG_MODULE
1374 * - \ref USBD_MODULE
1375 * - \ref SC0_MODULE
1376 * - \ref SC1_MODULE
1377 * - \ref SC2_MODULE
1378 * - \ref EADC_MODULE
1379 * @return Selected module clock divider number setting
1380 * @details This function get selected module clock divider number.
1381 */
1382
1383 __NONSECURE_ENTRY_WEAK
CLK_GetModuleClockDivider(uint32_t u32ModuleIdx)1384 uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx)
1385 {
1386 uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL;
1387 uint32_t au32DivTbl[4] = {0x0UL, 0x4UL, 0x8UL, 0x10UL};
1388
1389 if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk)
1390 {
1391 /* Get clock divider control register address */
1392 u32TmpAddr = (uint32_t)&CLK->CLKDIV0 + (au32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]);
1393 /* Get clock divider number setting */
1394 u32TmpVal = ((inpw((uint32_t *)u32TmpAddr) & (MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx))) >> MODULE_CLKDIV_Pos(u32ModuleIdx));
1395 }
1396
1397 return u32TmpVal;
1398 }
1399
1400
1401 /**@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */
1402
1403 /**@}*/ /* end of group CLK_Driver */
1404
1405 /**@}*/ /* end of group Standard_Driver */
1406
