1/*
2 * Copyright (c) 2017-2023 Arm Limited. All rights reserved.
3 * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company)
4 * or an affiliate of Cypress Semiconductor Corporation. All rights reserved.
5 *
6 * Licensed under the Apache License, Version 2.0 (the "License");
7 * you may not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 *     http://www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an "AS IS" BASIS,
14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19/*********** WARNING: This is an auto-generated file. Do not edit! ***********/
20
21#include "region_defs.h"
22
23LR_CODE S_CODE_START {
24
25    /****  This initial section contains common code for secure binary */
26    ER_TFM_CODE S_CODE_START S_CODE_SIZE {
27        *.o (RESET +First)
28        * (+RO)
29    }
30
31    /**** Unprivileged Secure code start here */
32    TFM_UNPRIV_CODE_START +0 ALIGN 32 {
33        *armlib*
34        *libtfm_sprt.a (+RO)
35    }
36
37    /*
38     * This empty, zero long execution region is here to mark the end address
39     * of TFM unprivileged code.
40     */
41    TFM_UNPRIV_CODE_END +0 ALIGN 32 EMPTY 0x0 {
42    }
43
44    /**** PSA RoT RO part (CODE + RODATA) start here */
45    /*
46     * This empty, zero long execution region is here to mark the start address
47     * of PSA RoT code.
48     */
49    TFM_PSA_CODE_START +0 ALIGN 32 EMPTY 0x0 {
50    }
51
52#ifdef TFM_PARTITION_INTERNAL_TRUSTED_STORAGE
53    TFM_SP_ITS_LINKER +0 ALIGN 32 {
54        *tfm_internal_trusted_storage* (+RO)
55        *(TFM_SP_ITS_ATTR_FN)
56    }
57#endif /* TFM_PARTITION_INTERNAL_TRUSTED_STORAGE */
58
59#ifdef TFM_PARTITION_CRYPTO
60    TFM_SP_CRYPTO_LINKER +0 ALIGN 32 {
61        *tfm_crypto* (+RO)
62        *(TFM_SP_CRYPTO_ATTR_FN)
63    }
64#endif /* TFM_PARTITION_CRYPTO */
65
66#ifdef TFM_PARTITION_PLATFORM
67    TFM_SP_PLATFORM_LINKER +0 ALIGN 32 {
68        *tfm_platform* (+RO)
69        *(TFM_SP_PLATFORM_ATTR_FN)
70    }
71#endif /* TFM_PARTITION_PLATFORM */
72
73#ifdef TFM_PARTITION_INITIAL_ATTESTATION
74    TFM_SP_INITIAL_ATTESTATION_LINKER +0 ALIGN 32 {
75        *tfm_attest* (+RO)
76        *(TFM_SP_INITIAL_ATTESTATION_ATTR_FN)
77    }
78#endif /* TFM_PARTITION_INITIAL_ATTESTATION */
79
80#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
81    TFM_SP_SECURE_TEST_PARTITION_LINKER +0 ALIGN 32 {
82        *tfm_secure_client_service.* (+RO)
83        *test_framework* (+RO)
84        *uart_stdout.* (+RO)
85        *Driver_USART.* (+RO)
86        *arm_uart_drv.* (+RO)
87        *uart_pl011_drv.* (+RO)
88        *uart_cmsdk_drv* (+RO)
89        *secure_suites.* (+RO)
90        *attestation_s_interface_testsuite.* (+RO)
91        *(TFM_SP_SECURE_TEST_PARTITION_ATTR_FN)
92    }
93#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
94
95#ifdef TFM_PARTITION_TEST_CORE_IPC
96    TFM_SP_IPC_SERVICE_TEST_LINKER +0 ALIGN 32 {
97        *ipc_service_test.* (+RO)
98        *(TFM_SP_IPC_SERVICE_TEST_ATTR_FN)
99    }
100#endif /* TFM_PARTITION_TEST_CORE_IPC */
101
102#ifdef TFM_PARTITION_TEST_PS
103    TFM_SP_PS_TEST_LINKER +0 ALIGN 32 {
104        *tfm_ps_test_service.* (+RO)
105        *(TFM_SP_PS_TEST_ATTR_FN)
106    }
107#endif /* TFM_PARTITION_TEST_PS */
108
109    /*
110     * This empty, zero long execution region is here to mark the end address
111     * of PSA RoT code.
112     */
113    TFM_PSA_CODE_END +0 ALIGN 32 EMPTY 0x0 {
114    }
115
116    /**** APPLICATION RoT RO part (CODE + RODATA) start here */
117    /*
118     * This empty, zero long execution region is here to mark the start address
119     * of APP RoT code.
120     */
121    TFM_APP_CODE_START +0 ALIGN 32 EMPTY 0x0 {
122    }
123
124#ifdef TFM_PARTITION_PROTECTED_STORAGE
125    TFM_SP_PS_LINKER +0 ALIGN 32 {
126        *tfm_storage* (+RO)
127        *test_ps_nv_counters.* (+RO)
128        *(TFM_SP_PS_ATTR_FN)
129    }
130#endif /* TFM_PARTITION_PROTECTED_STORAGE */
131
132#ifdef TFM_PARTITION_TEST_CORE_IPC
133    TFM_SP_IPC_CLIENT_TEST_LINKER +0 ALIGN 32 {
134        *ipc_client_test.* (+RO)
135        *(TFM_SP_IPC_CLIENT_TEST_ATTR_FN)
136    }
137#endif /* TFM_PARTITION_TEST_CORE_IPC */
138
139#ifdef TFM_PARTITION_SLIH_TEST
140    TFM_SP_SLIH_TEST_LINKER +0 ALIGN 32 {
141        *tfm_slih_test_service.* (+RO)
142        *timer_cmsdk* (+RO)
143        *(TFM_SP_SLIH_TEST_ATTR_FN)
144    }
145#endif /* TFM_PARTITION_SLIH_TEST */
146
147#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
148    TFM_SP_SECURE_CLIENT_2_LINKER +0 ALIGN 32 {
149        *tfm_secure_client_2.* (+RO)
150        *(TFM_SP_SECURE_CLIENT_2_ATTR_FN)
151    }
152#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
153
154#ifdef TFM_MULTI_CORE_TEST
155    TFM_SP_MULTI_CORE_TEST_LINKER +0 ALIGN 32 {
156        *multi_core_test.* (+RO)
157        *(TFM_SP_MULTI_CORE_TEST_ATTR_FN)
158    }
159#endif /* TFM_MULTI_CORE_TEST */
160
161    /*
162     * This empty, zero long execution region is here to mark the end address
163     * of APP RoT code.
164     */
165    TFM_APP_CODE_END +0 ALIGN 32 EMPTY 0x0 {
166    }
167
168#if defined(S_RAM_CODE_START)
169    /* Flash drivers code that gets copied from Flash */
170    ER_CODE_SRAM S_RAM_CODE_START ALIGN 4 {
171        *libflash_drivers* (+RO)
172        * (.ramfunc)
173    }
174
175    /* This empty, zero long execution region is here to mark the limit
176     * address of the last execution region that is allocated in CODE_SRAM.
177     */
178    ER_CODE_SRAM_WATERMARK +0 EMPTY 0x0 {
179    }
180
181    /* Make sure that the sections allocated in the CODE_SRAM does not exceed
182     * the size of the SRAM available.
183     */
184    ScatterAssert(ImageLimit(ER_CODE_SRAM_WATERMARK) <=
185                  S_RAM_CODE_START + S_RAM_CODE_SIZE)
186#endif
187
188    /**** Base address of secure data area */
189    TFM_SECURE_DATA_START S_DATA_START {
190    }
191
192    /* Shared area between BL2 and runtime to exchange data */
193    TFM_SHARED_DATA +0 ALIGN 32 OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE {
194    }
195
196    /* MSP */
197    ARM_LIB_STACK +0 ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE - 0x8 {
198    }
199
200    STACKSEAL +0 EMPTY 0x8 {
201    }
202
203    /**** APP RoT DATA start here */
204    /*
205     * This empty, zero long execution region is here to mark the start address
206     * of APP RoT RW and Stack.
207     */
208    TFM_APP_RW_STACK_START +0 ALIGN 32 EMPTY 0x0 {
209    }
210
211#ifdef TFM_PARTITION_PROTECTED_STORAGE
212    TFM_SP_PS_LINKER_DATA +0 ALIGN 32 {
213        *tfm_storage* (+RW +ZI)
214        *test_ps_nv_counters.* (+RW +ZI)
215        *(TFM_SP_PS_ATTR_RW)
216        *(TFM_SP_PS_ATTR_ZI)
217    }
218
219    TFM_SP_PS_LINKER_STACK +0 ALIGN 128 EMPTY 0x800 {
220    }
221#endif /* TFM_PARTITION_PROTECTED_STORAGE */
222
223#ifdef TFM_PARTITION_TEST_CORE_IPC
224    TFM_SP_IPC_CLIENT_TEST_LINKER_DATA +0 ALIGN 32 {
225        *ipc_client_test.* (+RW +ZI)
226        *(TFM_SP_IPC_CLIENT_TEST_ATTR_RW)
227        *(TFM_SP_IPC_CLIENT_TEST_ATTR_ZI)
228    }
229
230    TFM_SP_IPC_CLIENT_TEST_LINKER_STACK +0 ALIGN 128 EMPTY 0x0300 {
231    }
232#endif /* TFM_PARTITION_TEST_CORE_IPC */
233
234#ifdef TFM_PARTITION_SLIH_TEST
235    TFM_SP_SLIH_TEST_LINKER_DATA +0 ALIGN 32 {
236        *tfm_slih_test_service.* (+RW +ZI)
237        *timer_cmsdk* (+RW +ZI)
238        *(TFM_SP_SLIH_TEST_ATTR_RW)
239        *(TFM_SP_SLIH_TEST_ATTR_ZI)
240    }
241
242    TFM_SP_SLIH_TEST_LINKER_STACK +0 ALIGN 128 EMPTY 0x0400 {
243    }
244#endif /* TFM_PARTITION_SLIH_TEST */
245
246#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
247    TFM_SP_SECURE_CLIENT_2_LINKER_DATA +0 ALIGN 32 {
248        *tfm_secure_client_2.* (+RW +ZI)
249        *(TFM_SP_SECURE_CLIENT_2_ATTR_RW)
250        *(TFM_SP_SECURE_CLIENT_2_ATTR_ZI)
251    }
252
253    TFM_SP_SECURE_CLIENT_2_LINKER_STACK +0 ALIGN 128 EMPTY 0x300 {
254    }
255#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
256
257#ifdef TFM_MULTI_CORE_TEST
258    TFM_SP_MULTI_CORE_TEST_LINKER_DATA +0 ALIGN 32 {
259        *multi_core_test.* (+RW +ZI)
260        *(TFM_SP_MULTI_CORE_TEST_ATTR_RW)
261        *(TFM_SP_MULTI_CORE_TEST_ATTR_ZI)
262    }
263
264    TFM_SP_MULTI_CORE_TEST_LINKER_STACK +0 ALIGN 128 EMPTY 0x0100 {
265    }
266#endif /* TFM_MULTI_CORE_TEST */
267
268    /*
269     * This empty, zero long execution region is here to mark the end address
270     * of APP RoT RW and Stack.
271     */
272    TFM_APP_RW_STACK_END +0 ALIGN 32 EMPTY 0x0 {
273    }
274
275    ARM_LIB_HEAP +0 ALIGN 8 EMPTY S_HEAP_SIZE {
276    }
277
278    ER_TFM_DATA +0 {
279        * (+RW +ZI)
280    }
281
282    /**** PSA RoT DATA start here */
283    /*
284     * This empty, zero long execution region is here to mark the start address
285     * of PSA RoT RW and Stack.
286     */
287    TFM_PSA_RW_STACK_START +0 ALIGN 32 EMPTY 0x0 {
288    }
289
290#ifdef TFM_PARTITION_INTERNAL_TRUSTED_STORAGE
291    TFM_SP_ITS_LINKER_DATA +0 ALIGN 32 {
292        *tfm_internal_trusted_storage* (+RW +ZI)
293        *(TFM_SP_ITS_ATTR_RW)
294        *(TFM_SP_ITS_ATTR_ZI)
295    }
296
297    TFM_SP_ITS_LINKER_STACK +0 ALIGN 128 EMPTY 0x680 {
298    }
299#endif /* TFM_PARTITION_INTERNAL_TRUSTED_STORAGE */
300
301#ifdef TFM_PARTITION_CRYPTO
302    TFM_SP_CRYPTO_LINKER_DATA +0 ALIGN 32 {
303        *tfm_crypto* (+RW +ZI)
304        *(TFM_SP_CRYPTO_ATTR_RW)
305        *(TFM_SP_CRYPTO_ATTR_ZI)
306    }
307
308    TFM_SP_CRYPTO_LINKER_STACK +0 ALIGN 128 EMPTY 0x2000 {
309    }
310#endif /* TFM_PARTITION_CRYPTO */
311
312#ifdef TFM_PARTITION_PLATFORM
313    TFM_SP_PLATFORM_LINKER_DATA +0 ALIGN 32 {
314        *tfm_platform* (+RW +ZI)
315        *(TFM_SP_PLATFORM_ATTR_RW)
316        *(TFM_SP_PLATFORM_ATTR_ZI)
317    }
318
319    TFM_SP_PLATFORM_LINKER_STACK +0 ALIGN 128 EMPTY 0x0400 {
320    }
321#endif /* TFM_PARTITION_PLATFORM */
322
323#ifdef TFM_PARTITION_INITIAL_ATTESTATION
324    TFM_SP_INITIAL_ATTESTATION_LINKER_DATA +0 ALIGN 32 {
325        *tfm_attest* (+RW +ZI)
326        *(TFM_SP_INITIAL_ATTESTATION_ATTR_RW)
327        *(TFM_SP_INITIAL_ATTESTATION_ATTR_ZI)
328    }
329
330    TFM_SP_INITIAL_ATTESTATION_LINKER_STACK +0 ALIGN 128 EMPTY 0x0A80 {
331    }
332#endif /* TFM_PARTITION_INITIAL_ATTESTATION */
333
334#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
335    TFM_SP_SECURE_TEST_PARTITION_LINKER_DATA +0 ALIGN 32 {
336        *tfm_secure_client_service.* (+RW +ZI)
337        *test_framework* (+RW +ZI)
338        *uart_stdout.* (+RW +ZI)
339        *Driver_USART.* (+RW +ZI)
340        *arm_uart_drv.* (+RW +ZI)
341        *uart_pl011_drv.* (+RW +ZI)
342        *uart_cmsdk_drv* (+RW +ZI)
343        *secure_suites.* (+RW +ZI)
344        *attestation_s_interface_testsuite.* (+RW +ZI)
345        *(TFM_SP_SECURE_TEST_PARTITION_ATTR_RW)
346        *(TFM_SP_SECURE_TEST_PARTITION_ATTR_ZI)
347    }
348
349    TFM_SP_SECURE_TEST_PARTITION_LINKER_STACK +0 ALIGN 128 EMPTY 0x0D00 {
350    }
351#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
352
353#ifdef TFM_PARTITION_TEST_CORE_IPC
354    TFM_SP_IPC_SERVICE_TEST_LINKER_DATA +0 ALIGN 32 {
355        *ipc_service_test.* (+RW +ZI)
356        *(TFM_SP_IPC_SERVICE_TEST_ATTR_RW)
357        *(TFM_SP_IPC_SERVICE_TEST_ATTR_ZI)
358    }
359
360    TFM_SP_IPC_SERVICE_TEST_LINKER_STACK +0 ALIGN 128 EMPTY 0x0220 {
361    }
362#endif /* TFM_PARTITION_TEST_CORE_IPC */
363
364#ifdef TFM_PARTITION_TEST_PS
365    TFM_SP_PS_TEST_LINKER_DATA +0 ALIGN 32 {
366        *tfm_ps_test_service.* (+RW +ZI)
367        *(TFM_SP_PS_TEST_ATTR_RW)
368        *(TFM_SP_PS_TEST_ATTR_ZI)
369    }
370
371    TFM_SP_PS_TEST_LINKER_STACK +0 ALIGN 128 EMPTY 0x500 {
372    }
373#endif /* TFM_PARTITION_TEST_PS */
374
375    /*
376     * This empty, zero long execution region is here to mark the end address
377     * of PSA RoT RW and Stack.
378     */
379    TFM_PSA_RW_STACK_END +0 ALIGN 32 EMPTY 0x0 {
380    }
381
382    /* This empty, zero long execution region is here to mark the limit address
383     * of the last execution region that is allocated in SRAM.
384     */
385    SRAM_WATERMARK +0 EMPTY 0x0 {
386    }
387
388    /* Make sure that the sections allocated in the SRAM does not exceed the
389     * size of the SRAM available.
390     */
391    ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE)
392}
393
394LR_VENEER CMSE_VENEER_REGION_START {
395    /*
396     * Place the CMSE Veneers (containing the SG instruction) in a separate
397     * 32 bytes aligned region so that the SAU can be programmed to
398     * just set this region as Non-Secure Callable.
399     */
400    CMSE_VENEER CMSE_VENEER_REGION_START CMSE_VENEER_REGION_SIZE {
401        *(Veneer$$CMSE)
402    }
403}
404
405LR_NS_PARTITION NS_PARTITION_START {
406    /* Reserved place for NS application.
407     * No code will be placed here, just address of this region is used in the
408     * secure code to configure certain HW components. This generates an empty
409     * execution region description warning during linking.
410     */
411    ER_NS_PARTITION NS_PARTITION_START UNINIT NS_PARTITION_SIZE {
412    }
413}
414
415#ifdef BL2
416LR_SECONDARY_PARTITION SECONDARY_PARTITION_START {
417    /* Reserved place for new image in case of firmware upgrade.
418     * No code will be placed here, just address of this region is used in the
419     * secure code to configure certain HW components. This generates an empty
420     * execution region description warning during linking.
421     */
422    ER_SECONDARY_PARTITION SECONDARY_PARTITION_START \
423        UNINIT SECONDARY_PARTITION_SIZE {
424    }
425}
426#endif /* BL2 */
427