1 /****************************************************************************** 2 * @file dac.h 3 * @version V1.00 4 * @brief DAC driver header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __DAC_H__ 10 #define __DAC_H__ 11 12 #ifdef __cplusplus 13 extern "C" 14 { 15 #endif 16 17 18 /** @addtogroup Standard_Driver Standard Driver 19 @{ 20 */ 21 22 /** @addtogroup DAC_Driver DAC Driver 23 @{ 24 */ 25 26 27 /** @addtogroup DAC_EXPORTED_CONSTANTS DAC Exported Constants 28 @{ 29 */ 30 31 /*---------------------------------------------------------------------------------------------------------*/ 32 /* DAC_CTL Constant Definitions */ 33 /*---------------------------------------------------------------------------------------------------------*/ 34 #define DAC_CTL_LALIGN_RIGHT_ALIGN (0UL<<DAC_CTL_LALIGN_Pos) /*!< Right alignment. */ 35 #define DAC_CTL_LALIGN_LEFT_ALIGN (1UL<<DAC_CTL_LALIGN_Pos) /*!< Left alignment */ 36 37 #define DAC_WRITE_DAT_TRIGGER (0UL) /*!< Write DAC_DAT trigger */ 38 #define DAC_SOFTWARE_TRIGGER (0UL|DAC_CTL_TRGEN_Msk) /*!< Software trigger */ 39 #define DAC_LOW_LEVEL_TRIGGER ((0UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin low level trigger */ 40 #define DAC_HIGH_LEVEL_TRIGGER ((1UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin high level trigger */ 41 #define DAC_FALLING_EDGE_TRIGGER ((2UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin falling edge trigger */ 42 #define DAC_RISING_EDGE_TRIGGER ((3UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin rising edge trigger */ 43 #define DAC_TIMER0_TRIGGER ((2UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 0 trigger */ 44 #define DAC_TIMER1_TRIGGER ((3UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 1 trigger */ 45 #define DAC_TIMER2_TRIGGER ((4UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 2 trigger */ 46 #define DAC_TIMER3_TRIGGER ((5UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 3 trigger */ 47 #define DAC_EPWM0_TRIGGER ((6UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< EPWM0 trigger */ 48 #define DAC_EPWM1_TRIGGER ((7UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< EPWM1 trigger */ 49 50 #define DAC_TRIGGER_MODE_DISABLE (0UL<<DAC_CTL_TRGEN_Pos) /*!< Trigger mode disable */ 51 #define DAC_TRIGGER_MODE_ENABLE (1UL<<DAC_CTL_TRGEN_Pos) /*!< Trigger mode enable */ 52 53 54 /**@}*/ /* end of group DAC_EXPORTED_CONSTANTS */ 55 56 57 /** @addtogroup DAC_EXPORTED_FUNCTIONS DAC Exported Functions 58 @{ 59 */ 60 /*---------------------------------------------------------------------------------------------------------*/ 61 /* DAC Macro Definitions */ 62 /*---------------------------------------------------------------------------------------------------------*/ 63 64 /** 65 * @brief Start the D/A conversion. 66 * @param[in] dac The pointer of the specified DAC module. 67 * @return None 68 * @details User writes SWTRG bit (DAC_SWTRG[0]) to generate one shot pulse and it is cleared to 0 by hardware automatically. 69 */ 70 #define DAC_START_CONV(dac) ((dac)->SWTRG = DAC_SWTRG_SWTRG_Msk) 71 72 /** 73 * @brief Enable DAC data left-aligned. 74 * @param[in] dac The pointer of the specified DAC module. 75 * @return None 76 * @details User has to load data into DAC_DAT[15:4] bits. DAC_DAT[31:16] and DAC_DAT[3:0] are ignored in DAC conversion. 77 */ 78 #define DAC_ENABLE_LEFT_ALIGN(dac) ((dac)->CTL |= DAC_CTL_LALIGN_Msk) 79 80 /** 81 * @brief Enable DAC data right-aligned. 82 * @param[in] dac The pointer of the specified DAC module. 83 * @return None 84 * @details User has to load data into DAC_DAT[11:0] bits, DAC_DAT[31:12] are ignored in DAC conversion. 85 */ 86 #define DAC_ENABLE_RIGHT_ALIGN(dac) ((dac)->CTL &= ~DAC_CTL_LALIGN_Msk) 87 88 /** 89 * @brief Enable output voltage buffer. 90 * @param[in] dac The pointer of the specified DAC module. 91 * @return None 92 * @details The DAC integrates a voltage output buffer that can be used to reduce output impedance and 93 * drive external loads directly without having to add an external operational amplifier. 94 */ 95 #define DAC_ENABLE_BYPASS_BUFFER(dac) ((dac)->CTL |= DAC_CTL_BYPASS_Msk) 96 97 /** 98 * @brief Disable output voltage buffer. 99 * @param[in] dac The pointer of the specified DAC module. 100 * @return None 101 * @details This macro is used to disable output voltage buffer. 102 */ 103 #define DAC_DISABLE_BYPASS_BUFFER(dac) ((dac)->CTL &= ~DAC_CTL_BYPASS_Msk) 104 105 /** 106 * @brief Enable the interrupt. 107 * @param[in] dac The pointer of the specified DAC module. 108 * @param[in] u32Ch Specified DAC channel. 109 * @return None 110 * @details This macro is used to enable DAC interrupt. 111 */ 112 #define DAC_ENABLE_INT(dac, u32Ch) ((dac)->CTL |= DAC_CTL_DACIEN_Msk) 113 114 /** 115 * @brief Disable the interrupt. 116 * @param[in] dac The pointer of the specified DAC module. 117 * @param[in] u32Ch Specified DAC channel 118 * @return None 119 * @details This macro is used to disable DAC interrupt. 120 */ 121 #define DAC_DISABLE_INT(dac, u32Ch) ((dac)->CTL &= ~DAC_CTL_DACIEN_Msk) 122 123 /** 124 * @brief Enable DMA under-run interrupt. 125 * @param[in] dac The pointer of the specified DAC module. 126 * @return None 127 * @details This macro is used to enable DMA under-run interrupt. 128 */ 129 #define DAC_ENABLE_DMAUDR_INT(dac) ((dac)->CTL |= DAC_CTL_DMAURIEN_Msk) 130 131 /** 132 * @brief Disable DMA under-run interrupt. 133 * @param[in] dac The pointer of the specified DAC module. 134 * @return None 135 * @details This macro is used to disable DMA under-run interrupt. 136 */ 137 #define DAC_DISABLE_DMAUDR_INT(dac) ((dac)->CTL &= ~DAC_CTL_DMAURIEN_Msk) 138 139 /** 140 * @brief Enable PDMA mode. 141 * @param[in] dac The pointer of the specified DAC module. 142 * @return None 143 * @details DAC DMA request is generated when a hardware trigger event occurs while DMAEN (DAC_CTL[2]) is set. 144 */ 145 #define DAC_ENABLE_PDMA(dac) ((dac)->CTL |= DAC_CTL_DMAEN_Msk) 146 147 /** 148 * @brief Disable PDMA mode. 149 * @param[in] dac The pointer of the specified DAC module. 150 * @return None 151 * @details This macro is used to disable DMA mode. 152 */ 153 #define DAC_DISABLE_PDMA(dac) ((dac)->CTL &= ~DAC_CTL_DMAEN_Msk) 154 155 /** 156 * @brief Write data for conversion. 157 * @param[in] dac The pointer of the specified DAC module. 158 * @param[in] u32Ch Specified DAC channel. 159 * @param[in] u32Data Decides the data for conversion, valid range are between 0~0xFFF. 160 * @return None 161 * @details 12 bit left alignment: user has to load data into DAC_DAT[15:4] bits. 162 * 12 bit right alignment: user has to load data into DAC_DAT[11:0] bits. 163 */ 164 #define DAC_WRITE_DATA(dac, u32Ch, u32Data) ((dac)->DAT = (u32Data)) 165 166 /** 167 * @brief Read DAC 12-bit holding data. 168 * @param[in] dac The pointer of the specified DAC module. 169 * @param[in] u32Ch Specified DAC channel. 170 * @return Return DAC 12-bit holding data. 171 * @details This macro is used to read DAC_DAT register. 172 */ 173 #define DAC_READ_DATA(dac, u32Ch) ((dac)->DAT) 174 175 /** 176 * @brief Get the busy state of DAC. 177 * @param[in] dac The pointer of the specified DAC module. 178 * @param[in] u32Ch Specified DAC channel. 179 * @retval 0 Idle state. 180 * @retval 1 Busy state. 181 * @details This macro is used to read BUSY bit (DAC_STATUS[8]) to get busy state. 182 */ 183 #define DAC_IS_BUSY(dac, u32Ch) (((dac)->STATUS & DAC_STATUS_BUSY_Msk) >> DAC_STATUS_BUSY_Pos) 184 185 /** 186 * @brief Get the interrupt flag. 187 * @param[in] dac The pointer of the specified DAC module. 188 * @param[in] u32Ch Specified DAC channel. 189 * @retval 0 DAC is in conversion state. 190 * @retval 1 DAC conversion finish. 191 * @details This macro is used to read FINISH bit (DAC_STATUS[0]) to get DAC conversion complete finish flag. 192 */ 193 #define DAC_GET_INT_FLAG(dac, u32Ch) ((dac)->STATUS & DAC_STATUS_FINISH_Msk) 194 195 /** 196 * @brief Get the DMA under-run flag. 197 * @param[in] dac The pointer of the specified DAC module. 198 * @retval 0 No DMA under-run error condition occurred. 199 * @retval 1 DMA under-run error condition occurred. 200 * @details This macro is used to read DMAUDR bit (DAC_STATUS[1]) to get DMA under-run state. 201 */ 202 #define DAC_GET_DMAUDR_FLAG(dac) (((dac)->STATUS & DAC_STATUS_DMAUDR_Msk) >> DAC_STATUS_DMAUDR_Pos) 203 204 /** 205 * @brief This macro clear the interrupt status bit. 206 * @param[in] dac The pointer of the specified DAC module. 207 * @param[in] u32Ch Specified DAC channel. 208 * @return None 209 * @details User writes FINISH bit (DAC_STATUS[0]) to clear DAC conversion complete finish flag. 210 */ 211 #define DAC_CLR_INT_FLAG(dac, u32Ch) ((dac)->STATUS = DAC_STATUS_FINISH_Msk) 212 213 /** 214 * @brief This macro clear the DMA under-run flag. 215 * @param[in] dac The pointer of the specified DAC module. 216 * @return None 217 * @details User writes DMAUDR bit (DAC_STATUS[1]) to clear DMA under-run flag. 218 */ 219 #define DAC_CLR_DMAUDR_FLAG(dac) ((dac)->STATUS = DAC_STATUS_DMAUDR_Msk) 220 221 222 /** 223 * @brief Enable DAC group mode 224 * @param[in] dac The pointer of the specified DAC module. 225 * @return None 226 * @note Only DAC0 has this control bit. 227 * \hideinitializer 228 */ 229 #define DAC_ENABLE_GROUP_MODE(dac) ((dac)->CTL |= DAC_CTL_GRPEN_Msk) 230 231 /** 232 * @brief Disable DAC group mode 233 * @param[in] dac The pointer of the specified DAC module. 234 * @return None 235 * @note Only DAC0 has this control bit. 236 * \hideinitializer 237 */ 238 #define DAC_DISABLE_GROUP_MODE(dac) ((dac)->CTL &= ~DAC_CTL_GRPEN_Msk) 239 240 void DAC_Open(DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc); 241 void DAC_Close(DAC_T *dac, uint32_t u32Ch); 242 uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay); 243 244 /**@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */ 245 246 /**@}*/ /* end of group DAC_Driver */ 247 248 /**@}*/ /* end of group Standard_Driver */ 249 250 #ifdef __cplusplus 251 } 252 #endif 253 254 #endif /* __DAC_H__ */ 255
