1 /* 2 * Copyright (c) 2021-2022, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef __MMIO_DEFS_H__ 9 #define __MMIO_DEFS_H__ 10 11 #ifdef __cplusplus 12 extern "C" { 13 #endif 14 15 #include <stdint.h> 16 #include "tfm_peripherals_def.h" 17 #include "tfm_peripherals_config.h" 18 #include "handle_attr.h" 19 20 /* Allowed named MMIO of this platform */ 21 const uintptr_t partition_named_mmio_list[] = { 22 #if TFM_PERIPHERAL_DCNF_SECURE 23 (uintptr_t)TFM_PERIPHERAL_DCNF, 24 #endif 25 #if TFM_PERIPHERAL_FPU_SECURE 26 (uintptr_t)TFM_PERIPHERAL_FPU, 27 #endif 28 #if TFM_PERIPHERAL_OSCILLATORS_SECURE 29 (uintptr_t)TFM_PERIPHERAL_OSCILLATORS, 30 #endif 31 #if TFM_PERIPHERAL_REGULATORS_SECURE 32 (uintptr_t)TFM_PERIPHERAL_REGULATORS, 33 #endif 34 #if TFM_PERIPHERAL_CLOCK_SECURE 35 (uintptr_t)TFM_PERIPHERAL_CLOCK, 36 #endif 37 #if TFM_PERIPHERAL_POWER_SECURE 38 (uintptr_t)TFM_PERIPHERAL_POWER, 39 #endif 40 #if TFM_PERIPHERAL_RESET_SECURE 41 (uintptr_t)TFM_PERIPHERAL_RESET, 42 #endif 43 #if TFM_PERIPHERAL_SPIM0_SECURE 44 (uintptr_t)TFM_PERIPHERAL_SPIM0, 45 #endif 46 #if TFM_PERIPHERAL_SPIS0_SECURE 47 (uintptr_t)TFM_PERIPHERAL_SPIS0, 48 #endif 49 #if TFM_PERIPHERAL_TWIM0_SECURE 50 (uintptr_t)TFM_PERIPHERAL_TWIM0, 51 #endif 52 #if TFM_PERIPHERAL_TWIS0_SECURE 53 (uintptr_t)TFM_PERIPHERAL_TWIS0, 54 #endif 55 #if TFM_PERIPHERAL_UARTE0_SECURE 56 (uintptr_t)TFM_PERIPHERAL_UARTE0, 57 #endif 58 #if TFM_PERIPHERAL_SPIM1_SECURE 59 (uintptr_t)TFM_PERIPHERAL_SPIM1, 60 #endif 61 #if TFM_PERIPHERAL_SPIS1_SECURE 62 (uintptr_t)TFM_PERIPHERAL_SPIS1, 63 #endif 64 #if TFM_PERIPHERAL_TWIM1_SECURE 65 (uintptr_t)TFM_PERIPHERAL_TWIM1, 66 #endif 67 #if TFM_PERIPHERAL_TWIS1_SECURE 68 (uintptr_t)TFM_PERIPHERAL_TWIS1, 69 #endif 70 #if TFM_PERIPHERAL_UARTE1_SECURE 71 (uintptr_t)TFM_PERIPHERAL_UARTE1, 72 #endif 73 #if TFM_PERIPHERAL_SPIM4_SECURE 74 (uintptr_t)TFM_PERIPHERAL_SPIM4, 75 #endif 76 #if TFM_PERIPHERAL_SPIM2_SECURE 77 (uintptr_t)TFM_PERIPHERAL_SPIM2, 78 #endif 79 #if TFM_PERIPHERAL_SPIS2_SECURE 80 (uintptr_t)TFM_PERIPHERAL_SPIS2, 81 #endif 82 #if TFM_PERIPHERAL_TWIM2_SECURE 83 (uintptr_t)TFM_PERIPHERAL_TWIM2, 84 #endif 85 #if TFM_PERIPHERAL_TWIS2_SECURE 86 (uintptr_t)TFM_PERIPHERAL_TWIS2, 87 #endif 88 #if TFM_PERIPHERAL_UARTE2_SECURE 89 (uintptr_t)TFM_PERIPHERAL_UARTE2, 90 #endif 91 #if TFM_PERIPHERAL_SPIM3_SECURE 92 (uintptr_t)TFM_PERIPHERAL_SPIM3, 93 #endif 94 #if TFM_PERIPHERAL_SPIS3_SECURE 95 (uintptr_t)TFM_PERIPHERAL_SPIS3, 96 #endif 97 #if TFM_PERIPHERAL_TWIM3_SECURE 98 (uintptr_t)TFM_PERIPHERAL_TWIM3, 99 #endif 100 #if TFM_PERIPHERAL_TWIS3_SECURE 101 (uintptr_t)TFM_PERIPHERAL_TWIS3, 102 #endif 103 #if TFM_PERIPHERAL_UARTE3_SECURE 104 (uintptr_t)TFM_PERIPHERAL_UARTE3, 105 #endif 106 #if TFM_PERIPHERAL_SAADC_SECURE 107 (uintptr_t)TFM_PERIPHERAL_SAADC, 108 #endif 109 #if TFM_PERIPHERAL_TIMER0_SECURE 110 (uintptr_t)TFM_PERIPHERAL_TIMER0, 111 #endif 112 #if TFM_PERIPHERAL_TIMER1_SECURE 113 (uintptr_t)TFM_PERIPHERAL_TIMER1, 114 #endif 115 #if TFM_PERIPHERAL_TIMER2_SECURE 116 (uintptr_t)TFM_PERIPHERAL_TIMER2, 117 #endif 118 #if TFM_PERIPHERAL_RTC0_SECURE 119 (uintptr_t)TFM_PERIPHERAL_RTC0, 120 #endif 121 #if TFM_PERIPHERAL_RTC1_SECURE 122 (uintptr_t)TFM_PERIPHERAL_RTC1, 123 #endif 124 #if TFM_PERIPHERAL_DPPI_SECURE 125 (uintptr_t)TFM_PERIPHERAL_DPPI, 126 #endif 127 #if TFM_PERIPHERAL_WDT0_SECURE 128 (uintptr_t)TFM_PERIPHERAL_WDT0, 129 #endif 130 #if TFM_PERIPHERAL_WDT1_SECURE 131 (uintptr_t)TFM_PERIPHERAL_WDT1, 132 #endif 133 #if TFM_PERIPHERAL_COMP_SECURE 134 (uintptr_t)TFM_PERIPHERAL_COMP, 135 #endif 136 #if TFM_PERIPHERAL_LPCOMP_SECURE 137 (uintptr_t)TFM_PERIPHERAL_LPCOMP, 138 #endif 139 #if TFM_PERIPHERAL_EGU0_SECURE 140 (uintptr_t)TFM_PERIPHERAL_EGU0, 141 #endif 142 #if TFM_PERIPHERAL_EGU1_SECURE 143 (uintptr_t)TFM_PERIPHERAL_EGU1, 144 #endif 145 #if TFM_PERIPHERAL_EGU2_SECURE 146 (uintptr_t)TFM_PERIPHERAL_EGU2, 147 #endif 148 #if TFM_PERIPHERAL_EGU3_SECURE 149 (uintptr_t)TFM_PERIPHERAL_EGU3, 150 #endif 151 #if TFM_PERIPHERAL_EGU4_SECURE 152 (uintptr_t)TFM_PERIPHERAL_EGU4, 153 #endif 154 #if TFM_PERIPHERAL_EGU5_SECURE 155 (uintptr_t)TFM_PERIPHERAL_EGU5, 156 #endif 157 #if TFM_PERIPHERAL_PWM0_SECURE 158 (uintptr_t)TFM_PERIPHERAL_PWM0, 159 #endif 160 #if TFM_PERIPHERAL_PWM1_SECURE 161 (uintptr_t)TFM_PERIPHERAL_PWM1, 162 #endif 163 #if TFM_PERIPHERAL_PWM2_SECURE 164 (uintptr_t)TFM_PERIPHERAL_PWM2, 165 #endif 166 #if TFM_PERIPHERAL_PWM3_SECURE 167 (uintptr_t)TFM_PERIPHERAL_PWM3, 168 #endif 169 #if TFM_PERIPHERAL_PDM0_SECURE 170 (uintptr_t)TFM_PERIPHERAL_PDM0, 171 #endif 172 #if TFM_PERIPHERAL_I2S0_SECURE 173 (uintptr_t)TFM_PERIPHERAL_I2S0, 174 #endif 175 #if TFM_PERIPHERAL_IPC_SECURE 176 (uintptr_t)TFM_PERIPHERAL_IPC, 177 #endif 178 #if TFM_PERIPHERAL_QSPI_SECURE 179 (uintptr_t)TFM_PERIPHERAL_QSPI, 180 #endif 181 #if TFM_PERIPHERAL_NFCT_SECURE 182 (uintptr_t)TFM_PERIPHERAL_NFCT, 183 #endif 184 #if TFM_PERIPHERAL_MUTEX_SECURE 185 (uintptr_t)TFM_PERIPHERAL_MUTEX, 186 #endif 187 #if TFM_PERIPHERAL_QDEC0_SECURE 188 (uintptr_t)TFM_PERIPHERAL_QDEC0, 189 #endif 190 #if TFM_PERIPHERAL_QDEC1_SECURE 191 (uintptr_t)TFM_PERIPHERAL_QDEC1, 192 #endif 193 #if TFM_PERIPHERAL_USBD_SECURE 194 (uintptr_t)TFM_PERIPHERAL_USBD, 195 #endif 196 #if TFM_PERIPHERAL_USBREG_SECURE 197 (uintptr_t)TFM_PERIPHERAL_USBREG, 198 #endif 199 #if TFM_PERIPHERAL_NVMC_SECURE 200 (uintptr_t)TFM_PERIPHERAL_NVMC, 201 #endif 202 #if TFM_PERIPHERAL_GPIO0_SECURE 203 (uintptr_t)TFM_PERIPHERAL_GPIO0, 204 #endif 205 #if TFM_PERIPHERAL_P1_SECURE 206 (uintptr_t)TFM_PERIPHERAL_GPIO1, 207 #endif 208 #if TFM_PERIPHERAL_VMC_SECURE 209 (uintptr_t)TFM_PERIPHERAL_VMC, 210 #endif 211 }; 212 213 #ifdef __cplusplus 214 } 215 #endif 216 217 #endif /* __MMIO_DEFS_H__ */ 218
