1 /* 2 * Copyright (c) 2019-2024 Arm Limited. All rights reserved. 3 * 4 * Licensed under the Apache License Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing software 11 * distributed under the License is distributed on an "AS IS" BASIS 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __DEVICE_CFG_H__ 18 #define __DEVICE_CFG_H__ 19 20 /** 21 * \file device_cfg.h 22 * \brief 23 * This is the device configuration file with only used peripherals 24 * defined and configured via the secure and/or non-secure base address. 25 */ 26 27 #include "host_device_cfg.h" 28 #ifdef RSE_HAS_EXPANSION_PERIPHERALS 29 #include "rse_expansion_device_cfg.h" 30 #endif /* RSE_HAS_EXPANSION_PERIPHERALS */ 31 32 #ifdef RSE_DEBUG_UART 33 /* ARM UART CMSDK */ 34 #define DEFAULT_UART_CONTROL 0 35 #define DEFAULT_UART_BAUDRATE 115200 36 #define UART0_CMSDK_S 37 #define UART0_CMSDK_NS 38 #endif /* RSE_DEBUG_UART */ 39 40 /* ARM Memory Protection Controller (MPC) */ 41 #define MPC_VM0_S 42 #define MPC_VM1_S 43 #ifdef RSE_XIP 44 #define MPC_SIC_S 45 #endif /* RSE_XIP */ 46 47 /* ARM Peripheral Protection Controllers (PPC) */ 48 #define PPC_RSE_MAIN0_S 49 #define PPC_RSE_MAIN_EXP0_S 50 #define PPC_RSE_MAIN_EXP1_S 51 #define PPC_RSE_MAIN_EXP2_S 52 #define PPC_RSE_MAIN_EXP3_S 53 #define PPC_RSE_PERIPH0_S 54 #define PPC_RSE_PERIPH1_S 55 #define PPC_RSE_PERIPH_EXP0_S 56 #define PPC_RSE_PERIPH_EXP1_S 57 #define PPC_RSE_PERIPH_EXP2_S 58 #define PPC_RSE_PERIPH_EXP3_S 59 60 /* ARM ATU */ 61 #define ATU_S 62 63 #ifdef RSE_XIP 64 /* ARM SIC */ 65 #define SIC_S 66 #endif 67 68 /* ARM TRAM */ 69 #ifdef RSE_ENABLE_TRAM 70 #define TRAM_S 71 #endif /* RSE_ENABLE_TRAM */ 72 73 /* ARM Integrity Checker */ 74 #define INTEGRITY_CHECKER_S 75 76 /** System Counter Armv8-M */ 77 #define SYSCOUNTER_CNTRL_ARMV8_M_S 78 #define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S 79 80 /** 81 * Arbitrary scaling values for test purposes 82 */ 83 #define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u 84 #define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u 85 #define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u 86 #define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u 87 88 /* Arm GPIO */ 89 #define GPIO0_S 90 #define GPIO1_S 91 92 /* System Timer Armv8-M */ 93 #define SYSTIMER0_ARMV8_M_S 94 95 #define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) 96 97 /* Arm KMU */ 98 #define KMU_S 99 100 /* Arm SAM */ 101 #define SAM_S 102 103 /* Arm LCM */ 104 #define LCM_S 105 106 /* DMA350 defines */ 107 #define DMA350_DMA0_S 108 #define DMA350_DMA0_CHANNEL_COUNT 4 109 #define DMA350_DMA0_CH0_S 110 #define DMA350_DMA0_CH1_S 111 #define DMA350_DMA0_CH2_S 112 #define DMA350_DMA0_CH3_S 113 114 #endif /* __DEVICE_CFG_H__ */ 115
