1#############
2Corstone-1000
3#############
4
5************
6Introduction
7************
8
9The ARM's Corstone-1000 platform is a reference implementation of PSA FF-M
10architecture where NSPE and SPE environments are partitioned/isolated into
11Cortex-A35 and Cortex-M0+ respectively.
12
13Cortex-M0+ acting as Secure Enclave is the Root-of-trust of SoC. Its
14software comprises of two boot loading stages, i.e. Bl1 and Bl2 (based on
15mcuboot) and TF-M as run time software. Cortex-A35, also referred as host,
16is treated as non-secure from the Secure Enclave perspective.
17The Cortex-A35 is brought out of rest by Secure Enclave in aarch64 bit mode,
18and boots the software ecosystem based on linux, u-boot, UEFI run time
19services, TF-A, Secure Partitions and Optee.
20
21The communication between NSPE and SPE is based on PSA IPC protocol running on
22top of the RSE communication protocol. The Corstone-1000 supports only the
23`Embed protocol`, and the ATU support is removed.
24
25The secure enclave subsystem has ARM's CC-312 (Crypto Cell) hardware to
26accelerate cryptographic operations. Additionaly, platform supports Secure Debug
27using SDC-600 as the communication interface between host debugger and platform
28target. The platform has the build option to enable secure debug protocol to
29unlock debug ports during boot time. The protocol is based on ARM's ADAC
30(Authenticated Debug Access Control) standard.
31
32
33***********
34System boot
35***********
36
37- The SoC reset brings Secure Enclave (SE), that is Cortex-M0+, out of rest.
38- SE executes the BL1 ROM code based on mcuboot.
39- BL1 load, verifies and transfer execution to BL2 which is again based on mcuboot.
40- BL2 loads and verifies TF-M and host's initial boot loader image.
41- BL2 transfer the execution to the TF-M.
42- During TF-M initialization, the host is taken out of rest.
43- Hashes of the keys used for image verification are stored in the OTP memory.
44
45*****
46Build
47*****
48
49Platform solution
50=================
51
52The platform binaries are build using Yocto. Below is the user guide:
53
54`Arm Corstone-1000 User Guide`_
55
56Secure Test
57===========
58
59This section can be used to test the secure enclave software independently from
60the host. The below configuration builds the secure enclave binaries with CI test
61frame integrated. On boot, secure enclave softwares stack is brought up, and
62CI tests starts executing at the end of the initialization process. In the
63below configuration, host software support is disabled, and meant only
64to test/verify the secure enclave softwares.
65
66FVP
67---
68
69- Download Corstone-1000 FVP from : `Arm Ecosystem FVPs`_
70- Install FVP by running the shell script.
71- Running of the binary will boot secure enclave software stack and at the end all CI test
72  from tf-m-test along with platform specific tests are executed.
73
74.. code-block:: bash
75
76    cd <tf-m-root>/
77    cmake -B build/ -S . -DCMAKE_BUILD_TYPE=Debug -DTFM_TOOLCHAIN_FILE=<tf-m-root>/toolchain_GNUARM.cmake -DTFM_PLATFORM=arm/corstone1000 -DPLATFORM_IS_FVP=TRUE -DTEST_NS=OFF -DTEST_S=ON -DEXTRA_S_TEST_SUITE_PATH=platform/ext/target/arm/corstone1000/ci_regression_tests/
78    cmake --build build -- install
79    dd conv=notrunc bs=1 if=build/install/outputs/bl1_1.bin of=build/install/outputs/bl1.bin seek=0
80    dd conv=notrunc bs=1 if=build/install/outputs/bl1_provisioning_bundle.bin of=build/install/outputs/bl1.bin seek=40960
81    ./platform/ext/target/arm/corstone1000/create-flash-image.sh build/install/outputs cs1000.bin
82
83    <path-to-FVP-installation>/models/Linux64_GCC-9.3/FVP_Corstone-1000 -C board.flashloader0.fname="none" -C se.trustedBootROMloader.fname="build/install/outputs/bl1.bin" -C board.xnvm_size=64 -C se.trustedSRAM_config=6 -C se.BootROM_config="3" -C board.smsc_91c111.enabled=0  -C board.hostbridge.userNetworking=true --data board.flash0=build/install/outputs/cs1000.bin@0x68000000 -C diagnostics=4 -C disable_visualisation=true -C board.se_flash_size=8192 -C diagnostics=4  -C disable_visualisation=true
84
85FPGA
86----
87
88- Follow the above pointed platform user guide to setup the FPGA board.
89- Use the BL1 generated from the below commands to place it inside FPGA board SD Card.
90- Use the cs1000.bin created from the below commands to place it inside FPGA board SD Card.
91
92.. code-block:: bash
93
94    cd <tf-m-root>/
95    cmake -B build/ -S . -DCMAKE_BUILD_TYPE=Debug -DTFM_TOOLCHAIN_FILE=<tf-m-root>/toolchain_GNUARM.cmake -DTFM_PLATFORM=arm/corstone1000 -DTEST_NS=OFF -DTEST_S=ON -DTEST_S_PS=OFF -DTEST_S_PLATFORM=OFF -DEXTRA_S_TEST_SUITE_PATH=platform/ext/target/arm/corstone1000/ci_regression_tests/
96    cmake --build build -- install
97    dd conv=notrunc bs=1 if=build/install/outputs/bl1_1.bin of=build/install/outputs/bl1.bin seek=0
98    dd conv=notrunc bs=1 if=build/install/outputs/bl1_provisioning_bundle.bin of=build/install/outputs/bl1.bin seek=40960
99    ./platform/ext/target/arm/corstone1000/create-flash-image.sh build/install/outputs cs1000.bin
100    cp build/install/outputs/bl1.bin <path-to-FPGA-SD-CARD>/SOFTWARE/
101    cp build/install/outputs/cs1000.bin <path-to-FPGA-SD-CARD>/SOFTWARE/
102
103FPGA build can not compile all the CI tests into a single build as it exceeds
104the available RAM size. So there is a need to select few tests but not all.
105The above configuration disable build of -DTEST_S_PS and -DTEST_S_PLATFORM.
106Other test configurations are:
107
108- -DTEST_S_ATTESTATION=ON/OFF
109- -DTEST_S_CRYPTO=ON/OFF
110- -DTEST_S_ITS=ON/OFF
111- -DTEST_S_PS=ON/OFF
112- -DTEST_S_PLATFORM=ON/OFF
113
114*Copyright (c) 2021-2024, Arm Limited. All rights reserved.*
115
116.. _Arm Ecosystem FVPs: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps
117.. _Arm Corstone-1000 User Guide: https://corstone1000.docs.arm.com/en/corstone1000-2022.11.23/user-guide.html
118