1 /**************************************************************************//** 2 * @file wdt_reg.h 3 * @version V1.00 4 * @brief WDT register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __WDT_REG_H__ 10 #define __WDT_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 19 /*---------------------- Watch Dog Timer Controller -------------------------*/ 20 /** 21 @addtogroup WDT Watch Dog Timer Controller(WDT) 22 Memory Mapped Structure for WDT Controller 23 @{ 24 */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var WDT_T::CTL 32 * Offset: 0x00 WDT Control Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[1] |RSTEN |WDT Time-out Reset Enable Control (Write Protect) 37 * | | |Setting this bit will enable the WDT time-out reset system function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires. 38 * | | |0 = WDT time-out reset system function Disabled. 39 * | | |1 = WDT time-out reset system function Enabled. 40 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 41 * |[2] |RSTF |WDT Time-out Reset Flag 42 * | | |This bit indicates the system has been reset by WDT time-out reset system event or not. 43 * | | |0 = WDT time-out reset system event did not occur. 44 * | | |1 = WDT time-out reset system event has been occurred. 45 * | | |Note: This bit is cleared by writing 1 to it. 46 * |[3] |IF |WDT Time-out Interrupt Flag 47 * | | |This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval 48 * | | |0 = WDT time-out interrupt event interrupt did not occur. 49 * | | |1 = WDT time-out interrupt interrupt event occurred. 50 * | | |Note: This bit is cleared by writing 1 to it. 51 * |[4] |WKEN |WDT Time-out Wake-up Function Control (Write Protect) 52 * | | |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a event to trigger CPU wake-up trigger event to chip. 53 * | | |0 = Trigger wWake-up trigger event function Disabled if WDT time-out interrupt signal generated. 54 * | | |1 = Trigger Wake-up trigger event function Enabled if WDT time-out interrupt signal generated. 55 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. 56 * | | |Note2: Chip can be woken-up by while WDT time-out interrupt signal generated only if WDT clock source is selected to LIRC or LXT (32 kHz). 57 * |[5] |WKF |WDT Time-out Wake-up Flag (Write Protect) 58 * | | |This bit indicates the WDT time-out event has triggered interrupt chip wake-up or not.flag status of WDT 59 * | | |0 = WDT does not cause chip wake-up. 60 * | | |1 = Chip wake-up from Idle or Power-down mode if when WDT time-out interrupt signal is generated. 61 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. 62 * | | |Note2: This bit is cleared by writing 1 to it. 63 * |[6] |INTEN |WDT Time-out Interrupt Enable Control (Write Protect) 64 * | | |If this bit is enabled, when WDT time-out event occurs, the IF (WDT_CTL[3]) will be set to 1 and the WDT time-out interrupt signal is generated and inform to CPU. 65 * | | |0 = WDT time-out interrupt Disabled. 66 * | | |1 = WDT time-out interrupt Enabled. 67 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 68 * |[7] |WDTEN |WDT Enable Control (Write Protect) 69 * | | |0 = Set WDT counter stop Disabled, and (This action will reset the internal up counter value will be reset also). 70 * | | |1 = Set WDT counter start Enabled. 71 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. 72 * | | |Note2: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period to become active, user can read SYNC (WDT_CTL[30]) to check enable/disable command is completed or not. 73 * | | |Note32: If CWDTEN[2:0] (combined by with Config0[31] and Config0[4:3]) bits is not configure to 0x111, this bit is forced as 1 and user cannot change this bit to 0. 74 * | | |Note3: This bit disabled needs 2 * WDT_CLK. 75 * |[11:8] |TOUTSEL |WDT Time-out Interval Selection (Write Protect) 76 * | | |These three bits select the time-out interval period after for the WDT starts counting. 77 * | | |000 = 2^4 * WDT_CLK. 78 * | | |001 = 2^6 * WDT_CLK. 79 * | | |010 = 2^8 * WDT_CLK. 80 * | | |011 = 2^10 * WDT_CLK. 81 * | | |100 = 2^12 * WDT_CLK. 82 * | | |101 = 2^14 * WDT_CLK. 83 * | | |110 = 2^16 * WDT_CLK. 84 * | | |111 = 2^18 * WDT_CLK. 85 * | | |111 = 2^20 * WDT_CLK. 86 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 87 * |[30] |SYNC |WDT Enable Control SYNC SYNC Flag Indicator (Read Only) 88 * | | |If use to synchronization, software er can check execute enable/disable this flag after enable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is become completed or not active or not.. 89 * | | |SYNC delay is 90 * | | |0 = Set WDTEN bit is WDT enable control synccompletedhronizing is completion. 91 * | | |1 = Set WDTEN bit WDT enable control is synchronizing and not become active yet.. 92 * | | |Note: Perform enable or disable WDTEN bit 93 * | | |This bit enabled needs 2 * WDT_CLK period to become active. 94 * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect) 95 * | | |0 = ICE debug mode acknowledgment affects WDT counting. 96 * | | |WDT up counter will be held while CPU is held by ICE. 97 * | | |1 = ICE debug mode acknowledgment Disabled. 98 * | | |WDT up counter will keep going no matter CPU is held by ICE or not. 99 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 100 * @var WDT_T::ALTCTL 101 * Offset: 0x04 WDT Alternative Control Register 102 * --------------------------------------------------------------------------------------------------- 103 * |Bits |Field |Descriptions 104 * | :----: | :----: | :---- | 105 * |[1:0] |RSTDSEL |WDT Reset Delay Period Selection (Write Protect) 106 * | | |When WDT time-out event happened, user has a time named WDT Reset Delay Period to clear execute WDT counter by setting RSTCNT (WDT_CTL[0]) reset to prevent WDT time-out reset system occurred happened 107 * | | |User can select a suitable setting of RSTDSEL for different application program WDT Reset Delay Period. 108 * | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK. 109 * | | |01 = WDT Reset Delay Period is 130 * WDT_CLK. 110 * | | |10 = WDT Reset Delay Period is 18 * WDT_CLK. 111 * | | |11 = WDT Reset Delay Period is 3 * WDT_CLK. 112 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. 113 * | | |Note2: This register will be reset to 0 if WDT time-out reset system event occurred happened. 114 * @var WDT_T::RSTCNT 115 * Offset: 0x08 WDT Reset Counter Register 116 * --------------------------------------------------------------------------------------------------- 117 * |Bits |Field |Descriptions 118 * | :----: | :----: | :---- | 119 * |[31:0] |RSTCNT |WDT Reset Counter Register 120 * | | |Writing 0x00005AA5 to this register field will reset the internal 18-bit WDT up counter value to 0. 121 * | | |Note: This WDT_RSTCNT is not write protected, but this RSTCNT (WDT_CTL[0]) is write protected. 122 * | | |Note: Perform RSTCNT to reset counter needs 2 * WDT_CLK period to become active. 123 */ 124 __IO uint32_t CTL; /*!< [0x0000] WDT Control Register */ 125 __IO uint32_t ALTCTL; /*!< [0x0004] WDT Alternative Control Register */ 126 __O uint32_t RSTCNT; /*!< [0x0008] WDT Reset Counter Register */ 127 128 } WDT_T; 129 130 /** 131 @addtogroup WDT_CONST WDT Bit Field Definition 132 Constant Definitions for WDT Controller 133 @{ 134 */ 135 136 #define WDT_CTL_RSTEN_Pos (1) /*!< WDT_T::CTL: RSTEN Position */ 137 #define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) /*!< WDT_T::CTL: RSTEN Mask */ 138 139 #define WDT_CTL_RSTF_Pos (2) /*!< WDT_T::CTL: RSTF Position */ 140 #define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) /*!< WDT_T::CTL: RSTF Mask */ 141 142 #define WDT_CTL_IF_Pos (3) /*!< WDT_T::CTL: IF Position */ 143 #define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) /*!< WDT_T::CTL: IF Mask */ 144 145 #define WDT_CTL_WKEN_Pos (4) /*!< WDT_T::CTL: WKEN Position */ 146 #define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) /*!< WDT_T::CTL: WKEN Mask */ 147 148 #define WDT_CTL_WKF_Pos (5) /*!< WDT_T::CTL: WKF Position */ 149 #define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) /*!< WDT_T::CTL: WKF Mask */ 150 151 #define WDT_CTL_INTEN_Pos (6) /*!< WDT_T::CTL: INTEN Position */ 152 #define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) /*!< WDT_T::CTL: INTEN Mask */ 153 154 #define WDT_CTL_WDTEN_Pos (7) /*!< WDT_T::CTL: WDTEN Position */ 155 #define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) /*!< WDT_T::CTL: WDTEN Mask */ 156 157 #define WDT_CTL_TOUTSEL_Pos (8) /*!< WDT_T::CTL: TOUTSEL Position */ 158 #define WDT_CTL_TOUTSEL_Msk (0xful << WDT_CTL_TOUTSEL_Pos) /*!< WDT_T::CTL: TOUTSEL Mask */ 159 160 #define WDT_CTL_SYNC_Pos (30) /*!< WDT_T::CTL: SYNC Position */ 161 #define WDT_CTL_SYNC_Msk (0x1ul << WDT_CTL_SYNC_Pos) /*!< WDT_T::CTL: SYNC Mask */ 162 163 #define WDT_CTL_ICEDEBUG_Pos (31) /*!< WDT_T::CTL: ICEDEBUG Position */ 164 #define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /*!< WDT_T::CTL: ICEDEBUG Mask */ 165 166 #define WDT_ALTCTL_RSTDSEL_Pos (0) /*!< WDT_T::ALTCTL: RSTDSEL Position */ 167 #define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT_T::ALTCTL: RSTDSEL Mask */ 168 169 #define WDT_RSTCNT_RSTCNT_Pos (0) /*!< WDT_T::RSTCNT: RSTCNT Position */ 170 #define WDT_RSTCNT_RSTCNT_Msk (0xfffffffful << WDT_RSTCNT_RSTCNT_Pos) /*!< WDT_T::RSTCNT: RSTCNT Mask */ 171 172 173 /**@}*/ /* WDT_CONST */ 174 /**@}*/ /* end of WDT register group */ 175 /**@}*/ /* end of REGISTER group */ 176 177 #endif /* __WDT_REG_H__ */ 178
