1 /*
2 * Copyright (c) 2017-2021 Arm Limited
3 * Copyright (c) 2021 Nuvoton Technology Corp. All rights reserved.
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 */
17
18 #include "cmsis.h"
19 #include "target_cfg.h"
20 #include "Driver_MPC.h"
21 #include "region_defs.h"
22 #include "tfm_plat_defs.h"
23 #include "region.h"
24 #include "NuMicro.h"
25
26 #ifdef PSA_API_TEST_IPC
27 #define PSA_FF_TEST_SECURE_UART2
28 #endif
29
30 #define ARRAY_SIZE(arr) (sizeof(arr)/sizeof(arr[0]))
31
32 /* The section names come from the scatter file */
33 REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base);
34 REGION_DECLARE(Image$$, ER_VENEER, $$Base);
35 REGION_DECLARE(Image$$, VENEER_ALIGN, $$Limit);
36 #ifdef BL2
37 REGION_DECLARE(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base);
38 #endif /* BL2 */
39
40 const struct memory_region_limits memory_regions = {
41 .non_secure_code_start =
42 (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) +
43 BL2_HEADER_SIZE,
44
45 .non_secure_partition_base =
46 (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base),
47
48 .non_secure_partition_limit =
49 (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) +
50 NS_PARTITION_SIZE - 1,
51
52 .veneer_base = (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base),
53 .veneer_limit = (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit),
54
55 #ifdef BL2
56 .secondary_partition_base =
57 (uint32_t)®ION_NAME(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base),
58
59 .secondary_partition_limit =
60 (uint32_t)®ION_NAME(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base) +
61 SECONDARY_PARTITION_SIZE - 1,
62 #endif /* BL2 */
63 };
64
65 /* Allows software, via SAU, to define the code region as a NSC */
66 #define NSCCFG_CODENSC 1
67
68 /* Import MPC driver */
69 extern ARM_DRIVER_MPC Driver_SRAM1_MPC, Driver_SRAM2_MPC;
70
71 /* Define Peripherals NS address range for the platform */
72 #define PERIPHERALS_BASE_NS_START (0x40000000)
73 #define PERIPHERALS_BASE_NS_END (0x4FFFFFFF)
74
75 /* Enable system reset request for CPU 0 */
76 #define ENABLE_CPU0_SYSTEM_RESET_REQUEST (1U << 4U)
77
78 /* To write into AIRCR register, 0x5FA value must be write to the VECTKEY field,
79 * otherwise the processor ignores the write.
80 */
81 #define SCB_AIRCR_WRITE_MASK ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos))
82
83 /* Debug configuration flags */
84 #define SPNIDEN_SEL_STATUS (0x01u << 7)
85 #define SPNIDEN_STATUS (0x01u << 6)
86 #define SPIDEN_SEL_STATUS (0x01u << 5)
87 #define SPIDEN_STATUS (0x01u << 4)
88 #define NIDEN_SEL_STATUS (0x01u << 3)
89 #define NIDEN_STATUS (0x01u << 2)
90 #define DBGEN_SEL_STATUS (0x01u << 1)
91 #define DBGEN_STATUS (0x01u << 0)
92
93 #define All_SEL_STATUS (SPNIDEN_SEL_STATUS | SPIDEN_SEL_STATUS | \
94 NIDEN_SEL_STATUS | DBGEN_SEL_STATUS)
95
96 struct platform_data_t tfm_peripheral_std_uart = {
97 UART0_BASE+NS_OFFSET,
98 UART0_BASE+NS_OFFSET+0xFFF,
99 PPC_SP_DO_NOT_CONFIGURE,
100 -1
101 };
102
103 struct platform_data_t tfm_peripheral_uart1 = {
104 UART1_BASE,
105 UART1_BASE + 0xFFF,
106 PPC_SP_DO_NOT_CONFIGURE,
107 -1
108 };
109
110 struct platform_data_t tfm_peripheral_timer0 = {
111 TMR01_BASE,
112 TMR01_BASE + 0xFFF,
113 PPC_SP_DO_NOT_CONFIGURE,
114 -1
115 };
116
117 #ifdef PSA_API_TEST_IPC
118
119 /* Below data structure are only used for PSA FF tests, and this pattern is
120 * definitely not to be followed for real life use cases, as it can break
121 * security.
122 */
123
124 struct platform_data_t
125 tfm_peripheral_FF_TEST_UART_REGION = {
126 UART2_BASE_S,
127 UART2_BASE_S + 0xFFF,
128 PPC_SP_APB_PPC_EXP2,
129 CMSDK_UART2_APB_PPC_POS
130 };
131
132 struct platform_data_t
133 tfm_peripheral_FF_TEST_WATCHDOG_REGION = {
134 APB_WATCHDOG_BASE_S,
135 APB_WATCHDOG_BASE_S + 0xFFF,
136 PPC_SP_DO_NOT_CONFIGURE,
137 -1
138 };
139
140 #define FF_TEST_NVMEM_REGION_START 0x102FFC00
141 #define FF_TEST_NVMEM_REGION_END 0x102FFFFF
142 #define FF_TEST_SERVER_PARTITION_MMIO_START 0x3801FC00
143 #define FF_TEST_SERVER_PARTITION_MMIO_END 0x3801FD00
144 #define FF_TEST_DRIVER_PARTITION_MMIO_START 0x3801FE00
145 #define FF_TEST_DRIVER_PARTITION_MMIO_END 0x3801FF00
146
147 struct platform_data_t
148 tfm_peripheral_FF_TEST_NVMEM_REGION = {
149 FF_TEST_NVMEM_REGION_START,
150 FF_TEST_NVMEM_REGION_END,
151 PPC_SP_DO_NOT_CONFIGURE,
152 -1
153 };
154
155 struct platform_data_t
156 tfm_peripheral_FF_TEST_SERVER_PARTITION_MMIO = {
157 FF_TEST_SERVER_PARTITION_MMIO_START,
158 FF_TEST_SERVER_PARTITION_MMIO_END,
159 PPC_SP_DO_NOT_CONFIGURE,
160 -1
161 };
162
163 struct platform_data_t
164 tfm_peripheral_FF_TEST_DRIVER_PARTITION_MMIO = {
165 FF_TEST_DRIVER_PARTITION_MMIO_START,
166 FF_TEST_DRIVER_PARTITION_MMIO_END,
167 PPC_SP_DO_NOT_CONFIGURE,
168 -1
169 };
170 #endif
171
enable_fault_handlers(void)172 enum tfm_plat_err_t enable_fault_handlers(void)
173 {
174 /* Explicitly set secure fault priority to the highest */
175 NVIC_SetPriority(SCU_IRQn, 0);
176
177 return TFM_PLAT_ERR_SUCCESS;
178 }
179
system_reset_cfg(void)180 enum tfm_plat_err_t system_reset_cfg(void)
181 {
182 uint32_t reg_value = SCB->AIRCR;
183
184 /* Clear SCB_AIRCR_VECTKEY value */
185 reg_value &= ~(uint32_t)(SCB_AIRCR_VECTKEY_Msk);
186
187 /* Enable system reset request only to the secure world */
188 reg_value |= (uint32_t)(SCB_AIRCR_WRITE_MASK | SCB_AIRCR_SYSRESETREQS_Msk);
189
190 SCB->AIRCR = reg_value;
191
192 return TFM_PLAT_ERR_SUCCESS;
193 }
194
init_debug(void)195 enum tfm_plat_err_t init_debug(void)
196 {
197
198 #if defined(DAUTH_NONE)
199
200 /* Disable secure and non-secure debug */
201 DPM->NSCTL = 0x5a000000 | DPM_NSCTL_DBGDIS_Msk;
202
203 #elif defined(DAUTH_NS_ONLY)
204
205 /* Disable secure debug */
206 DPM->CTL = 0x5a000000 | DPM_CTL_DBGDIS_Msk;
207
208 #elif defined(DAUTH_FULL)
209 /* By default, all debug is available */
210 /* If secure or all debug is disable, it may need erase whole chip to alow debug again. */
211 #else
212
213 #if !defined(DAUTH_CHIP_DEFAULT)
214 #error "No debug authentication setting is provided."
215 #endif
216
217 /* Set all the debug enable selector bits to 0 */
218
219
220 /* No need to set any enable bits because the value depends on
221 * input signals.
222 */
223 #endif
224
225 return TFM_PLAT_ERR_SUCCESS;
226 }
227
228 /*----------------- NVIC interrupt target state to NS configuration ----------*/
nvic_interrupt_target_state_cfg(void)229 enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void)
230 {
231 /* Target every interrupt to NS; unimplemented interrupts will be WI */
232 for (uint8_t i=0; i<sizeof(NVIC->ITNS)/sizeof(NVIC->ITNS[0]); i++) {
233 NVIC->ITNS[i] = 0xFFFFFFFF;
234 }
235
236 /* Make sure that SCU are targeted to S state */
237 NVIC_ClearTargetState(SCU_IRQn);
238
239 #ifdef SECURE_UART1
240 /* UART1 is a secure peripheral, so its IRQs have to target S state */
241 NVIC_ClearTargetState(UART1_IRQn);
242 #endif
243
244 return TFM_PLAT_ERR_SUCCESS;
245 }
246
247 /*----------------- NVIC interrupt enabling for S peripherals ----------------*/
nvic_interrupt_enable(void)248 enum tfm_plat_err_t nvic_interrupt_enable(void)
249 {
250 NVIC_EnableIRQ(SCU_IRQn);
251
252 #ifdef PSA_FF_TEST_SECURE_UART2
253 # error "Not support PSA_FF_TEST_SECURE_UART2 in M2354"
254 #endif
255
256 return TFM_PLAT_ERR_SUCCESS;
257 }
258
259 /*------------------- SAU/IDAU configuration functions -----------------------*/
260 struct sau_cfg_t {
261 uint32_t RBAR;
262 uint32_t RLAR;
263 bool nsc;
264 };
265
266 const struct sau_cfg_t sau_cfg[] = {
267 {
268 ((uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base)),
269 ((uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) +
270 NS_PARTITION_SIZE - 1),
271 false,
272 },
273 {
274 NS_DATA_START,
275 NS_DATA_LIMIT,
276 false,
277 },
278 {
279 (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base),
280 (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit),
281 true,
282 }
283 };
284
285 #define NR_SAU_INIT_STEP 3
286
sau_and_idau_cfg(void)287 void sau_and_idau_cfg(void)
288 {
289 uint32_t i;
290
291 /* Enables SAU */
292 TZ_SAU_Enable();
293
294 for (i = 0; i < ARRAY_SIZE(sau_cfg); i++) {
295 SAU->RNR = i;
296 SAU->RBAR = sau_cfg[i].RBAR & SAU_RBAR_BADDR_Msk;
297 SAU->RLAR = (sau_cfg[i].RLAR & SAU_RLAR_LADDR_Msk) |
298 (sau_cfg[i].nsc ? SAU_RLAR_NSC_Msk : 0U) |
299 SAU_RLAR_ENABLE_Msk;
300 }
301
302 }
303
304 /*------------------- Memory configuration functions -------------------------*/
305 #ifdef BL2
306 #define NR_MPC_INIT_STEP 7
307 #else
308 #define NR_MPC_INIT_STEP 6
309 #endif
310
mpc_init_cfg(void)311 int32_t mpc_init_cfg(void)
312 {
313 int32_t i;
314
315 SCU->PNSSET[0] = SCU_INIT_PNSSET0_VAL;
316 SCU->PNSSET[1] = SCU_INIT_PNSSET1_VAL;
317 SCU->PNSSET[2] = SCU_INIT_PNSSET2_VAL;
318 SCU->PNSSET[3] = SCU_INIT_PNSSET3_VAL;
319 SCU->PNSSET[4] = SCU_INIT_PNSSET4_VAL;
320 SCU->PNSSET[5] = SCU_INIT_PNSSET5_VAL;
321 SCU->PNSSET[6] = SCU_INIT_PNSSET6_VAL;
322
323 SCU->IONSSET[0] = SCU_INIT_IONSSET0_VAL;
324 SCU->IONSSET[1] = SCU_INIT_IONSSET1_VAL;
325 SCU->IONSSET[2] = SCU_INIT_IONSSET2_VAL;
326 SCU->IONSSET[3] = SCU_INIT_IONSSET3_VAL;
327 SCU->IONSSET[4] = SCU_INIT_IONSSET4_VAL;
328 SCU->IONSSET[5] = SCU_INIT_IONSSET5_VAL;
329 SCU->IONSSET[6] = SCU_INIT_IONSSET6_VAL;
330 SCU->IONSSET[7] = SCU_INIT_IONSSET7_VAL;
331
332 /* Set Non-secure SRAM */
333 for(i = 15; i >= SCU_SECURE_SRAM_SIZE / 16384; i--)
334 {
335 SCU->SRAMNSSET |= (1U << i);
336 }
337
338 /* Set interrupt to non-secure according to PNNSET settings */
339 if(SCU_INIT_PNSSET0_VAL & BIT9) NVIC->ITNS[1] |= BIT22; /* Int of USBH_INT */
340 if(SCU_INIT_PNSSET0_VAL & BIT13) NVIC->ITNS[2] |= BIT0; /* Int of SDHOST0_INT */
341 if(SCU_INIT_PNSSET0_VAL & BIT24) NVIC->ITNS[3] |= BIT2; /* Int of PDMA1_INT */
342 if(SCU_INIT_PNSSET1_VAL & BIT18) NVIC->ITNS[2] |= BIT7; /* Int of CRYPTO */
343 if(SCU_INIT_PNSSET2_VAL & BIT2) NVIC->ITNS[3] |= BIT15; /* Int of EWDT_INT */
344 if(SCU_INIT_PNSSET2_VAL & BIT2) NVIC->ITNS[3] |= BIT16; /* Int of EWWDT_INT */
345 if(SCU_INIT_PNSSET2_VAL & BIT3) NVIC->ITNS[1] |= BIT10; /* Int of EADC0_INT */
346 if(SCU_INIT_PNSSET2_VAL & BIT3) NVIC->ITNS[1] |= BIT11; /* Int of EADC1_INT */
347 if(SCU_INIT_PNSSET2_VAL & BIT3) NVIC->ITNS[1] |= BIT14; /* Int of EADC2_INT */
348 if(SCU_INIT_PNSSET2_VAL & BIT3) NVIC->ITNS[1] |= BIT15; /* Int of EADC3_INT */
349 if(SCU_INIT_PNSSET2_VAL & BIT5) NVIC->ITNS[1] |= BIT12; /* Int of ACMP01_INT */
350 if(SCU_INIT_PNSSET2_VAL & BIT7) NVIC->ITNS[1] |= BIT9; /* Int of DAC_INT */
351 if(SCU_INIT_PNSSET2_VAL & BIT8) NVIC->ITNS[2] |= BIT4; /* Int of I2S0_INT */
352 if(SCU_INIT_PNSSET2_VAL & BIT13) NVIC->ITNS[1] |= BIT23; /* Int of USBOTG_INT */
353 if(SCU_INIT_PNSSET2_VAL & BIT17) NVIC->ITNS[1] |= BIT2; /* Int of TMR2_INT */
354 if(SCU_INIT_PNSSET2_VAL & BIT17) NVIC->ITNS[1] |= BIT3; /* Int of TMR3_INT */
355 if(SCU_INIT_PNSSET2_VAL & BIT18) NVIC->ITNS[3] |= BIT18; /* Int of TMR4_INT */
356 if(SCU_INIT_PNSSET2_VAL & BIT18) NVIC->ITNS[3] |= BIT19; /* Int of TMR5_INT */
357 if(SCU_INIT_PNSSET2_VAL & BIT24) NVIC->ITNS[0] |= BIT25; /* Int of EPWM0_P0_INT */
358 if(SCU_INIT_PNSSET2_VAL & BIT24) NVIC->ITNS[0] |= BIT26; /* Int of EPWM0_P1_INT */
359 if(SCU_INIT_PNSSET2_VAL & BIT24) NVIC->ITNS[0] |= BIT27; /* Int of EPWM0_P2_INT */
360 if(SCU_INIT_PNSSET2_VAL & BIT25) NVIC->ITNS[0] |= BIT29; /* Int of EPWM1_P0_INT */
361 if(SCU_INIT_PNSSET2_VAL & BIT25) NVIC->ITNS[0] |= BIT30; /* Int of EPWM1_P1_INT */
362 if(SCU_INIT_PNSSET2_VAL & BIT25) NVIC->ITNS[0] |= BIT31; /* Int of EPWM1_P2_INT */
363 if(SCU_INIT_PNSSET2_VAL & BIT26) NVIC->ITNS[2] |= BIT14; /* Int of BPWM0_INT */
364 if(SCU_INIT_PNSSET2_VAL & BIT27) NVIC->ITNS[2] |= BIT15; /* Int of BPWM1_INT */
365 if(SCU_INIT_PNSSET3_VAL & BIT0) NVIC->ITNS[0] |= BIT22; /* Int of QSPI0_INT */
366 if(SCU_INIT_PNSSET3_VAL & BIT1) NVIC->ITNS[0] |= BIT23; /* Int of SPI0_INT */
367 if(SCU_INIT_PNSSET3_VAL & BIT2) NVIC->ITNS[1] |= BIT19; /* Int of SPI1_INT */
368 if(SCU_INIT_PNSSET3_VAL & BIT3) NVIC->ITNS[1] |= BIT20; /* Int of SPI2_INT */
369 if(SCU_INIT_PNSSET3_VAL & BIT4) NVIC->ITNS[1] |= BIT30; /* Int of SPI3_INT */
370 if(SCU_INIT_PNSSET3_VAL & BIT16) NVIC->ITNS[1] |= BIT4; /* Int of UART0_INT */
371 if(SCU_INIT_PNSSET3_VAL & BIT17) NVIC->ITNS[1] |= BIT5; /* Int of UART1_INT */
372 if(SCU_INIT_PNSSET3_VAL & BIT18) NVIC->ITNS[1] |= BIT16; /* Int of UART2_INT */
373 if(SCU_INIT_PNSSET3_VAL & BIT19) NVIC->ITNS[1] |= BIT17; /* Int of UART3_INT */
374 if(SCU_INIT_PNSSET3_VAL & BIT20) NVIC->ITNS[2] |= BIT10; /* Int of UART4_INT */
375 if(SCU_INIT_PNSSET3_VAL & BIT21) NVIC->ITNS[2] |= BIT11; /* Int of UART5_INT */
376 if(SCU_INIT_PNSSET4_VAL & BIT0) NVIC->ITNS[1] |= BIT6; /* Int of I2C0_INT */
377 if(SCU_INIT_PNSSET4_VAL & BIT1) NVIC->ITNS[1] |= BIT7; /* Int of I2C1_INT */
378 if(SCU_INIT_PNSSET4_VAL & BIT2) NVIC->ITNS[2] |= BIT18; /* Int of I2C2_INT */
379 if(SCU_INIT_PNSSET4_VAL & BIT16) NVIC->ITNS[1] |= BIT26; /* Int of SC0_INT */
380 if(SCU_INIT_PNSSET4_VAL & BIT17) NVIC->ITNS[1] |= BIT27; /* Int of SC1_INT */
381 if(SCU_INIT_PNSSET4_VAL & BIT18) NVIC->ITNS[1] |= BIT28; /* Int of SC2_INT */
382 if(SCU_INIT_PNSSET5_VAL & BIT0) NVIC->ITNS[1] |= BIT24; /* Int of CAN0_INT */
383 if(SCU_INIT_PNSSET5_VAL & BIT16) NVIC->ITNS[2] |= BIT20; /* Int of QEI0_INT */
384 if(SCU_INIT_PNSSET5_VAL & BIT17) NVIC->ITNS[2] |= BIT21; /* Int of QEI1_INT */
385 if(SCU_INIT_PNSSET5_VAL & BIT20) NVIC->ITNS[2] |= BIT22; /* Int of ECAP0_INT */
386 if(SCU_INIT_PNSSET5_VAL & BIT21) NVIC->ITNS[2] |= BIT23; /* Int of ECAP1_INT */
387 if(SCU_INIT_PNSSET5_VAL & BIT25) NVIC->ITNS[3] |= BIT5; /* Int of TRNG_INT */
388 if(SCU_INIT_PNSSET5_VAL & BIT27) NVIC->ITNS[3] |= BIT4; /* Int of LCD_INT */
389 if(SCU_INIT_PNSSET6_VAL & BIT0) NVIC->ITNS[1] |= BIT21; /* Int of USBD_INT */
390 if(SCU_INIT_PNSSET6_VAL & BIT16) NVIC->ITNS[2] |= BIT12; /* Int of USCI0_INT */
391 if(SCU_INIT_PNSSET6_VAL & BIT17) NVIC->ITNS[2] |= BIT13; /* Int of USCI1_INT */
392 if(SCU_INIT_IONSSET_VAL & BIT0) NVIC->ITNS[0] |= BIT16; /* Int of PA */
393 if(SCU_INIT_IONSSET_VAL & BIT1) NVIC->ITNS[0] |= BIT17; /* Int of PB */
394 if(SCU_INIT_IONSSET_VAL & BIT2) NVIC->ITNS[0] |= BIT18; /* Int of PC */
395 if(SCU_INIT_IONSSET_VAL & BIT3) NVIC->ITNS[0] |= BIT19; /* Int of PD */
396 if(SCU_INIT_IONSSET_VAL & BIT4) NVIC->ITNS[0] |= BIT20; /* Int of PE */
397 if(SCU_INIT_IONSSET_VAL & BIT5) NVIC->ITNS[0] |= BIT21; /* Int of PF */
398 if(SCU_INIT_IONSSET_VAL & BIT6) NVIC->ITNS[2] |= BIT8; /* Int of PG */
399 if(SCU_INIT_IONSSET_VAL & BIT7) NVIC->ITNS[2] |= BIT24; /* Int of PH */
400 if(SCU_INIT_IONSSET_VAL & BIT8) NVIC->ITNS[0] |= BIT10; /* Int of EINT0 */
401 if(SCU_INIT_IONSSET_VAL & BIT9) NVIC->ITNS[0] |= BIT11; /* Int of EINT1 */
402 if(SCU_INIT_IONSSET_VAL & BIT10) NVIC->ITNS[0] |= BIT12; /* Int of EINT2 */
403 if(SCU_INIT_IONSSET_VAL & BIT11) NVIC->ITNS[0] |= BIT13; /* Int of EINT3 */
404 if(SCU_INIT_IONSSET_VAL & BIT12) NVIC->ITNS[0] |= BIT14; /* Int of EINT4 */
405 if(SCU_INIT_IONSSET_VAL & BIT13) NVIC->ITNS[0] |= BIT15; /* Int of EINT5 */
406 if(SCU_INIT_IONSSET_VAL & BIT14) NVIC->ITNS[2] |= BIT9; /* Int of EINT6 */
407 if(SCU_INIT_IONSSET_VAL & BIT15) NVIC->ITNS[2] |= BIT25; /* Int of EINT7 */
408
409 /* Enable SCU Int status */
410 SCU->SVIOIEN = (uint32_t)(-1);
411 SCU->PVIOIEN = (uint32_t)(-1);
412 NVIC_EnableIRQ(SCU_IRQn);
413
414 /* Set UART0 for Non-secure */
415 SCU_SET_PNSSET(UART0_Attr);
416
417 /* Set TIMER2 for Non-secure */
418 SCU_SET_PNSSET(TMR23_Attr);
419
420 /* Add barriers to assure the MPC configuration is done before continue
421 * the execution.
422 */
423 __DSB();
424 __ISB();
425
426 return ARM_DRIVER_OK;
427 }
428
429 /*---------------------- PPC configuration functions -------------------------*/
430 #define NR_PPC_INIT_STEP 4
431
ppc_init_cfg(void)432 void ppc_init_cfg(void)
433 {
434 }
435
ppc_configure_to_non_secure(enum ppc_bank_e bank,uint16_t pos)436 void ppc_configure_to_non_secure(enum ppc_bank_e bank, uint16_t pos)
437 {
438 }
439
ppc_configure_to_secure(enum ppc_bank_e bank,uint16_t pos)440 void ppc_configure_to_secure(enum ppc_bank_e bank, uint16_t pos)
441 {
442 }
443
ppc_en_secure_unpriv(enum ppc_bank_e bank,uint16_t pos)444 void ppc_en_secure_unpriv(enum ppc_bank_e bank, uint16_t pos)
445 {
446 }
447
ppc_clr_secure_unpriv(enum ppc_bank_e bank,uint16_t pos)448 void ppc_clr_secure_unpriv(enum ppc_bank_e bank, uint16_t pos)
449 {
450 }
451
ppc_clear_irq(void)452 void ppc_clear_irq(void)
453 {
454 }
455
